US20050272237A1 - Dual damascene integration structure and method for forming improved dual damascene integration structure - Google Patents

Dual damascene integration structure and method for forming improved dual damascene integration structure Download PDF

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US20050272237A1
US20050272237A1 US11/143,831 US14383105A US2005272237A1 US 20050272237 A1 US20050272237 A1 US 20050272237A1 US 14383105 A US14383105 A US 14383105A US 2005272237 A1 US2005272237 A1 US 2005272237A1
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hard
gcib
layer
dual damascene
porous layer
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John Hautala
Greg Book
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TEL Epion Inc
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TEL Epion Inc
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Publication of US20050272237A1 publication Critical patent/US20050272237A1/en
Priority to US12/246,352 priority patent/US20090130861A1/en
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/06—Sources
    • H01J2237/08—Ion sources
    • H01J2237/0812—Ionized cluster beam [ICB] sources
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only

Definitions

  • This invention relates generally to improved dual damascene integration structures for semiconductor integrated circuits utilizing low dielectric constant (low-k) dielectrics, and to methods of forming such structures using low-k dielectrics and the application of gas-cluster ion-beam processing.
  • low-k dielectric constant
  • FIGS. 2A-2F show schematics illustrating in-process structures (identified as 300 A- 300 F) resulting after each step in a conventional “via first” dual damascene ULK integration process.
  • the “via first” process begins with deposition of a sequence of insulator films over the previous metal wiring level (not shown in the figures.)
  • this insulator stack 300 A is comprised of etch stop film 302 , ULK dielectric layer 304 , first hard-mask layer 306 , second hard-mask layer 308 , antireflective coating 310 , and photoresist layer 312 .
  • the etch stop film 302 must have a reasonably low-k value and the ULK dielectric layer 304 must have a high etch rate ratio with respect to the etch stop film 302 . If the prior (underlying) metal wiring layer is copper, then this etch stop film 302 must also be a Cu diffusion barrier.
  • the most commonly used etch stop films for this application are Si 3 N 4 and SiCN.
  • the first hard-mask layer 306 is intended to remain as part of the dual damascene structure after processing to protect the fragile, porous ULK dielectric layer 304 from the effects of a subsequent chemical mechanical polishing (CMP) step.
  • the second hard-mask layer 308 is a material that provides oxidation resistance and enables photo rework through ash removal of the antireflective coating 310 and the photoresist layer 312 .
  • Typical materials used for first hard-mask layer 306 are SiCOH or SiC while SiO 2 and Si 3 N 4 are typically used for second hard-mask layer 308 .
  • the second hard-mask layer 308 is a sacrificial layer and is removed during subsequent CMP of the Cu and barrier materials.
  • the photoresist layer 312 is then imaged in the desired via pattern and then reactive ion etching (RIE) is used to transfer the pattern down through the antireflective coating 310 , hard-mask layers 306 and 308 and through the ULK dielectric layer 304 while stopping on the SiCN etch stop, thus forming via 324 .
  • RIE reactive ion etching
  • any remaining photoresist layer 312 and antireflective coating 310 are removed by plasma ashing with mixtures of oxygen and other gases to obtain structure 300 C.
  • Another prior art alternative is plasma ashing of the resist followed by solvent removal of the antireflective coating layers.
  • RIE polymer on the via sidewalls 314 is traditionally removed by wet cleans. It has been shown that both the oxygen plasma ashing and wet clean processes, which were traditionally used with SiO 2 dielectrics, can damage the porous ULK dielectric layer 304 materials and so are not optimal because they are detrimental to the process and can reduce the reliability and performance of the circuits thus formed.
  • antireflective coating and photoresist materials are next re-applied to the patterned wafer to obtain structure 300 D.
  • a bottom antireflective coating 316 which will fill the etched vias (via 324 , for example) and planarize the surface is applied first.
  • a third hard-mask layer 318 is then applied, which will allow photo rework, and this is followed by a standard antireflective coating 320 and photoresist layer 322 .
  • One prior art alternative to this scheme is to completely remove and then re-apply all anti-reflective coating and photoresist layers during each photo rework operation.
  • FIG. 2E shows the stack (structure 300 E) after imaging the photoresist layer 322 in a desired trench pattern and after transferring through RIE the pattern down through the third hard-mask layer 318 , bottom antireflective coating 316 , second hard-mask layer 308 , first hard-mask layer 306 and partially into the ULK dielectric layer 304 , thus forming a trench 326 .
  • the bottom antireflective coating 316 material should have a slightly faster RIE etch rate than the ULK dielectric layer 304 material or un-etched protrusions “fences” will remain around the via periphery.
  • RIE is used to remove any remaining photoresist layer 322 , antireflective coating 320 , third hard-mask layer 318 , bottom antireflective layer 316 , and to open the underlying etch stop film 302 , thus completing via 324 and obtaining structure 300 F.
  • oxygen RIE processes and any needed wet cleans have been shown to permeate and degrade the porous ULK dielectric layer 304 material, to the detriment of the process and to the reduced reliability and performance of the circuits thus formed.
  • FIGS. 3A-3G show schematics illustrating in-process structures 400 A- 400 G corresponding to stages in the prior art conventional “dual hard-mask” dual damascene ULK integration scheme, a second widely used formation process.
  • the “dual hard-mask” process begins with deposition of a sequence of insulator films over the previous metal wiring level. Similar to the “via first” scheme discussed above, this “dual hard-mask” insulator stack (structure 400 A) is also comprised of an etch stop film 402 , a ULK dielectric layer 404 , a first hard-mask layer 406 , second hard-mask layer 408 , an antireflective coating 410 , and a photoresist layer 412 .
  • the first hard-mask layer 406 in this integration scheme is intended to remain as part of the dual damascene structure after processing to protect the fragile, porous ULK dielectric layer 404 from the effects of subsequent CMP.
  • the second hard-mask layer 408 is a sacrificial layer and is removed during CMP of the Cu and barrier materials.
  • the photoresist layer 412 is then imaged in the desired trench pattern and RIE is used to transfer the pattern down through the antireflective coating 410 and second hard-mask layer 408 , stopping at first hard-mask layer 406 , thus forming trench pattern 414 in the second hard-mask layer 408 in structure 400 B.
  • the remaining photoresist layer 412 and antireflective coating 410 are either removed by plasma ashing with mixtures of oxygen and other gases or alternatively by using wet solvents.
  • antireflective coating 416 and photoresist layer 418 are next re-applied to the patterned wafer to obtain structure 400 D.
  • FIG. 3E shows resultant structure 400 E following imaging of the photoresist layer 418 in the desired via pattern followed by RIE transfer of the pattern down through the antireflective coating 416 , second hard-mask layer 408 , first hard-mask layer 406 , and partially into the ULK dielectric layer 404 , forming partial via 420 .
  • the antireflective coating 416 material should have a similar etch rate to the second hard-mask layer 408 during this process.
  • an ashing or RIE process is then used to remove any remaining photoresist layer 418 and antireflective coating 416 from the workpiece to obtain structure 400 F.
  • the structure 400 G illustrated in FIG. 3G shows that next a RIE process is used to extend the second hard-mask layer's trench pattern 414 through first hard-mask layer 406 and into the ULK dielectric layer 404 , forming trench 424 , while simultaneously completing the via etch and thus opening up the underlying etch stop film at the bottom of the completed via 422 .
  • the second hard-mask layer 408 is partially consumed during this process and is intended to be completely removed during the subsequent barrier and Cu CMP process.
  • the via shape tends to become elongated and to develop a sloped region 426 as also shown in FIG. 3G .
  • a subsequent argon pre-clean process for the Cu barrier and seed layer tends to sputter material from this sloped region 426 into the bottom of the via 422 , which is typically a copper metal layer, and causes contamination and reliability problems.
  • both of these prior art integration schemes utilize multiple hard-masks for processing which are complex and costly.
  • the final insulator dual damascene structure also retains a hard-mask layer which raises the effective k value of the insulator structure and also serves as a focal point for leakage, delamination, and other potential reliability problems.
  • the resulting final structures produced by these processes retain one or more of the hard-mask layers. This raises the effective k value of the insulator structure and is not desirable. There is additional motivation to minimize the use of these hard-mask layers in that every additional material interface is a potential source for electrical leakage, delamination, or other reliability problems.
  • the etched surfaces of the trench and via structure are open to contamination from subsequent process steps. For example conventional wet or dry stripping processes have been shown to contaminate the ULK films.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the present invention uses gas-cluster ion-beam (GCIB) processing and novel integration structures to solve many of the problems described above.
  • GCIB gas-cluster ion-beam
  • gas-clusters are nano-sized aggregates of materials that are gaseous under conditions of standard temperature and pressure. Such gas-clusters typically are comprised of aggregates of from a few to several thousand molecules loosely bound to form the cluster.
  • the clusters can be ionized by electron bombardment or other means, permitting them to be formed into directed beams of controllable energy.
  • Such ions each typically carry positive charges of q ⁇ e (where e is the electronic charge and q is an integer of from one to several representing the charge state of the cluster ion).
  • Non-ionized clusters may also exist within a cluster ion beam.
  • the larger sized cluster ions are often the most useful because of their ability to carry substantial energy per cluster ion, while yet having only modest average energy per molecule of from a fraction of an electron volt to a few tens of electron volts.
  • the clusters disintegrate on impact, with each individual molecule carrying only a small fraction of the total cluster ion energy. Consequently, the impact effects of large cluster ions are substantial, but are limited to a very shallow surface region. This makes cluster ions effective for a variety of surface modification processes, without the tendency to produce deeper subsurface damage characteristic of conventional monomer ion beam processing.
  • Many useful surface processing effects can be achieved by bombarding surfaces with GCIBs. These processing effects include, but are not necessarily limited to, cleaning, smoothing, etching, doping, and film formation or growth.
  • FIG. 1 is a schematic showing the basic elements of a prior art GCIB processing apparatus
  • FIGS. 2A-2F show schematics illustrating stages in the prior art conventional “via first” dual damascene ULK integration scheme
  • FIGS. 3A-3G show schematics illustrating stages in the prior art conventional “dual hard-mask” dual damascene ULK integration scheme
  • FIGS. 4A-4H show schematics illustrating an integration structure for a first embodiment of the invention and for explaining a first method of the invention.
  • FIGS. 5A-5G show schematics illustrating an integration structure for a second embodiment of the invention and for explaining a second method of the invention.
  • FIG. 1 shows a schematic of the basic elements of a typical configuration for a GCIB processing apparatus 100 which may be described as follows: a vacuum vessel 102 is divided into three communicating chambers, a source chamber 104 , an ionization/acceleration chamber 106 , and a processing chamber 108 . The three chambers are evacuated to suitable operating pressures by vacuum pumping systems 146 a , 146 b , and 146 c , respectively.
  • a condensable source gas 112 (for example argon or N 2 ) stored in a gas storage cylinder 111 is admitted under pressure through gas metering valve 113 and gas feed tube 114 into stagnation chamber 116 and is ejected into the substantially lower pressure vacuum through a properly shaped nozzle 110 .
  • a supersonic gas jet 118 results. Cooling, which results from the expansion in the jet, causes a portion of the gas jet 118 to condense into clusters, each comprising from several to several thousand weakly bound atoms or molecules.
  • a gas skimmer aperture 120 partially separates the gas molecules that have not condensed into a cluster jet from the cluster jet so as to minimize pressure in the downstream regions where such higher pressures would be detrimental (e.g., ionizer 122 , high voltage electrodes 126 , and processing chamber 108 ).
  • Suitable condensable source gases 112 include, but are not necessarily limited to argon, nitrogen, carbon dioxide, oxygen, and other gases and mixtures thereof.
  • the ionizer 122 is typically an electron impact ionizer that produces thermoelectrons from one or more incandescent filaments 124 and accelerates and directs the electrons causing them to collide with the gas-clusters in the gas jet 118 , where the jet passes through the ionizer 122 .
  • the electron impact ejects electrons from the clusters, causing a portion the clusters to become positively ionized.
  • Some clusters may have more than one electron ejected and may become multiply ionized.
  • a set of suitably biased high voltage electrodes 126 extracts the cluster ions from the ionizer, forming a beam, and then accelerates them to a desired energy (typically with acceleration potentials of from several hundred V to several tens of kV) and focuses them to form a GCIB 128 .
  • Filament power supply 136 provides filament voltage V f to heat the ionizer filament 124 .
  • Anode power supply 134 provides anode voltage V A to accelerate thermoelectrons emitted from filament 124 to cause them to irradiate the cluster containing gas jet 118 to produce ions.
  • Extraction power supply 138 provides extraction voltage V E to bias a high voltage electrode to extract ions from the ionizing region of ionizer 122 and to form a GCIB 128 .
  • Accelerator power supply 140 provides acceleration voltage V Acc to bias a high voltage electrode with respect to the ionizer 122 so as to result in a total GCIB acceleration potential equal to V Acc .
  • One or more lens power supplies may be provided to bias high voltage electrodes with focusing voltages (V L1 and V L2 for example) to focus the GCIB 128 .
  • a workpiece 152 which may be a semiconductor wafer or other workpiece to be processed by GCIB processing, is held on a workpiece holder 150 , which can be disposed in the path of the GCIB 128 . Since most applications contemplate the processing of large workpieces with spatially uniform results, a scanning system is desirable to uniformly scan the GCIB 128 across large areas to produce spatially homogeneous results.
  • the GCIB 128 is stationary, has a GCIB axis 129 , and the workpiece 152 is mechanically scanned through the GCIB 128 to distribute the effects of the GCIB 128 over a surface of the workpiece 152 .
  • An X-scan actuator 202 provides linear motion of the workpiece holder 150 in the direction of X-scan motion 208 (into and out of the plane of the paper).
  • a Y-scan actuator 204 provides linear motion of the workpiece holder 150 in the direction of Y-scan motion 210 , which is typically orthogonal to the X-scan motion 208 .
  • the combination of X-scanning and Y-scanning motions moves the workpiece 152 , held by the workpiece holder 150 in a raster-like scanning motion through GCIB 128 to cause a uniform (or otherwise programmed) irradiation of a surface of the workpiece 152 by the GCIB 128 for processing of the workpiece 152 .
  • the workpiece holder 150 disposes the workpiece 152 at an angle with respect to the axis of the GCIB 128 so that the GCIB 128 has an angle of beam incidence 206 with respect to the workpiece 152 surface.
  • the angle of beam incidence 206 may be any suitable angle, but is typically 90 degrees or near 90 degrees.
  • the workpiece 152 and the workpiece holder 150 move from the position shown to the alternate position “A” indicated by the designators 152 A and 150 A respectively. Notice that in moving between the two positions, the workpiece 152 is scanned through the GCIB 128 and in both extreme positions, is moved completely out of the path of the GCIB 128 (over-scanned). Though not shown explicitly in FIG. 1 , similar scanning and over-scan is performed in the (typically) orthogonal X-scan motion 208 direction (in and out of the plane of the paper).
  • a beam current sensor 218 is disposed beyond the workpiece holder 150 in the path of the GCIB 128 so as to intercept a sample of the GCIB 128 when the workpiece holder 150 is scanned out of the path of the GCIB 128 .
  • the beam current sensor 218 is typically a faraday cup or the like, closed except for a beam-entry opening, and is typically affixed to the wall of the vacuum vessel 102 with an electrically insulating mount 212 .
  • a controller 220 which may be a microcomputer based controller connects to the X-scan actuator 202 and the Y-scan actuator 204 through electrical cable 216 and controls the X-scan actuator 202 and the Y-scan actuator 204 so as to place the workpiece 152 into or out of the GCIB 128 and to scan the workpiece 152 uniformly relative to the GCIB 128 to achieve desired processing of the workpiece 152 by the GCIB 128 .
  • Controller 220 receives the sampled beam current collected by the beam current sensor 218 by way of lead 214 and thereby monitors the GCIB and controls the GCIB dose received by the workpiece 152 by removing the workpiece 152 from the GCIB 128 when a predetermined desired dose has been delivered.
  • GCIB processes useful at several stages of semiconductor integration include processes for etching, for ashing photoresists and the like, and for densifying and pore sealing of porous ULK dielectrics.
  • SCCM Useful Gasses Gas
  • kV Typical Gas Flow Gas Flow Range V ACC
  • gases such as CF 4 , CHF 3 , 95% O 2 C 2 F 2 , SF 6 , NF 3 , and Mixtures of fluorine- containing gases with O 2 , for example 1-10% NF 3 in 90-99% O 2
  • FIGS. 4A-4G illustrate in-process integration structures 500 A- 500 G resulting from inventive process steps in a first embodiment of the present invention, a method for fabricating the dual damascene integration structure 500 H shown in FIG. 4H incorporating porous ULK dielectrics. None of the suggested dimensions in any of the following embodiments are intended to limit the invention in any manner to such embodiments.
  • a process in accordance with the first embodiment of the invention begins with deposition of a sequence of insulator films over the previous metal wiring level (not shown, but would appear below the stop film layer 502 in structure 500 A.)
  • the insulator stack is comprised of an etch stop film 502 , porous ULK dielectric layer 504 and a hard-mask layer 506 .
  • the etch stop material has the same requirements as previously stated for the prior art processes and therefore is typically composed of a material such as Si 3 N 4 or SiCN.
  • the etch stop film 502 may have a thickness of about 35 nm.
  • the porous ULK dielectric layer 504 may have a thickness (for example) of about 300 nm.
  • the hard-mask layer 506 in this integration scheme does not remain as part of the dual damascene structure after processing. Therefore, relatively higher-k materials such as SiO 2 or Si 3 N 4 may be used for hard-mask layer 506 compared to what would be required in a conventional integration scheme. Since SiO 2 or Si 3 N 4 are also oxidation resistant, photo rework is allowed.
  • the hard-mask layer 506 may have a thickness (for example) of about 40 nm.
  • Suitable hard mask materials include, but are not necessarily limited to SiCOH, SiCN and SiC.
  • the surface of the porous ULK dielectric layer 504 may be densified and pore-sealed by GCIB processing (see Table 3 for typical process parameters.)
  • an antireflective coating 508 and a photoresist layer 510 of types known in the art are applied to insulator stack 500 B.
  • the antireflective coating 508 and photoresist layer 510 will both be employed, but there may be applications wherein antireflective coating is not necessary.
  • the antireflective coating 508 and photoresist layer 510 are collectively referred to herein as a “masking material” layer, however the same term could be applied, in such embodiments, to refer to a photoresist-only layer.
  • the antireflective coating 508 may be (for exemplary purposes) about 40 nm thick and the photoresist layer 510 may be (for example) about 200 nm thick, measured from the upper surface of coating 508 .
  • the antireflective coating 508 may comprise (for example, not for limitation) “AR 40 Anti-Reflectant” and the photoresist layer 510 may comprise (for example, not for limitation) “EpicTM 2210 ArF Photoresist”, both materials supplied commercially by Rohm and Haas Electronic Materials (Phoenix, Ariz.)
  • the resist is then imaged in the desired via pattern and then RIE or preferably GCIB etching (See Table 1 for example process parameters) is used to transfer the pattern down through the antireflective coating 508 , hard-mask layer 506 , and porous ULK dielectric layer 504 , stopping on the etch stop film 502 , thus forming via 512 in resultant structure 500 C.
  • RIE or preferably GCIB etching See Table 1 for example process parameters
  • the remaining photoresist layer 510 and antireflective coating 508 are removed by conventional plasma or GCIB ashing with mixtures of oxygen and other gases (See Table 2 for example process parameters) to obtain structure 500 D.
  • the sidewalls of the etched via 512 in the porous ULK dielectric layer 504 are cleaned and densified and rendered non-porous by the GCIB treatment (See Table 3 for example process parameters), thus avoiding the need for wet cleaning and avoiding the opportunity for contamination that results from wet processing of porous dielectrics.
  • FIG. 4E another masking material layer, comprised of optional bottom antireflective coating 516 and photoresist layer 518 are next applied to the patterned wafer (structure 500 E) as shown.
  • the antireflective coating component of the masking material layer fills the etched vias (via 512 for example) and planarizes the surface prior to the application of photoresist.
  • the bottom antireflective coating 516 and the photoresist layer 518 may similarly be composed of the materials described above. Not including the via filling depth, the bottom antireflective coating 516 material may be (for example) about 200 nm thick.
  • the photoresist layer 518 may be (for example) about 200 nm thick.
  • FIG. 4F shows a structure 500 F resulting from imaging the resist in the desired trench pattern and then RIE or GCIB etch transferring the pattern down through the bottom antireflective coating 516 , hard-mask layer 506 , and partially into the porous ULK dielectric layer 504 , thus forming a trench 520 .
  • the bottom antireflective coat 516 material should have a slightly faster GCIB etch rate than the porous ULK dielectric layer 504 material to avoid un-etched protrusions, “fences”, remaining around the upper surface of the via 512 periphery.
  • an ashing process preferably a GCIB ashing process (See Table 3 for example process parameters) then removes any remaining photoresist layer 518 and bottom antireflective coating 516 from the surface of the workpiece 500 G. This is followed by RIE or GCIB etching to remove the hard-mask layer 506 and to open up the underlying etch stop film 502 to complete the via 512 (See Table 1 for example process parameters.)
  • a final GCIB treatment (See Table 3 for example process parameters) is then used to complete the densification and smoothing of all the exposed ULK dielectric layer surfaces 522 to obtain the first embodiment of the improved dual damascence structure 500 H.
  • FIGS. 5A-5G illustrate in-process structures 600 A- 600 F and a final dual damascene integration structure 600 G using porous ULK dielectrics, formed in accordance with a second embodiment of the present invention, and which is based on initial transfer of a trench pattern into a hard-mask.
  • the process of the second embodiment begins with deposition of a sequence of insulator films over the previous metal wiring level.
  • This insulator stack 600 A is comprised of an etch stop film 602 , a porous ULK dielectric layer 604 and a hard-mask layer 606 .
  • a masking material layer comprised of an optional antireflective coating 608 and photoresist layer 610 are then applied to this insulator stack as also illustrated in this figure.
  • the etch stop material has the same requirements as previously stated for the prior art processes and therefore is typically a material such as Si 3 N 4 or SiCN.
  • the etch stop film 602 may have a thickness (for example) of about 35 nm.
  • the porous ULK dielectric layer 604 may have a thickness (for example) of about 300 nm.
  • the hard-mask layer 606 in this integration scheme does not remain as part of the dual damascene structure after processing. Therefore, relatively higher-k materials such as SiO 2 or Si 3 N 4 may be used for hard-mask layer 606 compared to what would be required in a conventional integration scheme. Since SiO 2 or Si 3 N 4 are also oxidation resistant, photo rework is allowed.
  • the hard-mask layer 606 may have a thickness (for example) of about 80 nm. This thickness is adjustable depending on the relative etch rates of the hard-mask to the ULK and underlying etch stop.
  • Suitable hard mask materials include, but are not necessarily limited to, SiCOH, SiCN and SiC.
  • the antireflective coating 608 may be (for example) about 40 nm thick and the photoresist layer 610 may be (for example) about 200 nm thick.
  • the antireflective coating 608 and the photoresist layer 610 may similarly comprise (for example, not for limitation) the materials discussed above or other known materials. Note that, optionally, prior to formation of the hard-mask layer 606 , the surface of the porous ULK dielectric layer 604 may be densified and pore-sealed by gas cluster ion beam processing (see Table 3 for typical process parameters).
  • FIG. 5B illustrates resultant structure 600 B subsequent to imaging of the photoresist layer 610 in the desired trench pattern and then use of RIE or GCIB etching (See Table 1 for example process parameters) to transfer of the pattern down through the antireflective coating 608 and hard-mask layer 606 , stopping after minimal etching of the porous ULK dielectric layer 604 , thus forming a trench pattern 612 in hard-mask layer 606 .
  • RIE or GCIB etching See Table 1 for example process parameters
  • the remaining masking material layer is removed by a conventional plasma or GCIB ashing process with pure concentrations or mixes of oxygen, nitrogen, hydrogen, argon and other gases (See Table 2 for example process parameters) while simultaneously accomplishing densification of surface 614 of the porous ULK dielectric layer 604 .
  • FIG. 5D another masking material layer composed of optional antireflective coating 616 and photoresist layer 618 are next applied to the patterned wafer (structure 600 D) as shown.
  • the antireflective coating 616 may comprise (for example, not for limitation) “AR 40 Anti-Reflectant” and the photoresist layer 618 may comprise (for example, not for limitation) “EpicTM 2210 ArF Photoresist.”
  • photoresist layer 618 is imaged in the desired via pattern and RIE or GCIB etching is used to transfer the pattern down through the antireflective coating 616 , the hard-mask layer 606 , and partially into the porous ULK dielectric layer 604 .
  • the antireflective coating material should have a similar etch rate to the hard-mask layer 606 during this step (See Table 1 for example process parameters—note that the relative etch rates in the bottom antireflective coat 616 and in the porous ULK dielectric layer 604 is controlled by setting the ratio of NF 3 to O 2 in the gas mixture.)
  • a conventional plasma or preferably GCIB ashing process (See Table 2 for example process parameters) is then used to remove any remaining material of the masking material layer from the workpiece (structure 600 F.)
  • a RIE or GCIB etch process is utilized which extends the hard-mask layer 606 trench pattern 612 into the porous ULK dielectric layer 604 , thus forming trench 624 , while simultaneously completing the via etch and opening up the underlying etch stop at the bottom of the via, thus completing via 610 (See Table 1 for example process parameters).
  • the hard-mask layer 606 is completely removed during this process.
  • another GCIB process is used to smooth and densify and to seal pores of all exposed ULK surfaces 622 (See Table 2 for example process parameters). Note that since GCIB etching is highly directional, the sidewalls of the vias do not develop a shallow slope (they have substantially no slope) as in a conventional RIE process (see FIG. 3G for illustration of this problem in the prior art).
  • utilizing GCIB processing eliminates the need for a hard-mask over a porous ULK dielectric material, since the GCIB process can provide smoothing, densification, and pore sealing of the etched ULK dielectric material.
  • RIE removal of the hard-mask over ULK dielectric results in a roughened porous ULK dielectric surface.
  • CMP removal of the hard-mask over ULK dielectric material can provide smoothing but no densification or pore sealing and therefore the associated wet chemistry degrades the porous ULK dielectric material.
  • Another benefit of this invention is that the number of hard-masks used in the formation of the dual damascene structure is minimized and hard-masks are eliminated in the final etched dual damascene structure. Therefore, the final dual damascene structure has a lower effective k and minimal interfaces that can be sources for leakage, delamination and other reliability problems.
  • the process causes densification and sealing of all porous etched ULK dielectric surfaces such that they are not susceptible to contamination from subsequent processes such CVD or ALD barrier processes.
  • GCIB etching is not subject to micro-loading effects and therefore provides better control of the etched trench depth and shape such that more precise specification of resistance and capacitance can be made to the design community.

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US20090130861A1 (en) 2009-05-21
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