US20050071707A1 - Integrated circuit with bi-modal data strobe - Google Patents

Integrated circuit with bi-modal data strobe Download PDF

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Publication number
US20050071707A1
US20050071707A1 US10/676,648 US67664803A US2005071707A1 US 20050071707 A1 US20050071707 A1 US 20050071707A1 US 67664803 A US67664803 A US 67664803A US 2005071707 A1 US2005071707 A1 US 2005071707A1
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Prior art keywords
signal
data
data strobe
controller
mode
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US10/676,648
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Craig Hampel
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Rambus Inc
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Rambus Inc
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=34377433&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US20050071707(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Rambus Inc filed Critical Rambus Inc
Priority to US10/676,648 priority Critical patent/US20050071707A1/en
Assigned to RAMBUS INC. reassignment RAMBUS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAMPEL, CRAIG E.
Priority to AT04783434T priority patent/ATE367608T1/de
Priority to KR1020117006938A priority patent/KR101108297B1/ko
Priority to DE602004007674.0T priority patent/DE602004007674T3/de
Priority to KR1020067008404A priority patent/KR101110469B1/ko
Priority to JP2006533897A priority patent/JP4783290B2/ja
Priority to PCT/US2004/029186 priority patent/WO2005033958A1/en
Priority to EP04783434.6A priority patent/EP1668523B2/en
Publication of US20050071707A1 publication Critical patent/US20050071707A1/en
Priority to US12/103,640 priority patent/US8352696B2/en
Priority to JP2011050556A priority patent/JP5191555B2/ja
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

Definitions

  • the present invention pertains generally to integrated circuit technologies. More specifically, the present invention pertains to integrated circuit devices with bi-modal data strobes.
  • a source synchronous data strobe serves to compensate for the delays in the transmit path of a device that is transmitting data and the receive path of a device receiving this data.
  • the size of these delays are a function of the speed, and variation in path speed, of a semiconductor device over its operating conditions and manufacturing tolerances.
  • the data strobe interconnect lines between devices are left in a tristate, or quiet state, when responsibility for generating a data strobe is transferred from one device to another.
  • the data strobe does not have a predetermined, constant frequency, but resembles a clock being briefly turned on and off.
  • the data strobe signal suffers from standing wave phenomena. The first edge, and perhaps the first few edges of a data strobe will typically arrive in-phase with respect to the data. However, subsequent edges of the data strobe may shift due to reflections of previous data strobe edges, and therefore will not be in phase with respect to the data. In other words, the data strobe would begin to appear more like a free running clock.
  • a controller for a memory system is coupled to a data strobe bus, a data bus, and a clock bus.
  • the controller includes an output buffer configured to assert a first data strobe signal on the data strobe bus when the output buffer is enabled.
  • the controller also includes a register to store a mode of controller operation.
  • the output buffer is enabled only during transfers from the controller of a first data signal over the data bus when the mode of controller operation is set to a first mode of controller operation.
  • the output buffer is, however, continuously enabled when the mode of controller operation is set to a second mode of controller operation.
  • the controller is configured to receive a clock signal over the clock bus and to clock receipt of a second data signal over the data bus with the clock signal.
  • a memory device is coupled to a data strobe bus, a data bus, and a clock bus.
  • the memory device is configured to receive over the data strobe bus a data strobe signal that is continuously, remotely asserted on the data strobe bus.
  • the memory device is also configured to receive over the data bus a first data signal in conjunction with the data strobe signal and to clock receipt of the first data signal with the data strobe signal.
  • the memory device is further configured to receive a clock signal over the clock bus.
  • the memory device In a first mode of operation, the memory device is configured to transmit over the data bus a second data signal in conjunction with the clock signal and to clock transmission of the second data signal with the clock signal.
  • the memory device is configured to clock transmission of the second data signal with the data strobe signal.
  • FIG. 1 illustrates a memory system
  • FIG. 2 illustrates a controller of the memory system illustrated in FIG. 1 .
  • FIG. 3 illustrates a DRAM that may be included in the memory system illustrated in FIG. 1 .
  • FIG. 4 illustrates another DRAM that may be included in the memory system illustrated in FIG. 1 .
  • FIG. 5A illustrates another controller that may be included in the memory system illustrated in FIG. 1 .
  • FIG. 5B illustrates another DRAM that may be included in the memory system illustrated in FIG. 1 .
  • FIG. 1 illustrates a memory system 100 that includes a master system clock or global clock 140 , a clock buffer 142 , a controller 110 / 425 , one or more memory modules 120 ( 120 - 1 , 120 - 2 ), one or more control and address (“C/A”) leads 150 , eight data (“DQ”) leads 160 ( 160 - 1 to 160 - 8 ) and eight data strobe (“DS”) leads 170 ( 170 - 1 to 170 - 8 ).
  • the memory module 120 - 1 in some embodiments is a DIMM (dual in-line memory module) that includes eight DRAMs 130 / 440 / 450 ( 130 - 1 to 130 - 8 ), and a configuration storage device 132 .
  • DIMM dual in-line memory module
  • each memory module 120 optionally includes a register 152 , a phase locked loop (“PLL”) clock buffer 144 .
  • PLL phase locked loop
  • These optional support circuits are helpful, for instance, in systems supporting large fan-outs (i.e., large numbers of DRAMs). In particular, these optional circuits support the distribution of clock, control and address signals among the DRAMs 130 .
  • the memory module configuration storage device 132 (sometimes called a mode register or configuration register) is implemented as a serial presence detect (SPD) device such as a PROM (programmable read only memory).
  • SPD serial presence detect
  • PROM programmable read only memory
  • the configuration storage device 132 is typically read by the controller upon power up or system reset to determine the capabilities and/or configuration of the memory module 120 .
  • a bit within the memory module configuration storage device 132 stores a data strobe mode value (also herein called a directional mode value), indicative of whether the memory devices within the memory module can be configured to disable driving of the data strobe, in addition to other mode values.
  • the information read from the memory module configuration storage device 132 is used by the controller 110 to set mode bits within the controller 110 and the DRAMs 130 .
  • the number of data leads, data strobes and DRAMs may be larger or smaller. Except where otherwise noted, discussions provided here with respect to controller 110 are also applicable to controller 425 , and discussions with respect to DRAM 130 are also applicable to DRAMs 440 and 450 .
  • the C/A leads 150 function as a control and address bus, having as many parallel signal paths as needed by the memory system 100 .
  • each of the DQ leads 160 function as a data bus, having as many parallel signal paths (or as few as one signal path) as needed by the memory system 100 .
  • the C/A leads 150 , DQ leads 160 and DS leads 170 connect the controller 110 to each of the memory modules.
  • the DS leads 170 transmit data strobes that act as source synchronous bi-directional timing references.
  • the set of leads 150 , 160 , 170 interconnecting the controller 110 / 425 and the memory module 120 are sometimes collectively called a memory bus or, more generally, an interconnect.
  • the DS leads 170 separately connect the controller 110 to each DRAM 130 in the memory module 120 .
  • the controller 110 transmits data to a DRAM 130 over a given DQ lead 160
  • the transmission and receipt of the data is clocked by the data strobe transmitted by the controller 110 over a corresponding DS lead 170 .
  • a DRAM 130 transmits data to the controller 110 over a given DQ lead 160
  • the transmission and receipt of the data is clocked by the data strobe transmitted by the DRAM 130 over a corresponding DS lead 170 .
  • the DS leads 170 in the memory system 100 are configured to operate in a unidirectional manner. More specifically, data strobes transmitted by the DS leads 170 are unidirectional—generated and transmitted by the controller 110 only.
  • the DRAMs 130 may receive a data strobe but not generate and transmit a data strobe.
  • the transmission and receipt of the data is clocked by the clock signal received from the clock buffer 142 .
  • the memory system 100 includes a controller 110 and a DRAM 130 that may be configured to operate in conjunction with DS leads 170 that are bidirectional or unidirectional.
  • the embodiments described here are not limited to a controller 110 and/or a DRAM 130 that operate in a unidirectional manner.
  • a single part e.g., a controller 110 , DRAM 130 / 440 / 450 , or memory module 120 ) may be configurable so as to satisfy past, present, and future needs of the memory system market. In other words, these devices are capable of providing improved performance while also maintaining backwards compatibility.
  • the controller 110 (sometimes called a memory controller) preferably sends and receives data to and from external components (i.e., components not illustrated in FIG. 1 ). Additionally, the controller 110 sends and receives this same data to and from the memory module 120 , which stores this data, via the DQ leads 160 . More specifically, each of the DQ leads 160 connects the controller 110 to a DRAM 130 within the memory module 120 . And as illustrated in FIG. 1 , the DQ leads 160 are bi-directional. More specifically, the controller 110 transmits data to and receives data from the DRAMs 130 via the DQ leads 160 .
  • the controller 110 controls the operation of the memory module 120 , and thus the DRAMs 130 , via the C/A lead 150 , with control and address signals. These signals enable the controller 110 to select one of possibly two or more memory modules 120 to which the controller 110 is coupled.
  • the memory module 120 is configured to receive over the control and address bus 150 control and address signals in conjunction with the clock signal asserted on the clock bus, the clock signal clocking receipt of the control and address signals.
  • the transmission of the control and address signals to the DRAMs 130 is synchronous and operates in parallel with the synchronous transmission of data signals over the DQ leads 160 .
  • the global clock 140 generates a clock (sometimes called the system clock or reference clock) that is transmitted to the clock buffer 142 , which drives the clock to the controller 110 and the memory module 120 .
  • the clock buffer is typically PLL based in order to phase align the clock.
  • Other bus structures for distributing the system or reference clock may be used, such as the configuration shown in U.S. Pat. No. 5,485,490, which is hereby incorporated by reference.
  • a PLL clock buffer 144 receives the clock from the clock buffer 142 .
  • the PLL clock buffer 144 aligns the phase of the module clock (used internally within the memory module) with the received reference clock, and transmits the module clock to the register 152 and the DRAMs 130 .
  • the transfer of data and control signals to the memory module 120 is thus synchronous to the clock generated by the global clock 140 .
  • FIG. 2 illustrates a controller 110 of the memory system 100 in greater detail. It is noted that FIG. 2 is a conceptual representation of a small subset of the components of a typical controller.
  • the controller 110 includes a write indicator 380 , a data-out register 388 , an output buffer 390 , another write indicator 392 , an output buffer 394 , a data-in register 395 , a read indicator 396 , an input buffer 397 , another read indicator 398 , and an input buffer 399 .
  • the two read indicators 396 , 398 are the same read control signal
  • the two write indicators 380 , 392 are the same write control signal.
  • the controller further includes a calibration selector 382 , a calibration array 384 , a clock calibrator 386 , while in other embodiments these elements are not included. In those embodiments in which these elements are not include, the clock from the clock buffer 142 is coupled to the output buffer 394 .
  • the controller 110 also includes a mode register 510 , an OR gate 515 , a calibration selector 555 , a calibration array 560 , a clock calibrator 565 , and a clocking multiplexor 570 .
  • Additional control logic 580 generates the control signals shown in FIG. 2 , and also performs control functions of the controller 110 that are not relevant to the present discussion.
  • the mode register 510 stores a directional mode. Generally, this mode determines whether the DS leads 170 are unidirectional or bidirectional.
  • the mode register 510 may preferably be set during operation of the controller 110 by one or more external components (not illustrated) or during the manufacture of the controller 110 .
  • the directional mode stored by the mode register 510 is transmitted to the OR gate 515 and to the clocking multiplexor 570 .
  • the OR gate 515 receives input from the mode register 510 .
  • the OR gate 515 also receives input from the write indicator 380 .
  • the output of the OR gate 515 is, therefore, high if either the directional mode is high or the write indicator 380 is high.
  • the write indicator 380 is high when the controller 110 writes data to a DRAM, and the directional mode is high when the controller 110 is configured to operate in a unidirectional mode (regardless of whether the controller 110 is writing data, reading data, or is otherwise inactive).
  • the output of the OR gate 515 is connected to the output buffer 394 to enable or disable the output buffer 394 .
  • the output buffer 394 is enabled.
  • its output is tristated (i.e., set to a high impedance state), which leaves the DS lead 170 floating if no other device is asserting a signal on the DS lead, and more generally allows the DS lead 170 to be driven by another device (e.g., a memory device in a memory module).
  • the controller 110 sets the write indicator 380 to enable the output of the output buffer 394 when transmitting data to a DRAM 130 . Additionally, the controller 110 stores calibration data for each memory module 120 to which the controller 110 is connected. In the memory systems illustrated in the present application, only one memory module 120 is shown. Memory systems, however, may include more than one memory module 120 . The various connections of the controller 110 to the memory modules 120 may be different. For example, the length and impedance of such connections may vary. As a result, the timing signals (e.g., clock or data strobe) may be calibrated or adjusted.
  • the timing signals e.g., clock or data strobe
  • the controller includes a calibration selector 382 , a calibration array 384 , a clock calibrator 386 for adjusting the timing signals used when writing data to a memory device.
  • the calibration array 384 stores calibration data for this purpose.
  • the calibration selector 382 carries a signal generated by the controller 110 that selects a specific calibration based upon which memory module 120 is being written to by the controller 110 .
  • the calibration selector 382 may transmit, for example, an address to select a specific calibration value stored by the calibration array 384 .
  • the selected calibration value is transmitted by the calibration array 384 to the clock calibrator 386 , which also receives a clock from the clock buffer 142 .
  • the clock calibrator 386 uses the selected calibration value to adjust the phase of the clock received thereby.
  • each stored calibration value specifies a delay to offset state transitions of the clock signal.
  • the stored calibration values each specify a clock phase.
  • the adjusted clock is the basis of a data strobe generated by the controller 110 .
  • This data strobe is transmitted by the clock calibrator 386 to the data-out register 388 and to the output buffer 394 .
  • the output buffer 394 transmits the data strobe to a DS lead 170 .
  • the data strobe clocks the output of data from the data-out register 388 to the output buffer 390 , which is connected to the DQ lead 160 and enabled by the write indicator 392 .
  • the data-in register 395 of the controller 110 receives a data strobe from the input buffer 397 and data from the input buffer 399 .
  • the input buffer 397 is enabled by the read indicator 396 and the input buffer 399 is enabled by the read indicator 398 .
  • the input buffer 397 receives input (i.e., a data strobe) from the DS lead 170 and the input buffer 399 receives input (i.e., data) from the DQ lead 160 .
  • the control logic 580 controller 110 sets the read indicators 396 , 398 to enable the input buffers 397 , 399 when receiving data from a DRAM 130 .
  • the received data strobe therefore, clocks the receipt of the data.
  • the data strobe When the controller 110 is configured to use the DS leads in a bidirectional manner, the data strobe is source synchronous and is driven by a DRAM while the DRAM transmits data. In this mode, the controller 110 is compatible with conventional DRAM (e.g., DRAM 130 ) memory modules. But when the controller is configured to use the DS leads 170 in a unidirectional manner, the data strobe is not source synchronous and is not driven by a DRAM. In this mode the data strobe may be used by a DRAM as a free running clock to sample data transmitted by the controller 110 .
  • DRAM e.g., DRAM 130
  • the memory module 120 includes a plurality of DRAMs 130 .
  • the controller 110 may include (though not illustrated for simplicity) a data-out register 388 for each DRAM 130 within the memory module 120 .
  • the output of the clock calibrator 386 is connected to each of the data-out registers 388 .
  • an output buffer 390 which is in turn connected to a respective DQ lead 160 , is included for each data-out register 388 .
  • the write indicator 392 is preferably connected to each of these data-out registers 388 so that the output of each data-out register 388 is clocked by the same data strobe and enabled by the same write indicator 392 .
  • an output buffer 394 is included for each DRAM 130 within the memory module 120 .
  • the output of the clock calibrator 386 is connected to each of the data-output buffers 394 , which are in turn connected to a respective DS lead 170 . This configuration enables the controller to transmit separate data to each DRAM 130 of a memory module 120 simultaneously.
  • a given calibration value therefore, applies to each of the data-out registers 388 simultaneously clocked by the data strobe.
  • Each set of DS 170 and DQ leads 160 connected to a given set of output buffers 390 , 394 may also be connected to more than one memory module 120 .
  • Calibration values therefore, are typically derived for each memory module 120 , not each DRAM 130 within a memory module 120 . When a specific memory module 120 is selected, this selection is reflected in the control and address signals transmitted to each memory module 120 in order to set the selected memory module 120 to receive data.
  • the controller 110 may include (though not illustrated for simplicity) a data-in register 395 , input buffer 397 , and input buffer 399 for each DRAM 130 within the memory module 120 (i.e., each set of DS 170 and DQ leads 160 ).
  • This configuration enables the controller to receive separate data from each DRAM 130 of a memory module 120 simultaneously.
  • a specific memory module 120 is selected to transmit data to the controller, only this memory module 120 puts data and a data strobe on the DQ 160 and DS leads 170 , respectively.
  • the calibration selector 555 carries a signal generated by the control logic 580 of controller 110 depending on which memory module is being read from by the controller 110 (i.e., depending on which memory module is transmitting data over the DQ lead 160 to the controller 110 ).
  • the calibration selector 555 may transmit an address to select a specific calibration value stored by the calibration array 560 .
  • the selected calibration value is transmitted by the calibration array 560 to the clock calibrator 565 , which also receives a clock from the clock buffer 142 .
  • the clock calibrator 565 uses the selected calibration value to adjust the phase of the clock received thereby.
  • the adjusted clock is transmitted by the clock calibrator 565 to the clocking multiplexor 570 .
  • the calibration selector 555 , calibration array 560 and clock calibrator 565 are used only when the directional mode is unidirectional, and are used to generate a phase adjusted receive clock that is adjusted or calibrated in accordance with the memory device from which data is being received. In some embodiments, operation of the clock calibrator 565 is disabled when the directional mode is bidirectional in order to reduce power usage.
  • the clocking multiplexor 570 is configured to transmit either the phase adjusted clock transmitted by the clock calibrator 565 or a data strobe transmitted over the DS lead 170 .
  • the output of the clocking multiplexor 570 may be called a clock signal or reference signal, even though in some circumstances this signal may be derived from the received data strobe.
  • the selection of the signal output by the clocking multiplexer 570 is controlled by the mode register 510 , which as stated above outputs a directional mode to the clocking multiplexor 570 .
  • the output of the clocking multiplexor 570 is transmitted to the input buffer 397 , which as stated above is enabled by the read indicator 396 and connected to the data-in register 395 .
  • the data received by the data-in register 395 is, therefore, clocked by either the adjusted clock produced by the clock calibrator 565 or the data strobe transmitted over the DS lead 170 .
  • the clocking multiplexor 570 transmits the data strobe transmitted over the DS lead 170 to the input buffer 397 when the controller 110 is configured to operate in a bidirectional mode. Additionally, the clocking multiplexor 570 transmits the adjusted clock produced by the clock calibrator 565 to the input buffer 397 when the controller 110 is configured to operate in a unidirectional mode.
  • the data strobe may be used by the controller 110 to sample data transmitted by a DRAM. But when configured to operate in a unidirectional manner, the capture of read data by the controller 110 is timed or clocked with a calibrated internal timing reference (e.g., the adjusted clock).
  • a calibrated internal timing reference e.g., the adjusted clock
  • FIG. 3 illustrates a DRAM 130 of the memory system 100 .
  • the DRAM 130 includes a mode register 302 , C/A register 310 , a transmit (Tx) indicator 320 , an output buffer 325 , a receive (Rx) indicator 330 , an input buffer 335 , a data-in register 340 , a receive indicator 350 , an input buffer 355 , a transmit (Tx) indicator 360 , an output buffer 365 , a data-out register 370 and an AND gate 304 .
  • the two receive indicators 330 and 350 are the same receive control signal
  • the two transmit indicators 320 and 360 are the same transmit control signal.
  • the receive and transmit indicators may be complements of each other.
  • FIG. 3 is a conceptual representation of a small subset of the components of a DRAM chip.
  • the data in and data out registers 340 , 370 shown in this Figure represent circuitry in the interface to the storage array of the DRAM, such as in the sense amplifier arrays of the DRAM, and that circuit may or may not strictly meet the definition of “registers” (as opposed, for instance, to latches and other clocked circuits).
  • the data in and data out registers 340 , 370 while shown separately in FIG. 3 , may be implemented in part or in whole with the same circuitry.
  • the C/A register 310 receives a clock (typically from the PLL clock buffer 144 , FIG. 1 ) and control and address signals, via the C/A lead 150 , from the controller 110 .
  • the clock clocks or times the receipt of these control and address signals.
  • the first set of input and output buffers 335 , 325 are connected to a DS lead 170 to receive and transmit, respectively, a data strobe. As illustrated, the data strobe transmitted by the output buffer 325 is generated by the DRAM 130 from the clock.
  • the DRAM mode register 302 stores a directional mode when used in conjunction with the DRAM 130 (or the DRAM 440 of FIG. 4 ).
  • the directional mode determines whether the DS leads 170 are unidirectional or bidirectional.
  • the mode register 302 may preferably be set during operation of the DRAM 130 by the controller 110 or during the manufacture of the DRAM 130 or memory module 120 .
  • the controller 110 and DRAM 130 are configured so that the controller may send a command over the control and address lines 150 that directs the DRAM to store a particular mode value in the mode register 302 .
  • the directional mode stored by the mode register 302 is transmitted to the AND gate 304 .
  • the AND gate 304 receives input from the DRAM mode register 302 .
  • the AND gate 304 also receives input from the transmit (Tx) indicator 320 .
  • the output of the AND gate 304 is high if the directional mode is high and the transmit (Tx) indicator 320 is high.
  • the transmit (Tx) indicator 320 and the directional mode are high when the DRAM 130 transmits a data strobe to the controller and the DRAM 130 is configured to operate in a bidirectional mode.
  • the output of the AND gate 304 is connected to the output buffer 325 to enable or disable the output buffer 325 .
  • the output buffer 325 is enabled and drives the received clock signal onto the DS lead 170 as the data strobe for the data being transmitted from the data out register 370 .
  • the output of the AND gate 304 is low such that the output buffer 325 is disabled.
  • the output buffer 325 When the output buffer 325 is not enabled, its output is tristated (i.e., set to a high impedance state), which leaves the DS lead 170 floating if no other device is asserting a signal on the DS lead, and more generally allows the DS lead 170 to be driven by another device (e.g., the memory controller 110 , or another memory device in another memory module on the same memory bus as the memory module 120 in which the DRAM 130 resides).
  • another device e.g., the memory controller 110 , or another memory device in another memory module on the same memory bus as the memory module 120 in which the DRAM 130 resides.
  • the data strobe received by the input buffer 335 is generated and transmitted by the controller 110 . Additionally, the input buffer 335 is enabled (or set to transmit a data strobe from the DS lead 170 to the data-in register 340 ) by the receive (Rx) indicator 330 . Thus, when the DRAM receives data from the controller 110 , the receive (Rx) indicator 330 is set so that the input buffer 335 is enabled. The receipt of data by the data-in register 340 is clocked, therefore, by the data strobe received over the DS lead 170 .
  • the second set of input and output buffers 355 , 365 is connected to a data signal (DQ) lead 160 to receive and transmit, respectively, data.
  • DQ data signal
  • the data transmitted by the output buffer 365 is transmitted from the data-out register 370 , which receives data from storage elements within the DRAM 130 .
  • the output buffer 365 is enabled (or set to transmit data to the DQ lead 160 ) by the transmit (Tx) indicator 360 .
  • the transmit (Tx) indicator 360 is set so that the output buffer 365 is enabled.
  • the data received by the input buffer 355 is transmitted by the controller 110 .
  • the input buffer 355 is enabled to transmit data from the DQ lead 160 to the data-in register 340 , which transmits data to storage elements within the DRAM 130 , by the receive (Rx) indicator 350 .
  • the receive (Rx) indicator 350 is set so that the input buffer 355 is enabled.
  • the transmission of data by the data-out register 370 is clocked, therefore, by the clock (not the data strobe received over the DS lead 170 ).
  • the data strobe is source synchronous and is driven by the DRAM 130 while the DRAM 130 transmits data.
  • the transmission delays associated with the strobe output buffer 325 and the data output buffer 365 are preferably the same, or very close to being the same. As a result, the phase relationship of the transmitted data and data strobe will be preserved when those signals arrive at the controller.
  • the DRAM 130 is compatible with conventional controllers (e.g., controller 110 , FIG. 1 ). But when the DRAM 130 is configured to use the DS leads in a unidirectional manner, the data strobe is not source synchronous and is not driven by the DRAM. In this mode, the DRAM 130 is compatible with controllers described herein (e.g., controllers with calibrated timing to receive data from the DRAM 130 ).
  • FIG. 4 illustrates another embodiment of a DRAM 440 of the memory system 100 .
  • the DRAM 440 illustrated in FIG. 4 includes a multiplexor 410 .
  • the multiplexor 410 receives the clock (typically from the PLL clock buffer 144 ) and a data strobe transmitted by the DS lead 170 .
  • the output of the multiplexor is transmitted to the data-out register 370 . So depending on the selection by the multiplexor 410 , the output of data by the data-out buffer is timed or clocked by the clock or the data strobe transmitted by the DS lead 170 . This selection is made by the mode register 302 , which transmits the directional mode as selection input to the multiplexor 410 .
  • the data output by the DRAM 440 is clocked by the data strobe generated by a controller (e.g., controller 110 ). This is possible because the data strobe is always transmitted by the controller. Additionally, the data strobe typically suffers from less phase shift than the clock, and as a result the rate of data transmission over the memory bus may be increased over that of prior systems. In this mode, the DRAM 440 is compatible with controllers (such as the controllers described herein) configured to continuously transmit a data strobe to the DRAM 440 .
  • controllers such as the controllers described herein
  • the DRAM 440 when the DRAM 440 is configured to use the DS leads 170 in a unidirectional manner, the data strobe is not available while the DRAM 440 transmits data. Instead, the data output by the DRAM 440 is clocked by the clock. In this mode, the DRAM 440 is compatible with conventional controllers (e.g., controller 110 ).
  • FIG. 5A illustrates another embodiment of a controller 425 for use in the memory system 100 .
  • the controller 425 illustrated in FIG. 5A does not operate in bidirectional mode. Accordingly, this controller 425 does not include a mode register 510 , a write indicator 380 , an OR gate 515 , or a clocking multiplexor 570 . These components are not needed because the output of the clock calibrator 386 is continuously applied to the DS lead 170 .
  • the controller may include a mode register that stores various mode values, but not a directional mode value.
  • this embodiment of the controller 425 includes data strobe output buffer 394 , to provide a signal delay that matches, or approximately matches, the transmission delay associate with data-out register 388 and output buffer 390 . Additionally, input to the data-in register is always clocked by the output of the clock calibrator 565 .
  • This controller 425 is compatible with the DRAMs described herein (e.g., DRAM 130 , DRAM 440 , and DRAM 450 ), but is not compatible with conventional DRAMs.
  • FIG. 5B illustrates another embodiment of a DRAM 450 for use in the memory system 100 .
  • this DRAM 450 does not include an AND gate 304 or an output buffer 325 . This is because this DRAM 450 does not transmit a data strobe over the DS lead 170 .
  • this DRAM 450 does not include a multiplexor 410 because the output of the data-out register 370 is not clocked or timed by the clock. Instead, the data-out register 370 , like the data-in register 340 , is always clocked by a data strobe transmitted over the DS lead 170 . Preferably, only control and address signals transmitted over the C/A lead 150 are clocked by the clock.
  • This DRAM 450 is compatible with controllers described herein (e.g., controller 110 and controller 425 ), but is not compatible with conventional controllers.
  • data strobes and clocks i.e., clock signals
  • these data strobes and clocks are illustrated as single ended signals.
  • these data strobes and clocks are differential signals.
  • the use of differential signals enables greater clock speeds and data rates. Accordingly, it is the claims, not merely the foregoing illustration, that are intended to define the exclusive rights of the invention.

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US10/676,648 US20050071707A1 (en) 2003-09-30 2003-09-30 Integrated circuit with bi-modal data strobe
EP04783434.6A EP1668523B2 (en) 2003-09-30 2004-09-03 Integrated circuit with bi-modal data strobe
PCT/US2004/029186 WO2005033958A1 (en) 2003-09-30 2004-09-03 Integrated circuit with bi-modal data strobe
DE602004007674.0T DE602004007674T3 (de) 2003-09-30 2004-09-03 Integrierte Schaltung mit bimodalem Daten-Strobe
KR1020117006938A KR101108297B1 (ko) 2003-09-30 2004-09-03 2가지 모드의 데이터 스트로브를 구비한 집적 회로
AT04783434T ATE367608T1 (de) 2003-09-30 2004-09-03 Integrierte schaltung mit bimodalem daten-strobe
KR1020067008404A KR101110469B1 (ko) 2003-09-30 2004-09-03 2가지 모드의 데이터 스트로브를 구비한 집적 회로
JP2006533897A JP4783290B2 (ja) 2003-09-30 2004-09-03 バイモーダル・データストローブを備えた集積回路
US12/103,640 US8352696B2 (en) 2003-09-30 2008-04-15 Integrated circuit with bi-modal data strobe
JP2011050556A JP5191555B2 (ja) 2003-09-30 2011-03-08 バイモーダル・データストローブを備えた集積回路

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EP1668523B2 (en) 2014-12-10
KR20060111465A (ko) 2006-10-27
DE602004007674T3 (de) 2015-05-28
DE602004007674D1 (de) 2007-08-30
JP4783290B2 (ja) 2011-09-28
WO2005033958A1 (en) 2005-04-14
JP2007507794A (ja) 2007-03-29
ATE367608T1 (de) 2007-08-15
DE602004007674T2 (de) 2008-04-10
KR20110038184A (ko) 2011-04-13
EP1668523A1 (en) 2006-06-14
US8352696B2 (en) 2013-01-08
KR101108297B1 (ko) 2012-01-25
KR101110469B1 (ko) 2012-01-31
EP1668523B1 (en) 2007-07-18
JP5191555B2 (ja) 2013-05-08
US20080195885A1 (en) 2008-08-14

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