US20040222416A1 - Polished semiconductor wafer and process for producing it - Google Patents

Polished semiconductor wafer and process for producing it Download PDF

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Publication number
US20040222416A1
US20040222416A1 US10/762,111 US76211104A US2004222416A1 US 20040222416 A1 US20040222416 A1 US 20040222416A1 US 76211104 A US76211104 A US 76211104A US 2004222416 A1 US2004222416 A1 US 2004222416A1
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United States
Prior art keywords
semiconductor wafer
boundary
etchant
shield
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US10/762,111
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English (en)
Inventor
Thomas Teuschler
Gunter Schwab
Maximilian Stadler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
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Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Assigned to SILTRONIC AG reassignment SILTRONIC AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SCHWAB, GUNTER, STADLER, MAXIMILIAN, TEUSCHLER, THOMAS
Publication of US20040222416A1 publication Critical patent/US20040222416A1/en
Assigned to SILTRONIC AG reassignment SILTRONIC AG CORRECTIVE ASSIGNMENT TO CORRECT ASSIGNOR'S ADDRESS PREVIOUSLY RECORDED AT REEL 01542 FRAME 0057. Assignors: SCHWAB, GUNTER, STADLER, MAXIMILIAN, TEUSCHLER, THOMAS
Priority to US11/703,458 priority Critical patent/US7972963B2/en
Abandoned legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01D—SEPARATION
    • B01D19/00—Degasification of liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01D—SEPARATION
    • B01D1/00—Evaporating
    • B01D1/30—Accessories for evaporators ; Constructional details thereof
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F1/00—Treatment of water, waste water, or sewage
    • C02F1/20—Treatment of water, waste water, or sewage by degassing, i.e. liberation of dissolved gases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F2103/00—Nature of the water, waste water, sewage or sludge to be treated
    • C02F2103/08—Seawater, e.g. for desalination

Definitions

  • the invention relates to a polished semiconductor wafer for the fabrication of electronic components, having a front surface and a back surface and an edge which forms the periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer.
  • the semiconductor wafer has a polished front surface, into which the components are formed. Strict demands are imposed on the flatness of the front surface, and these demands are extraordinarily high if it is intended to accommodate electronic structures with line widths of 0.1 ⁇ m or below ( ⁇ 0.1 ⁇ m technology). To enable the maximum number of circuits of this type to be integrated, it is necessary to ensure the required flatness to as close as possible to the edge of the front surface.
  • a semiconductor wafer is usually etched prior to a first polishing step, in order to remove damage from the surface left behind by a previous shaping operation, for example by grinding and/or lapping of the semiconductor wafer.
  • the abovementioned patent application states that a raised portion in the edge region of the polished front surface of the semiconductor wafer is likely if the semiconductor wafer is exposed to a flow of a liquid etchant which is guided onto the boundary of the semiconductor wafer during etching.
  • a shield can be positioned in front of the boundary of the semiconductor wafer preventing the etchant from being able to strike the boundary of the semiconductor wafer directly.
  • the document does not give any indications with regard to any potential for targeted influencing of the flatness of a semiconductor wafer in its edge region, in particular with a view to making the semiconductor wafer suitable for the ⁇ 0.1 ⁇ m technology.
  • the invention comprises a polished semiconductor wafer having a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer.
  • a maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 ⁇ m or less.
  • This particular geometry of the back surface of the semiconductor wafer is an essential feature for making the semiconductor wafer suitable for the ⁇ 0.1 ⁇ m technology. This result was likewise unexpected, since the flatness of the front surface forms the focal point of interest with regard to possible minimum line widths of electronic structures. Furthermore, the inventors have established that when producing a semiconductor wafer having this particular, it is essential for the etching step to be carried out in a certain way prior to a first polishing step.
  • the invention also includes a process for producing a polished semiconductor wafer, comprising at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant.
  • the boundary of the semiconductor wafer is shielded along a distance which extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 ⁇ m long.
  • Carrying out the etching step in this process results in a semiconductor wafer whose front surface and back surface are particularly planar all the way to the edge region.
  • the flatness of at least the front surface is optimized during the subsequent polishing, with the improved flatness of the back surface being responsible for this being possible, since the flatness of the front surface of a semiconductor wafer can scarcely be improved by a polishing step if the flatness of the back surface of the semiconductor wafer is relatively moderate. It is essential to the invention for the boundary of the semiconductor wafer which faces the flow of etchant to be at least partially shielded from the etchant flowing in.
  • the shielding action is also essential for the shielding action to cover a region before the boundary of the semiconductor wafer which, as seen in a direction perpendicular to the direction of flow of the etchant and parallel to the thickness of the semiconductor wafer, is at least of a length which corresponds to the sum of the thickness of the semiconductor wafer and a length of 100 ⁇ m.
  • the subject matter of the invention is also an arrangement comprising a semiconductor wafer and a shield which is positioned in front of a boundary of the semiconductor wafer and at least partially shields the boundary of the semiconductor wafer from a liquid etchant flowing onto the boundary.
  • the boundary of the semiconductor wafer has a profile which extends from an inner profile end E, over a length ⁇ , to an edge R of the semiconductor wafer. The edge is located at a distance of a radius from a center of the semiconductor wafer and forms a periphery of the semiconductor wafer.
  • the shield has a border S which is closest to the boundary of the semiconductor wafer and is at a distance ⁇ from the inner profile end E and a border lying furthest from the boundary of the semiconductor wafer.
  • the shield shielding the boundary of the semiconductor wafer which faces the flow of etchant along a distance which extends in the direction of a thickness d of the semiconductor wafer is at least d+100 ⁇ m long.
  • FIG. 1 shows a sectional view of a portion of a semiconductor wafer
  • FIG. 2 diagrammatically depicts an edge region of the semiconductor wafer and relates this region to an ideal plane
  • FIG. 3 shows, in general form, the arrangement according to the invention of the semiconductor wafer and the shield
  • FIG. 4 uses a diagram based on a comparative example and three examples to demonstrate the effect of the invention on the flatness of the back surface of a semiconductor wafer in the edge region;
  • FIGS. 5 to 12 show various embodiments of the arrangement of the semiconductor wafer and the shield during the etching of the semiconductor wafer; the arrangement shown in FIG. 5 forms part of the prior art.
  • FIG. 1 shows the edge region of a silicon semiconductor wafer, since the invention has the effect of improving the flatness of this region.
  • the semiconductor wafer 1 is illustrated in conjunction with a two-dimensional system of coordinates, with the aid of which the relative position of the semiconductor wafer and the shield can subsequently be clarified.
  • the reference point for the system of coordinates is the center of the semiconductor wafer, which is rotated about this center during etching.
  • the edge R of the semiconductor wafer is located at a distance of a radius from the center and forms the periphery of the semiconductor wafer. It is part of a profiled boundary 4 of the semiconductor wafer, the profile being produced mechanically using a shaping tool, for example a profile grinding wheel, in what is known as an edge rounding step.
  • the location of the profile which is closest to the center is marked as the inner profile end E.
  • the boundary of the semiconductor wafer may be rounded symmetrically or asymmetrically.
  • the edge region of the semiconductor wafer, which is of particular interest in connection with the invention, is located at a distance R-1 mm to R-6 mm from the center of the semiconductor wafer, on the front surface 2 and the back surface 3 of the semiconductor wafer.
  • the semiconductor wafer which preferably substantially comprises silicon
  • a flow of liquid etchant which flows to the boundary of the semiconductor wafer at a defined velocity parallel to the radial direction shown in the system of coordinates.
  • Suitable etchants are both alkaline and acid reacting solutions. However, acid reacting solutions are preferred, since the risk that they will introduce metallic impurities into the semiconductor material is much lower.
  • a particularly preferred etchant contains aqueous hydrogen fluoride solution and at least one oxidizing acid, particularly preferably nitric acid, and, if appropriate, further additives. It is also particularly preferred for small gas bubbles to be dispersed in the etchant in order to make the removal of material by etching more uniform. This can be realized, for example, in accordance with the description given in U.S. Pat. No. 5,451,267, the disclosure of which is herein incorporated by reference.
  • the boundary of the semiconductor wafer which faces the flow of etchant is to be at least partially shielded in the manner of the invention. This means that at least part of the periphery of the semiconductor wafer lying in the direction of flow of the etchant is shielded.
  • the effect of the shielding on the flatness of the side faces of the semiconductor wafer is at its greatest, however, if the periphery of the semiconductor wafer which lies in the direction of flow of the etchant is completely shielded in the manner of the invention. This option is therefore also particularly preferred.
  • a shield 5 is arranged in front of boundary 4 of the semiconductor wafer, for example in the manner presented in the above-mentioned EP 1119031 A2.
  • the shield must have a thickness which satisfies the requirement that the flow of the etchant be blocked over a length corresponding to the sum of the thickness d of the semiconductor wafer and a distance of 100 ⁇ m.
  • the thickness d of semiconductor wafer 1 corresponds to the distance between front surface 2 and back surface 3 of the semiconductor wafer.
  • the profile extends from the inner profile end E over a length p to the edge R of the semiconductor wafer.
  • Shield 5 has a rear border located furthest from the boundary of the semiconductor wafer and a border S located closest to the boundary of the semiconductor wafer. Border S is at a distance a, the size of which is preferably 10 mm or less, from inner profile end E.
  • the rear border may be straight or rounded with respect to the vertical direction of the system of coordinates.
  • the body of shield 5 may have a rectangular periphery, in accordance with the sectional illustration, with a constant thickness t max , or, in accordance with the option indicated by dashed lines, may be designed so as to taper toward one or both borders.
  • the degree of tapering may range between thickness t max and a minimum thickness t min .
  • the shield may have a recess 6 which is formed in the radial direction and extends down to a depth y to a base G of the recess. If this feature is present, it is particularly preferred for the relative position of the semiconductor wafer and the shield to be selected in such a way that the boundary of the semiconductor wafer extends into the recess, for example even to such an extent that the difference E-S becomes negative.
  • the length of the shield i.e. the distance between the border S and the rear border, is preferably 5 to 200 mm, particularly preferably 30 to 70 mm.
  • a semiconductor wafer which has been etched in accordance with the invention is distinguished by the fact that its side faces are particularly planar even in the edge region. This naturally also has positive effects on the result of subsequent polishing of the semiconductor wafer, since the flatness of the semiconductor wafer is improved still further as a result.
  • the subsequent polishing and any cleaning steps carried out before and after it are to be carried out in accordance with the prior art.
  • At least one polishing of at least the front surface of the semiconductor wafer is carried out.
  • the polishing can be carried out as single-side polishing or as double-side polishing. In the case of single-side polishing of the front surface, the back surface of the semiconductor wafer is fixed on a support plate, for example by adhesive bonding.
  • the semiconductor wafer lies in a freely moveable manner in a recess in a carrier.
  • the high flatness of the back surface ensures that the polishing of the front surface produces a semiconductor wafer which is extremely planar on this surface all the way into the edge region.
  • Such a successful polishing result can scarcely be achieved with a semiconductor wafer which has been etched in accordance with the prior art and is less planar in the edge region of the side faces, since the locally reduced flatness in the edge region of the back surface is transferred to the front surface, where it also leads to deviations from the ideal plane.
  • the first polishing step is carried out as stock removal polishing and for the final polishing step to be carried out as touch polishing, these two varieties of polishing being distinguished substantially by the amount of material removed during the polishing.
  • the material removed is generally 2 ⁇ m or less and in the case of stock removal polishing, the material removed may be up to 10 ⁇ m and above.
  • the semiconductor wafer can also be coated, for example by an epitaxial layer being deposited on the front surface and/or by the back surface being sealed with a layer of polycrystalline material and/or with an oxide layer.
  • a particularly preferred process sequence for production of the claimed semiconductor wafer comprises the separation of the semiconductor wafer by sawing a single crystal, the rounding of the boundary of the semiconductor wafer, if appropriate the grinding of the semiconductor wafer, which may be carried out as single-side grinding or sequential or simultaneous double-side grinding, and/or the lapping, wet-chemical etching, if appropriate edge polishing, and polishing, which is carried out at least once, of the semiconductor wafer, cleaning steps carried out between the processes and one or more coating operations which are carried out following the final polishing of a side face.
  • FIG. 4 compares the results of a test on the flatness of the back surface of the semiconductor wafers in the edge region for the semiconductor wafers of the Comparative Example and of Examples 1 to 3 in diagram form. It is clear that the semiconductor wafers which were treated in accordance with the prior art did not achieve the criterion that the maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface be 0.7 ⁇ m or less.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • General Chemical & Material Sciences (AREA)
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US10/762,111 2003-01-23 2004-01-21 Polished semiconductor wafer and process for producing it Abandoned US20040222416A1 (en)

Priority Applications (1)

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US11/703,458 US7972963B2 (en) 2003-01-23 2007-10-11 Polished semiconductor wafer and process for producing it

Applications Claiming Priority (2)

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DE10302611A DE10302611B4 (de) 2003-01-23 2003-01-23 Polierte Halbleiterscheibe und Verfahren zu deren Herstellung und Anordnung bestehend aus einer Halbleiterscheibe und einem Schild
DE10302611.8 2003-01-23

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US (2) US20040222416A1 (ko)
JP (1) JP2004228586A (ko)
KR (2) KR100677734B1 (ko)
CN (1) CN1303653C (ko)
DE (1) DE10302611B4 (ko)
TW (1) TWI248641B (ko)

Cited By (5)

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US20070042567A1 (en) * 2005-08-17 2007-02-22 Sakae Koyata Process for producing silicon wafer
US20080214094A1 (en) * 2007-02-15 2008-09-04 Takeo Katoh Method for manufacturing silicon wafer
US20100224964A1 (en) * 2009-03-04 2010-09-09 Siltronic Ag Epitaxially coated silicon wafer and method for producing an epitaxially coated silicon wafer
US20110039411A1 (en) * 2009-08-12 2011-02-17 Siltronic Ag Method For Producing A Polished Semiconductor Wafer
US10961638B2 (en) 2015-12-17 2021-03-30 Siltronic Ag Method for epitaxially coating semiconductor wafers, and semiconductor wafer

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DE102013204830B4 (de) 2013-03-19 2014-10-09 Siltronic Ag Verfahren und Vorrichtung zur Behandlung einer Halbleiterscheibe mit einem Ätzmedium

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US6899762B2 (en) * 1999-08-13 2005-05-31 Siltronic Ag Epitaxially coated semiconductor wafer and process for producing it
US20030031890A1 (en) * 2001-08-08 2003-02-13 Jiro Moriya Angular substrates
US6861360B2 (en) * 2001-12-06 2005-03-01 Siltronic Ag Double-sided polishing process for producing a multiplicity of silicon semiconductor wafers

Cited By (8)

* Cited by examiner, † Cited by third party
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US20070042567A1 (en) * 2005-08-17 2007-02-22 Sakae Koyata Process for producing silicon wafer
US7648890B2 (en) 2005-08-17 2010-01-19 Sumco Corporation Process for producing silicon wafer
US20080214094A1 (en) * 2007-02-15 2008-09-04 Takeo Katoh Method for manufacturing silicon wafer
US20100224964A1 (en) * 2009-03-04 2010-09-09 Siltronic Ag Epitaxially coated silicon wafer and method for producing an epitaxially coated silicon wafer
US8304860B2 (en) 2009-03-04 2012-11-06 Siltronic Ag Epitaxially coated silicon wafer and method for producing an epitaxially coated silicon wafer
US20110039411A1 (en) * 2009-08-12 2011-02-17 Siltronic Ag Method For Producing A Polished Semiconductor Wafer
US8409992B2 (en) 2009-08-12 2013-04-02 Siltronic Ag Method for producing a polished semiconductor wafer
US10961638B2 (en) 2015-12-17 2021-03-30 Siltronic Ag Method for epitaxially coating semiconductor wafers, and semiconductor wafer

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DE10302611B4 (de) 2011-07-07
US20080057714A1 (en) 2008-03-06
KR20040067899A (ko) 2004-07-30
CN1518069A (zh) 2004-08-04
JP2004228586A (ja) 2004-08-12
TWI248641B (en) 2006-02-01
KR100664603B1 (ko) 2007-01-04
KR20060024825A (ko) 2006-03-17
KR100677734B1 (ko) 2007-02-05

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