US20030194545A1 - Systems and methods for filling voids and improving properties of porous thin films - Google Patents

Systems and methods for filling voids and improving properties of porous thin films Download PDF

Info

Publication number
US20030194545A1
US20030194545A1 US10/063,326 US6332602A US2003194545A1 US 20030194545 A1 US20030194545 A1 US 20030194545A1 US 6332602 A US6332602 A US 6332602A US 2003194545 A1 US2003194545 A1 US 2003194545A1
Authority
US
United States
Prior art keywords
thin film
sol
gel
layer
film layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/063,326
Other languages
English (en)
Inventor
James Zesch
Joost Vlassak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/063,326 priority Critical patent/US20030194545A1/en
Assigned to XEROX CORPORATION reassignment XEROX CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: VLASSAK, JOOST J., ZESCH, JAMES CHARLES
Assigned to BANK ONE, NA, AS ADMINISTRATIVE AGENT reassignment BANK ONE, NA, AS ADMINISTRATIVE AGENT SECURITY AGREEMENT Assignors: XEROX CORPORATION
Priority to JP2003101082A priority patent/JP4729247B2/ja
Publication of US20030194545A1 publication Critical patent/US20030194545A1/en
Assigned to JPMORGAN CHASE BANK, AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: XEROX CORPORATION
Priority to US11/154,629 priority patent/US7201022B2/en
Assigned to XEROX CORPORATION reassignment XEROX CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A. AS SUCCESSOR-IN-INTEREST ADMINISTRATIVE AGENT AND COLLATERAL AGENT TO JPMORGAN CHASE BANK
Assigned to XEROX CORPORATION reassignment XEROX CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A. AS SUCCESSOR-IN-INTEREST ADMINISTRATIVE AGENT AND COLLATERAL AGENT TO BANK ONE, N.A.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/0038—Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y10T428/249955—Void-containing component partially impregnated with adjacent component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y10T428/249987—With nonvoid component of specified composition

Definitions

  • This invention relates to reducing the porosity of porous thin films.
  • Substrates having thin films are used commonly in many applications. Thin films are deposited upon substrates used routinely, for instance, in integrated circuits. Likewise, substrates having thin films are used in a multitude of micro-electro-mechanical devices. Substrates having thin films are also used in the semiconductor industry, where great precision in the patterns formed in, and/or locations of, the thin film formed upon the substrates is necessary. The specific patterning and/or positioning of the thin film formed upon a substrate is typically achieved by controllably etching away the thin film material from the substrate using a photoresist mask, such that the thin film material remains in only those areas covered by the photoresist mask.
  • FIG. 1 shows steps corresponding to earlier methods of depositing thin films on substrates.
  • the substrate may be any known or later-developed suitable material, such as glass, metal, or the like. In general, the substrate material will be appropriate for the application the thin film device will be used with.
  • the thin film is formed by sputtering a layer of material used to form the thin film onto the substrate, applying a layer of photoresist materials over the sputtered thin film layer, masking and developing the photoresist material layer to a desired pattern, and then etching away the unwanted photoresist materials and portions of the thin film layer to achieve the desired pattern in the thin film.
  • the resulting thin film layer tends to be porous. That is, the thin film will have voids, pores, holes, cracks and/or other surface penetrating defects.
  • Porosity in sputtered thin films is a common occurrence. Such porosity in sputtered thin films contributes to problems, such as photoresist intrusions, that render subsequent photolithography difficult. Porosity in sputtered thin films also contributes to lateral etchant intrusions into sidewalls of a thin film, thus rendering subsequent thin film etching difficult with respect to the precision required in thin films. Likewise, porosity in sputtered thin films results in a decreased mechanical thin film strength. Because of the weakened nature of the thin film, wire-bonding becomes difficult or unreliable.
  • porosity in sputtered thin films results in a lack of lateral film cohesion, which unfavorably compromises the physical properties of the thin film.
  • the transverse electro-mechanical coupling co-efficient of a thin film may be compromised by the lack of lateral film cohesion that occurs in porous thin films.
  • a photolithography/photoresist material layer is applied over the thin film layer.
  • the photolithography/photoresist material layer is commonly formed by spin-casting the photolithography/photoresist material layer onto the thin film. Because the thin film has surface-penetrating defects, the photolithography/photoresist material penetrates into the porous thin film.
  • the photolithography/photoresist material is then exposed through a mask to achieve a desired pattern of exposed/unexposed portions of the photolithography/photoresist material layer on the thin film.
  • the exposed, or unexposed, portion of the photolithography/photoresist material layer is washed away or otherwise removed to leave the desired pattern of photolithography/photoresist material layer on the thin film.
  • An etchant to which the thin film, but not the photolithography/photoresist material layer, is sensitive is then applied to remove the portions of the thin film that are not protected by the photolithography/photoresist material layer.
  • the remaining patterned photolithography/photoresist material layer is then removed, without damaging the underlying thin film to leave a patterned thin film layer.
  • portions of the thin film that were to be protected by the patterned layer of photolithography/photoresist material layer are nonetheless etched away.
  • any etchant that laterally intruded or migrated into unintended areas of the thin film may have weakened the thin film and substrate, and also results in a thin film pattern that is not as accurate or precise as desired.
  • This invention provides systems and methods that reduce the porosity of thin film materials.
  • This invention separately provides systems and methods for improving the quality of photoresist-patterned thin films.
  • This invention separately provides systems and methods that reduce the incursion of photolithography/photoresist material into thin films.
  • This invention separately provides systems and methods that reduce the ability of thin film etchants to intrude into thin films under patterned photoresist layers.
  • This invention separately provides systems and methods that coat and penetrate a thin film with a sol-gel preparation to yield the combinant sol-gel/thin film layer having physical properties substantially the same as the original untreated thin film only layer.
  • the systems and methods of this invention result in a treated thin film that reduces the ability of the photolithography/photoresist materials to intrude into voids or other surface penetrating defects in the thin film.
  • the systems and methods of this invention additionally or alternatively provide a treated thin film that is better able to resist etchant migrations or intrusions into the thin film that would otherwise disrupt or destroy the desired thin film pattern on the substrate.
  • the treated thin film is formed by applying a sol-gel layer on the porous thin film after the porous thin film is formed on or over the substrate, but before the photolithography/photoresist materials are applied to the thin film.
  • the porous thin film can be solidified to remove many, if not all, of the various surface-penetrating defects. That is, the initially porous thin film and sol-gel combination forms a uniformly strong treated thin film layer.
  • the sol-gel material or a pre-cursor of the sol-gel material, is applied to the thin film in liquid form and then converted by post application processing, such as by baking or curing the sol-gel material onto the thin film.
  • post application processing such as by baking or curing the sol-gel material onto the thin film.
  • the sol-gel material, and thus the treated thin film layer will also have the same etch rates and the same co-efficient of thermal expansion as the original, untreated, porous thin film.
  • the etchant will more accurately remove the unprotected areas of the treated thin film relative to the protected areas of the treated thin film over which the photolithography/photoresist materials have been patterned. Migrations or intrusions of the photoresist materials and/or the etchant into the thin film are reduced.
  • the thin film and sol-gel have similar co-efficients of thermal expansion, the strength and durability of the substrate and thin film is increased as the voids, pores and/or other surface-penetrating defects are not as susceptible to cracking or otherwise failing under the force of energy transmission from the thin film to a counterpart device or under heating in subsequent processing steps.
  • FIG. 1 is a flowchart illustrating a conventional method for depositing a thin film on a substrate
  • FIG. 2 represents a substrate having an ideal thin film layer formed on or over the substrate and a photoresist material layer formed over the thin film;
  • FIG. 3 illustrates a substrate having a thin film layer on the substrate and a photoresist material layer that has seeped into cracks or other surface defects of the thin film layer;
  • FIG. 4 illustrates the photoresist material layer of FIG. 3 after exposing the photoresist layer through a mask
  • FIG. 5 illustrates the thin film layer of FIG. 4 after the etching and removal of the patterned photoresist layer
  • FIG. 6 is a flowchart outlining one exemplary embodiment of a method for forming a thin film layer on or over a substrate according to the systems and methods of this invention
  • FIG. 7 illustrates a substrate having a thin film formed on or over the substrate and a sol-gel layer formed on the thin film layer;
  • FIG. 8 illustrates the sol-gel layer seeping into and filling cracks and/or surface defects in the thin film layer
  • FIG. 9 illustrates a photoresist material layer applied on top of the combined sol-gel/thin film layer after the sol-gel has been cured
  • FIG. 10 illustrates the photoresist material layer of FIG. 9 after exposing and developing the photoresist layer through a mask
  • FIG. 11 illustrates the combined sol-gel/thin film layer of FIG. 10 according to the systems and methods of this invention after etching and removal of the patterned photoresist layer.
  • This invention is directed to reducing the porosity in porous thin films and improving the accuracy and quality of photoresist-patterned thin films.
  • Altering conventional methods of making thin films by adding a sol-gel layer to the thin film layer prior to applying a photoresist material layer reduces the number of cracks or other surface defects in the thin film layer. Baking or curing the sol-gel layer after applying the sol-gel layer to the thin film layer results in the sol-gel and thin film layers substantially combining to form a single unified layer of similar properties.
  • the combined sol-gel/thin film layer has, for example, a co-efficient of thermal expansion or an etch rate that is substantially the same as that of a continuous non-porous thin film of the same material, which the thin film ideally would have had without the sol-gel layer.
  • the sol-gel material, or a precursor of the sol-gel material is applied to the thin film in liquid form and then converted by post application processing such as baking or curing to form a unified sol-gel/thin film layer.
  • a sol-gel layer to a porous thin film may be used in applications other than a photolithography/photoresist material etching application, which is set forth and described herein as an exemplary illustration only of some of the benefits and advantages of reducing the effects of porosity defects in a thin film layer by adding and combining the sol-gel layer with the thin film layer.
  • sol-gel/thin film layer having reduced porosity defects include an increased mechanical integrity of the sol-gel/thin film layer. As a result, more uniform strength or stability exists in the sol-gel/thin film layer rendering wire bonding, for example, more reliable. For instance, the sol-gel/thin film layer provides greater mechanical strength than non-sol-gel treated thin films.
  • the uniformity and lateral cohesion of the sol-gel/thin film layer renders a medium having substantially the same velocity of sound which improves the transmission reliability of acoustic sound waves through the sol-gel/thin film layer.
  • electro-mechanical properties of the sol-gel/thin film layer are less likely to be compromised than non-sol-gel treated thin films. Photoresist intrusions and/or lateral etchant intrusions are also reduced due to the application of the sol-gel layer upon the thin film layer.
  • the sol-gel/thin film combinant layer will exhibit substantially the same coefficient of thermal expansion as the untreated thin film layer, while at the same time reducing the porosity defects that otherwise often occur in sputtered thin films as discussed above.
  • Other benefits and advantages, such as the planarization of the thin film layer by the sol-gel, for example, may also result from the sol-gel/thin film layer of the invention.
  • FIG. 1 shows a flowchart outlining a conventional method for producing thin films on substrates.
  • step S 100 operation continues to step S 200 , where a substrate is provided.
  • step S 300 a thin film is deposited on or over the substrate.
  • step S 400 a photoresist material layer is applied over the thin film. Operation continues to step S 500 .
  • step S 500 the photoresist material layer is exposed through a mask.
  • step S 600 the photoresist material layer is developed. Masking and developing the photoresist material layer in steps S 500 and S 600 results in a patterned photoresist material layer.
  • step S 700 an etchant is applied to remove the thin film over which no remaining photoresist material layer remains.
  • a stripper is subsequently applied in step S 800 to remove the remaining patterned portion of the photoresist material layer over the thin film layer portion. Operation then continues to step S 900 , where the method ends.
  • FIG. 2 shows a substrate 100 having a thin film layer 110 and a photoresist layer 120 formed according to steps S 200 , S 300 and S 400 .
  • the thin film layer 110 would have no voids, cracks or other surface defects, as shown in FIG. 2.
  • voids, cracks or other surface defects typically occur in the thin film layer 110 .
  • the thin film layer 110 may be one of an oxide and a metallic salt, although it should be appreciated that other materials may be used to form the thin film layer 110 as well.
  • the oxide may be zinc.
  • the thin film layer 110 may be formed of includes nitrides, sulfides, selenides, tellurides, arsenides, phosphides, borides, bromides, carbides, chlorides, cyanides, disulfides, fluorides, hydroxides, iodides, monoxides, oxyfluorides, oxynitrides, pentoxides, peroxides, titanides, aluminates, antimonides, silicates, silicides, stannates, titanates, and tungstates.
  • any other known or later-developed material may also be used in the thin film layer
  • FIG. 3 shows a thin film layer 111 on a substrate 101 , where the thin film layer 111 exhibits a variety of voids 112 , and cracks or other surface defects 113 .
  • the photoresist material layer 121 when applied, seeps into the cracks or other surface defects 113 .
  • FIG. 4 shows the result of masking and developing the photoresist material layer 121 according to steps S 500 and S 600 of FIG. 1. Specifically, as shown in FIG. 4, after masking and developing the photoresist material layer 121 , portions of the photoresist material layer 121 are removed, or washed away, except in those areas 122 where it is desired to continue to cover and protect the thin film layer 111 .
  • some photoresist material also remains in other, desirably-unprotected, areas of the thin film layer 111 , such as in the cracks or other surface defects 113 .
  • masking and developing the photoresist material layer 121 typically removes only those parts of the photoresist material layer 121 that are on the surface of the thin film layer 111 .
  • the remaining portions 123 of the photoresist material located in the cracks and other surface defects 113 of the thin film layer 111 pose problems when the etchant is applied, as described above with respect to step S 600 of FIG. 1.
  • Such unpredictable etching may result in, for example, the removal of a portion of the thin film layer 111 that was intended to remain after etching. This occurs as the etchant penetrates under or around a location such that the void 112 is located. As a result, an etched portion 131 of the film 111 may occur such that a portion of the thin film layer 111 that was intended to be fully present is missing.
  • FIG. 6 is a flowchart outlining a first exemplary embodiment of a method for forming a thin film on a substrate according to this invention.
  • the thin film contemplated is a porous thin film that poses the problems and disadvantages illustrated above with respect to FIGS. 1 - 5 , particularly the unpredictable etching resulting in the removal of portions of the thin film layer that were intended to remain, and portions of the thin film layer that were intended to be removed remaining after etching the thin film. Reducing the porosity defects in porous thin films according to this invention improves the quality and accuracy of the patterned thin films produced.
  • step S 1100 a substrate is provided.
  • the substrate may be, for example, glass, metal, or other material known or later developed that is suitably appropriate to the application the thin film is to be used with.
  • step S 1200 a thin film layer is applied on or over the substrate.
  • step S 1300 a sol-gel layer is applied on the thin film layer.
  • the sol-gel layer, or a precursor of the sol-gel material is applied in liquid form and converted by post application processing, such as by baking or curing, to the thin film layer. Applying the sol-gel layer thus differs from forming the thin films represented in FIGS. 1 - 5 and permits a reduction of the porosity defects in the thin film layer to be obtained. Operation then continues to step S 1400 .
  • step S 1400 the sol-gel layer is cured, by baking or any other appropriate known or later developed curing techniques, to substantially merge and unify the sol-gel layer with the underlying thin film layer.
  • step S 1500 a photoresist material layer is applied over the top of the combined sol-gel/thin film layer.
  • step S 1600 the photoresist material layer is patterned using any appropriate known or later-developed patterning technique such as exposing the photoresist material through a mask. Operation then continues to step S 1700 .
  • step S 1700 the photoresist material layer is developed to produce a desired pattern in the photoresist material layer over the combined sol-gel/thin film layer.
  • step S 1800 an etchant is applied to remove the combined sol-gel/thin film layer, except in those areas where the photoresist material layer remains to protect the combined sol-gel/thin film layer.
  • step S 1900 a stripper is used to remove the protection portions of the photoresist material layer to yield the patterned thin film with improved accuracy and minimal porosity defects.
  • step S 2000 the method ends.
  • FIG. 7 illustrates a substrate 1000 having a thin film layer 1100 on or over the substrate 1000 and a sol-gel layer 1200 formed on the thin film layer 1100 .
  • the thin film layer 1100 has no voids, crack or other surface defects.
  • the sol-gel layer 1200 lies flat atop the upper surface of the thin film layer 1100 .
  • thin film layers deposited, or otherwise formed, on a substrate typically have voids and other defects due to their porous nature.
  • FIG. 8 shows a substrate 1001 with a more typical porous thin film layer 1101 in which a number of voids 1102 , and a number of cracks or other surface defects 1103 are present.
  • FIG. 8 also shows that in such thin films 1101 , the sol-gel layer 1201 , applied on or over the upper surface of the porous thin film layer 1101 , seeps into and fills the cracks or other surface defects 1103 present in the porous thin film layer 1101 .
  • FIG. 9 shows the substrate 1001 after the sol-gel layer 1201 and the thin film layer 1101 have been cured and merged to form a combined sol-gel/thin film layer 1110 .
  • the combined sol-gel/thin film layer 1110 exhibits substantially similar properties to that which were originally associated with the porous thin film layer 1101 .
  • a photoresist material layer 1300 is placed on or over the surface of the combined sol-gel/thin film layer 1110 .
  • masking and etching become more reliable as the combined sol-gel/thin film layer 1110 is patterned.
  • the physical properties of the combined sol-gel/thin film layer become substantially the same as the original thin-film-only layer.
  • the sol-gel/thin film layer has a co-efficient of thermal expansion substantially the same as that of the thin-film-only layer.
  • the combined sol-gel/thin film layer 1110 presents a smooth, generally defect-free (or at least defect-reduced) upper surface.
  • the portions of the photoresist material layer 1300 that are to be removed can be removed accurately, so that only the protection portions 1322 of the patterned photoresist material layer 1300 remain.
  • This patterning accuracy improves the accuracy in etching away only the unwanted portions of the combined sol-gel/thin film layer 1110 .
  • FIG. 11 illustrates the patterned combined sol-gel/thin film layer 1110 remaining after etching.
  • a reduced number of, and ideally no, remaining portions of combined sol-gel/thin film layer 1110 exist on top of the substrate 1001 other than those areas of the combined sol-gel/thin film layer 1110 that were under the protection portions 1322 of the patterned photoresist layer 1300 .
  • the unpredictable surfaces that occurred as a result of etchant seepage underneath or around voids present in the combined sol-gel/thin film layer are reduced and ideally eliminated. Accordingly, more accurate thin film patterning and etching of the combined sol-gel/thin film layer 1110 is achieved.
  • step S 1400 because curing the sol-gel in step S 1400 renders the combined sol-gel/thin film layer 1110 substantially the same as the initially-provided porous thin film layer 1101 alone, the desired properties of the thin film device are generally obtained. As a result, according to the systems and methods of this invention, a more reliable and more accurate thin film device is achieved at minimal expense.
  • steps S 1500 -S 1900 can be omitted if further processing of the sol-gel/thin film layer 1110 is not necessary or desirable, or that other processing in addition to, or instead of, photoresist patterning is to performed on the sol-gel/thin film layer 1110 . This may be especially so where an additional layer, different than, or to the exclusion of, the photoresist material layer is applied on or over the combined sol-gel/thin film layer 1110 .
  • Such a combinant sol-gel/thin film layer has a reduced number of porosity defects as compared to the original untreated thin film layer, so that a subsequent layer, or layers, other than photolithography/photoresist materials may be applied to the sol-gel/thin film layer 1110 without the risks a high number of porosity defects would otherwise pose. Accordingly, increased stability, strength and structural integrity may be advantageously achieved in any device having a sol-gel/thin film layer to reduce porosity defects otherwise present in an untreated thin film.
  • the steps S 1500 -S 1900 may be omitted after the sol-gel/thin film layer 1110 is formed so that further processing other than, or in combination with, etching may occur with advantages of the reduced porosity defects resulting form the sol-gel/thin layer 1110 .
  • Other exemplary benefits and/or advantages of the combined sol-gel thin film layer having reduced porosity defects include an increased mechanical integrity of the sol-gel/thin film layer. As a result, more uniform strength or stability exists in the sol-gel/thin film layer, rendering wire bonding, for example, more reliable.
  • the uniformity of the sol-gel/thin film layer creates a medium having substantially the same velocity of sound which improves the transmission reliability of acoustic sound waves in the sol-gel/thin film layer.
  • Photoresist intrusions and/or lateral etchant intrusion are also reduced due to applying the sol-gel layer on the thin film layer.
  • Other benefits and advantages may also result from the sol-gel thin film layer of the invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Materials For Photolithography (AREA)
  • Wire Bonding (AREA)
US10/063,326 2002-04-11 2002-04-11 Systems and methods for filling voids and improving properties of porous thin films Abandoned US20030194545A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/063,326 US20030194545A1 (en) 2002-04-11 2002-04-11 Systems and methods for filling voids and improving properties of porous thin films
JP2003101082A JP4729247B2 (ja) 2002-04-11 2003-04-04 空隙を充填して多孔性薄膜の特性を改善するためのシステム及び方法
US11/154,629 US7201022B2 (en) 2002-04-11 2005-06-17 Systems and methods for filling voids and improving properties of porous thin films

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/063,326 US20030194545A1 (en) 2002-04-11 2002-04-11 Systems and methods for filling voids and improving properties of porous thin films

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/154,629 Division US7201022B2 (en) 2002-04-11 2005-06-17 Systems and methods for filling voids and improving properties of porous thin films

Publications (1)

Publication Number Publication Date
US20030194545A1 true US20030194545A1 (en) 2003-10-16

Family

ID=28789682

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/063,326 Abandoned US20030194545A1 (en) 2002-04-11 2002-04-11 Systems and methods for filling voids and improving properties of porous thin films
US11/154,629 Expired - Fee Related US7201022B2 (en) 2002-04-11 2005-06-17 Systems and methods for filling voids and improving properties of porous thin films

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/154,629 Expired - Fee Related US7201022B2 (en) 2002-04-11 2005-06-17 Systems and methods for filling voids and improving properties of porous thin films

Country Status (2)

Country Link
US (2) US20030194545A1 (ja)
JP (1) JP4729247B2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007014631A2 (de) * 2005-08-03 2007-02-08 Schott Ag Substrat, umfassend zumindest eine voll- oder teilflächige makrostrukturierte schicht, verfahren zu deren herstellung und deren verwendung

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8277899B2 (en) 2010-12-14 2012-10-02 Svaya Nanotechnologies, Inc. Porous films by backfilling with reactive compounds
JP5788342B2 (ja) * 2012-02-08 2015-09-30 シャープ株式会社 半導体キャリア用フィルムおよびそれを用いた半導体装置、液晶モジュール

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3865469A (en) * 1973-01-18 1975-02-11 Matsushita Electric Ind Co Ltd Liquid crystal display device
US5202274A (en) * 1991-06-14 1993-04-13 Samsung Electronics Co., Ltd. Method of fabricating thin film transistor
US5688606A (en) * 1995-04-26 1997-11-18 Olin Corporation Anodized aluminum substrate having increased breakdown voltage
US5807611A (en) * 1996-10-04 1998-09-15 Dow Corning Corporation Electronic coatings
US5925228A (en) * 1997-01-09 1999-07-20 Sandia Corporation Electrophoretically active sol-gel processes to backfill, seal, and/or densify porous, flawed, and/or cracked coatings on electrically conductive material

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5413865A (en) * 1992-01-31 1995-05-09 Central Glass Company, Limited Water-repellent metal oxide film and method of forming same on glass substrate
US5733660A (en) * 1994-05-20 1998-03-31 Central Glass Company, Limited Glass pane with reflectance reducing coating

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3865469A (en) * 1973-01-18 1975-02-11 Matsushita Electric Ind Co Ltd Liquid crystal display device
US5202274A (en) * 1991-06-14 1993-04-13 Samsung Electronics Co., Ltd. Method of fabricating thin film transistor
US5688606A (en) * 1995-04-26 1997-11-18 Olin Corporation Anodized aluminum substrate having increased breakdown voltage
US5807611A (en) * 1996-10-04 1998-09-15 Dow Corning Corporation Electronic coatings
US5925228A (en) * 1997-01-09 1999-07-20 Sandia Corporation Electrophoretically active sol-gel processes to backfill, seal, and/or densify porous, flawed, and/or cracked coatings on electrically conductive material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007014631A2 (de) * 2005-08-03 2007-02-08 Schott Ag Substrat, umfassend zumindest eine voll- oder teilflächige makrostrukturierte schicht, verfahren zu deren herstellung und deren verwendung
WO2007014631A3 (de) * 2005-08-03 2008-03-13 Schott Ag Substrat, umfassend zumindest eine voll- oder teilflächige makrostrukturierte schicht, verfahren zu deren herstellung und deren verwendung

Also Published As

Publication number Publication date
US7201022B2 (en) 2007-04-10
JP2004006785A (ja) 2004-01-08
US20050233264A1 (en) 2005-10-20
JP4729247B2 (ja) 2011-07-20

Similar Documents

Publication Publication Date Title
JPH06181209A (ja) 半導体装置の製造方法
US7201022B2 (en) Systems and methods for filling voids and improving properties of porous thin films
WO2006033872A3 (en) Method of forming an in-situ recessed structure
EP0114133A1 (fr) Procédé de fabrication de conducteurs pour circuits intégrés, en technologie planar
JP2002151385A (ja) ステンシルマスク
KR100303779B1 (ko) 실리레이션된 이중 감광막을 이용한 패턴 형성 방법
JP2007135129A (ja) 圧電振動片の製造方法およびその製造方法により製造した圧電振動片
US7005385B2 (en) Method for removing a resist mask with high selectivity to a carbon hard mask used for semiconductor structuring
JP3158844B2 (ja) 半導体素子の製造方法
KR100856613B1 (ko) 반도체 소자의 제조 방법
US10529586B2 (en) Method of manufacturing semiconductor device
JPH08236531A (ja) 半導体装置の配線形成方法
KR100519314B1 (ko) 반도체 웨이퍼 식각방법
KR100247642B1 (ko) 반도체 소자의 콘택홀 형성방법
TW495905B (en) Forming method of passivation layer with low coupling top terminal metal layer
JPH04124822A (ja) 半導体装置の製造方法
JP2006135529A (ja) 薄膜共振子の製造方法
JPH06237136A (ja) 電子部品素子の製造方法
JPS6218034A (ja) 半導体装置の製造方法
JP2005051019A (ja) 半導体装置用電極の形成方法
JPH02148725A (ja) 半導体集積回路の製造方法
JP2000082930A (ja) レジスト膜及びそれを用いた圧電素子の製造方法
JPH10312987A (ja) マイクロマシーニング用ウエファ加工方法
JP2000208432A (ja) 半導体装置の製造方法
JPS62260341A (ja) 多層配線層の形成方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: XEROX CORPORATION, CONNECTICUT

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZESCH, JAMES CHARLES;VLASSAK, JOOST J.;REEL/FRAME:012589/0064;SIGNING DATES FROM 20020327 TO 20020409

AS Assignment

Owner name: BANK ONE, NA, AS ADMINISTRATIVE AGENT, ILLINOIS

Free format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:013111/0001

Effective date: 20020621

Owner name: BANK ONE, NA, AS ADMINISTRATIVE AGENT,ILLINOIS

Free format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:013111/0001

Effective date: 20020621

AS Assignment

Owner name: JPMORGAN CHASE BANK, AS COLLATERAL AGENT, TEXAS

Free format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:015134/0476

Effective date: 20030625

Owner name: JPMORGAN CHASE BANK, AS COLLATERAL AGENT,TEXAS

Free format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:015134/0476

Effective date: 20030625

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: XEROX CORPORATION, CONNECTICUT

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A. AS SUCCESSOR-IN-INTEREST ADMINISTRATIVE AGENT AND COLLATERAL AGENT TO BANK ONE, N.A.;REEL/FRAME:061388/0388

Effective date: 20220822

Owner name: XEROX CORPORATION, CONNECTICUT

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A. AS SUCCESSOR-IN-INTEREST ADMINISTRATIVE AGENT AND COLLATERAL AGENT TO JPMORGAN CHASE BANK;REEL/FRAME:066728/0193

Effective date: 20220822