TW495905B - Forming method of passivation layer with low coupling top terminal metal layer - Google Patents

Abstract

A kind of forming method for passivation layer with low coupling top terminal metal layer is disclosed in the present invention. At first, a dielectric layer having a metal plug is provided. Then, a metal layer is formed on a dielectric layer and is followed by removing part of the metal layer to form a metal interconnect such that the metal interconnect is mutually connected to the metal plug. After that, a conformal inter metal dielectric layer is formed on the metal layer and is followed by forming an oxide layer on the conformal inter metal dielectric layer. The oxide layer is then etched back to form a spacer on the sidewall of the conformal inter metal dielectric layer. Additionally, by using the spacer as a mask, most of the conformal inter metal dielectric layer is removed so as to reduce the coupling effects in between the metal layers. Finally, a passivation layer is formed on the metal layer.

Description

495905 V. Description of the invention ο) 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a protective layer with a low-coupling top metal layer. 5-2 Background of the Invention: Once the integrated circuit is completely presented, the representative protection process is suitable for the completion of more semiconductor process means. The protection process involves depositing a protection layer on the entire wafer surface. The protective layer is suitable for a structure for sealing a component on a wafer. For example, on the package of the entire integrated circuit, the protective layer can prevent moisture and more pollutants, and it can also prevent mechanical and chemical substances from damaging the components and packages in the integrated circuit. Generally speaking, the protective layer is a thick layer to effectively protect the integrated circuit. However, because the thick protective layer may be prone to cracks, there is a certain upper limit for the thickness of the protective layer under normal circumstances. The type of protective layer that contains silicon nitride or phosphosilicate glass. Silicon nitride is an ideal coating because of its extremely high density and high hardness. It can also be used to resist the penetration of external water vapor and protect the metal plug from water vapor. Phosphosilicate glass contains phosphorus atoms, which can effectively reduce the penetration of alkali metal ions to extend the life of the integrated circuit.

Page 4 495905 V. Description of the invention (2) Referring to the first A diagram, a dielectric layer 100 is first provided, such as a silicon dioxide oxide dielectric layer. There is a metal plug 102 in the dielectric layer, and the metal plug 102 contains at least tungsten, aluminum, or alloy. Next, a metal layer is formed on the dielectric layer 100 (not shown in the figure), so that the unremoved metal layer 104a and the metal plug 102 are connected to each other. Furthermore, a protective layer 106 is formed on the metal layer 104a. The protective layer 106 includes at least phosphosilicate glass. The phosphosilicate glass is intentionally deposited in a non-conformal step covering shape. Thus, the metal layer 1 The top edge of 0 4 a has an overhang. Between the metal lines formed by the top metal layer of the high-density layout, the overhangs on the top of adjacent metal lines will be tightly sealed because the distance between the metal lines is reduced. A hole 109 is formed. In this way, the subsequently deposited silicon nitride layer 108 cannot enter the hole 109. Therefore, the interference caused by the signal transmission between the metal lines and the metal lines, that is, the coupling caused by the dielectric layer between the metal lines is reduced. Generally known silicon nitride has a larger dielectric constant than silicon dioxide and air, and a dielectric layer with a larger dielectric constant results in greater coupling and even circuit failure. However, as shown in Figure A, this conventional method has the protective layer forming method of reducing the top metal layer coupling between metal lines as mentioned above, because there is no silicon nitride layer 1 0 8 in the hole 1 0 to cover the metal. Layer 1 0 4a, causing water vapor to penetrate through the gap between the metal-line-end and the metal-line-end, eroding the metal plug 1 0 2 under the metal layer 1 0 4 a Water and gas react with the barrier layer T i of the metal plug 102 to form an oxide of T i, causing problems such as high resistance of the metal plug, and even causing circuit failure. Because it is known that silicon nitride is a good material that blocks water vapor. Metal layer

495905 V. Description of the invention (3) 1 0 4 a does not completely cover the metal plug 1 0 2 because the layout area is saved, the layout of the metal layer 1 0 4 a and the metal plug 1 0 2 is aligned, and Caused by quasi-errors. Referring to FIG. 1B, a dielectric layer 100 is first provided, such as a silicon dioxide oxide dielectric layer. There is a metal plug 102 in the dielectric layer, and the metal plug 102 contains at least tungsten, aluminum, or an aluminum alloy. Next, a metal layer is formed on the dielectric layer 100 (not shown in the figure), so that the unremoved metal layer 104a and the metal plug 102 are connected to each other. Furthermore, a protective layer 10 6 A is formed on the metal layer 10 4 a. The protective layer 10 6 A contains at least phosphosilicate glass, and the deposition of the phosphosilicate glass in a non-conformal step coverage shape is less obvious, so It will be sealed to form a hole 10 9 A. In this way, the subsequent deposited silicon nitride layer 10 8 A will enter the hole 10 9 A. This method will not have the problem of water and gas invasion. However, the coupling effect between metal lines can be very serious, and even cause circuit failure. Based on the above-mentioned problems caused by the structures of the first A diagram and the first B diagram, it is necessary to improve the traditional process in order to develop components that are more suitable for the current development trend of the semiconductor industry. For example, in semiconductor devices, a method to prevent water vapor from invading metal plugs is needed to avoid high resistance problems, especially during the manufacturing process. The conformal inner metal dielectric layer can be made of silicon nitride with water-proof properties. Any dielectric (die 1 ectric 1 ayer) is formed with a gap wall on the bottom of the sidewall. The gap wall is used as a mask to remove other conformal inner metal dielectric layers, leaving only the bottom conformal inner metal dielectric layer. Protect metal plugs and reduce the effect of coup 1 i ng between metal layers.

Page 6 495905 Description of the 5 'invention (4) It can solve the problems of high resistance of traditional metal plugs, etc., and most of the inner metal dielectric layer (nitride nitride) has been removed, so a very low performance can be obtained. The top metal layer of the combined effect is connected. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, the conventional semiconductor device has many disadvantages. The present invention provides a method for forming a protective layer with a low coupling top metal layer, which can solve the water vapor invasion of metal in the traditional device Plug problems. An object of the present invention is to provide a method for forming a protective layer having a low-handled top metal layer, which mainly uses a gap wall formed on the bottom of the side wall of a conformal inner metal dielectric layer, and uses the gap wall as a cover to remove other common layers. In-shape metal dielectric layer, leaving only the conformal inner metal dielectric layer at the bottom to protect metal plugs and reduce the coupling (coup 1 ing) effect between metal layers. It is used to solve water vapor invasion. This causes problems such as high resistance caused by metal plugs at the bottom of the metal layer. According to the above purpose, the present invention discloses a method for forming a protective layer having a low-coupling top metal layer. First, a dielectric layer is provided, and the dielectric layer has a metal plug. Next, a metal layer is formed on the dielectric layer and a part of the metal layer is removed to form a metal interconnect, so that the metal interconnect and the

495905 V. Description of the invention (5) Metal plugs are connected to each other. Then, a conformal (c ο n f om r a 1) inner metal dielectric layer is formed on the metal layer. Furthermore, an oxide layer is formed on the conformal inner metal dielectric layer. Next, the oxide layer is remnant to form a spacer on the sidewall of the conformal inner metal dielectric layer. Moreover, the gap wall is used as a mask to remove most of the conformal inner metal dielectric layer, so as to reduce the consumptive (c 0 p 1 i n g) effect between the metal layers. Finally, a protective layer is formed on the metal layer. 5-4 Detailed description of the invention: The semiconductor design of the present invention can be widely applied to many semiconductor designs, and can be made of many different semiconductor materials. When the present invention is described by a preferred embodiment, Those skilled in the art should recognize that many steps can be changed, and the materials and materials can be replaced. These general replacements undoubtedly do not depart from the spirit and scope of the present invention. Secondly, the present invention is described in detail with a schematic diagram as follows. In the detailed description of the embodiments of the present invention, the cross-sectional view showing the semiconductor structure will not be partially enlarged according to the general scale in the semiconductor manufacturing process to facilitate the description, but it should not be used as a limited recognition. . In addition, the actual production should include three-dimensional space dimensions of length, width and depth. The invention mainly provides a method for forming a protective layer with a low-coupling top metal layer, which mainly uses the shape of the bottom of the sidewall of a conformal inner metal dielectric layer.

Page 8 495905 V. Description of the invention (6) Form a gap wall and use the gap wall as a screen to remove other conformal inner metal dielectric layers, leaving only the bottom inner conformal metal dielectric layer to protect the dielectric window Plug, and reduce the coupling (Coupling) effect between metal layers. The retained conformal inner metal dielectric layer can be used to resist the penetration of external water vapor and alkali metal ions, and protect the component from damage by water vapor. FIGS. 2A to 2E are schematic cross-sectional views of a method for forming a protective layer having a low-coupling top metal layer according to a preferred embodiment of the present invention. Referring to FIG. 2A, a dielectric layer 200 is first provided, such as a silicon dioxide dielectric layer. The dielectric layer already has a metal plug 202, and the metal plug 202 contains at least tungsten, aluminum, or an aluminum alloy. Taking the manufacture of tungsten plug 202 as an example (not shown on the figure), it can be divided into three main steps first. First, a barrier layer is deposited on the wafer that has completed the step of etching the via window. This barrier layer is usually T i / T i N. It can be used as an adhesive layer to improve the adhesion between tungsten and other materials. It is also possible to help determine the etching end point of tungsten etchback by the difference in plasma spectra between the crane remaining and the T i worm. Next, a blanket blanket metal crane (Blanket Tungsten) is deposited, and then a portion of the tungsten covering the surface of the dielectric layer 200 is removed by a dry etching method, leaving tungsten in the interlayer hole. Finish the production of the interposer plug. Next, a metal layer 20 4 is formed on the dielectric layer 20 0. On the top of the integrated circuit element, the metal interconnect metal is the metal layer 204. A patterned photoresist layer 206 is formed on the metal layer 20 4.

495905 V. Description of the invention (7) I ~-Referring to the second figure B, the photoresist layer 206 is used as an etching mask, and the metal layer 208 is formed on the dielectric layer 200 through a dry etch pattern transfer pattern. Is a metal layer 204a. The photoresist layer 206 is removed from the second a picture. Next, a conformal inner metal dielectric layer 208 is formed on the metal layer 204a. The conformal inner metal dielectric layer 208 includes at least silicon nitride and is subjected to a plasma enhanced chemical vapor deposition method ( PECVD), with a thickness between 2000 and 300 angstroms. Nitride stone can be used to resist the penetration of external water vapor and protect the plug of the interlayer window from water vapor. Then, an oxide layer 2 is formed on the conformal inner metal dielectric layer 208. The oxide layer 2 10 includes silicon dioxide and is deposited by a plasma enhanced chemical vapor deposition method (PECVD). The deposited thickness is between 300 and 500 Angstroms. According to the second C picture, using a non-isotropic etching method, this layer of dioxygen ^ 1 layer 21 is etched back (time (^ — 1 ^)) to form a spacer 212 within the conformal gold electrode 7 2 〇8 on the bottom of the side wall. This gap wall 21 2 has a silicon nitride layer a. Silicon nitride is an ideal protective layer because of its extreme degree of hardness and high hardness. Second, t t is used to resist external moisture. Penetrates and protects the plug of the interlayer window = =. This feature is used to solve the problems of water vapor invasion and high resistance caused by the metal plug 2 0 2 at the bottom of the Monsoon. 208, the gap wall 212 is a mask, and the method for etching the silicon nitride layer is to use a silicon nitride layer 208 of / 0 I ·, which is represented by the symbol 208a. , = Gas (Reactl0n — Etch). This 4% RIE '疋 is a kind of sputtering etching and plasma

Page 10 495905

V. Description of the invention (8) Dry etching technology between the rest of the time. By combining the physical and chemical removal mechanisms of thin films, we can obtain a combination of the advantages of anisotropic etching and an acceptable choice of money engraving technology. The nitride layer 208 on the top of the metal and most of the metal sidewalls is removed by this reactive ion etching method, which can greatly reduce the coupling effect between the metal layers. Referring to the second figure E, a non-conformal step coverage (non ~ conformal step coverage) is formed as a first protective layer 214, and this first protective layer 2 1 4 contains at least phosphorous silicon glass, and the chemical vapor phase is enhanced by plasma Shen ^

PECVD), with a thickness between 300 and 500 angstroms. Because stone / silica glass contains phosphorus atoms, it can effectively reduce alkali metal ions: to extend the life of the integrated circuit. In order to avoid the temperature of the deposition process being too high and affecting the stability of the metal layer 2 0 4 a at the bottom of the first protective layer 2 1 4, the process temperature of the first protective layer 2 1 4 deposition should be kept below 4 5 ye . Finally, a second protective layer 2 1 6 is formed on the first protective layer 2 1 4. The second protective layer 2 1 6 contains at least silicon nitride and is deposited by plasma enhanced chemical vapor deposition (PECVD). 'The thickness of the deposit was about 7 Angstroms. Because the first protective layer 2 1 4 is covered by a non-conformal step, the second protective layer cannot fill the cavity 2 0 9, which greatly reduces the coupling effect between metal layers ((: 〇111) 1 丨 1 ^

effect) 0 In summary, the present invention provides a method for forming a protective layer with a low-coupling top metal layer. Hood, remove other conformal

Page 11 495905 V. Description of the invention (9) The inner metal dielectric layer, leaving only the conformal inner metal dielectric layer at the bottom, to protect the metal plugs and reduce the lying between the metal layers (c 〇up 1 ing) effect. The retained conformal inner metal dielectric layer can be used to resist the penetration of external water vapor and alkali metal ions, and protect the component from water vapor attack and damage. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 495905 The drawings briefly explain the above-mentioned objects and advantages of the present invention. The following embodiments and diagrams will be used to describe the details below. Among them: Figure A is a conventional protective layer with a low coupling top metal layer. The cross-section of the forming method is not intended, and FIG. 1B is another schematic cross-sectional view of a conventional method for forming a protective layer of a low-coupling top metal layer; FIGS. 2A to 2E are preferred embodiments of the present invention. A schematic cross-sectional view of a method for forming a protective layer coupled to a top metal layer; FIG. 2A is a schematic cross-sectional view of a semiconductor device in a preferred embodiment of the present invention, in which a metal plug, a metal layer, and a photoresist layer have been sequentially formed on Figure 2B is a schematic diagram of the cross section of the silicon nitride layer and silicon dioxide layer in Figure 2A, and Figure 2C is a schematic cross-sectional view of the semiconductor device structure in Figure 2B. On it; the second D diagram is a schematic cross-sectional view of the structure of the second C diagram by etching the silicon dioxide layer by the reactive ion etching method; and

495905 Brief description of the drawing The second E-form protective layer has a cross-sectional schematic diagram overhanging the structure of the second D image on the top edge of the metal layer. Representative symbols of the main parts:

100 ^ 200 dielectric layer 102 ~ 202 metal plug 104a, 2 0 4a metal layer 106 ^ 1 06A, 214 first protective layer 108> 108A, 216 second protective layer 109 ^ 109A, 209 hole 206 photoresist layer 208 total In-shape metal dielectric layer 210 oxide layer 212 spacer

Page 14

Claims (1)

495905 VI. Scope of patent application 1. A method for forming a protective layer with a low-coupling top metal layer, the method at least comprises: providing a dielectric layer, the dielectric layer having a metal plug; forming a metal layer on the dielectric Layer; removing a part of the metal layer to form a metal connection, so that the metal connection and the metal plug are connected to each other; forming a conformal inner metal dielectric layer on the metal layer; forming an oxide layer on the conformal On the inner metal dielectric layer; etch back the oxide layer to form a gap on one side wall of the conformal inner metal dielectric layer; use the gap as a mask to remove most of the conformal inner metal dielectric And sequentially forming a first protective layer and a second protective layer on the metal layer. 2. The method according to item 1 of the patent application scope, wherein the above-mentioned conformal intra-metal dielectric layer includes at least nitride. 3. The method according to item 2 of the patent application, wherein the thickness of the above-mentioned conformal intra-metal dielectric layer is between 200 and 300 angstroms. 4. The method of claim 3, wherein the above-mentioned conformal inner metal dielectric layer is deposited by plasma enhanced chemical vapor deposition (PECVD). 495905 VI. Scope of patent application 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned oxide layer contains at least silicon dioxide. 6. The method according to item 5 of the patent application, wherein the thickness of the above-mentioned oxide layer is between 300 and 500 angstroms. 7. The method according to item 6 of the patent application, wherein the above oxide layer is deposited by plasma enhanced chemical vapor deposition (PECVD). 8. The method of claim 1, wherein the above-mentioned spacer is formed on a bottom of the sidewall of the conformal inner metal dielectric layer. 9. The method according to item 1 of the scope of patent application, wherein the above-mentioned conformal inner metal dielectric layer is engraved by a reactive ion #engraving method. 10. The method according to item 1 of the scope of patent application, wherein said first protective layer includes at least phosphorous-silica glass. 1 1. The method according to item 9 of the scope of patent application, wherein the thickness of the first protective layer is in the range of 300 angstroms to 500 angstroms. 1 2. The method according to item 10 of the patent application scope, wherein the first protective layer is deposited by a plasma enhanced chemical vapor deposition (PECVD) method. 495905 6. Scope of patent application 1 3. The method according to item 1 of the scope of patent application, wherein the above-mentioned second protective layer includes at least nitride. 14. The method according to item 13 of the scope of patent application, wherein the thickness of the second protective layer is about 70 angstroms. 15. The method according to item 14 of the scope of patent application, wherein the second protective layer is deposited by a plasma enhanced chemical vapor deposition method (PEC VD). 16. A method for forming a protective layer having a low-coupling top metal layer, the method at least comprising: providing a dielectric layer having a metal plug; forming a metal layer on the dielectric layer; removing Part of the metal layer to form a metal connection, so that the metal connection and the metal plug are connected to each other; forming a conformal silicon nitride layer on the metal layer; forming a dioxide dioxide layer on the conformal nitride On the layer; etch back the silicon dioxide layer to form a spacer on one side wall of the conformal silicon nitride layer; use the spacer as a mask to remove most of the conformal silicon nitride layer; And sequentially forming a phosphosilicate glass layer and a silicon nitride layer on the metal layer. 17. The method according to item 16 of the scope of patent application, wherein the above-mentioned conformal nitriding 495905 6. Scope of patent application The thickness of the silicon layer is between 200 and 300 angstroms. 18. The method according to item 17 of the scope of patent application, wherein the above-mentioned conformal silicon nitride layer is deposited by plasma enhanced chemical vapor deposition (PECVD). 19. The method according to item 16 of the scope of patent application, wherein the thickness of the aforementioned silicon dioxide layer is between 300 and 500 angstroms. 20. The method according to item 19 of the scope of patent application, wherein the silicon dioxide layer is deposited by a plasma enhanced chemical vapor deposition (PECVD) method. 2 1. The method of claim 16 in the scope of patent application, wherein the above-mentioned spacer is formed at a bottom of the side wall of the conformal inner metal dielectric layer. 22. The method according to item 16 of the scope of patent application, wherein the above-mentioned conformal metal dielectric layer is etched by a reactive ion I etch method I. 2 3. The method according to item 16 of the scope of patent application, wherein the thickness of the above-mentioned phosphor-silicate glass layer is between 300 angstroms and 500 angstroms. 2 4. The method according to item 23 of the scope of patent application, wherein the above-mentioned phosphosilicate glass layer is deposited by plasma enhanced chemical vapor deposition (PECVD). 25. The method according to item 16 of the scope of patent application, wherein the above-mentioned silicon nitride layer Page 18 495905 6. The thickness of the scope of patent application is about 7 0 0 Angstroms. 26. The method according to item 25 of the scope of patent application, wherein the above silicon nitride layer is deposited by plasma enhanced chemical vapor deposition (PECVD) 2 7. —Protection of a metal layer with a low coupling top A method for forming a layer, the method includes at least: providing a dielectric layer having a metal plug; forming a metal layer on the dielectric layer; removing a part of the metal layer to form a metal connection, so that the A metal connection is connected with the metal plug; a conformal silicon nitride layer is formed on the metal layer; a silicon dioxide layer is formed on the conformal silicon nitride layer; the silicon dioxide layer is etched back to form a silicon dioxide layer; A spacer wall is on one of the sidewalls of the conformal silicon nitride layer; the spacer wall is used as a mask to remove most of the conformal silicon nitride layer; a phosphorous silicon glass layer is formed on the metal layer, wherein the phosphorous The silica glass has an overhang on the top edge of one of the metal layers; and a nitride layer is covered on the metal layer. 28. The method according to item 27 of the scope of patent application, wherein the thickness of the above-mentioned conformal silicon nitride layer is between 200 and 300 angstroms. 29. The method according to item 28 of the scope of patent application, wherein the above-mentioned conformal nitriding 495905 6. Scope of patent application Silicon layer is deposited by plasma enhanced chemical vapor deposition (PECVD). 30. The method according to item 27 of the scope of patent application, wherein the thickness of the silicon dioxide layer is between 300 and 500 angstroms. 3 1. The method according to item 30 of the scope of patent application, wherein the above silicon dioxide layer is deposited by plasma enhanced chemical vapor deposition (PECVD). 32. The method according to item 27 of the scope of patent application, wherein the above-mentioned spacer is formed at a bottom of the sidewall of the conformal inner metal dielectric layer. 3 3. The method according to item 27 of the scope of patent application, wherein the above-mentioned conformal inner metal dielectric layer is formed by the reactive ion leaving method #. 34. The method according to item 27 of the scope of patent application, wherein the thickness of the above-mentioned phosphor-silica glass layer is between 300 angstroms and 500 angstroms. 35. The method according to item 27 of the scope of patent application, wherein the above phosphorosilicate glass layer is deposited by plasma enhanced chemical vapor deposition (PECVD). 36. The method according to item 27 of the scope of patent application, wherein the thickness of the above silicon nitride layer is about 70 angstroms. 37. The method according to item 36 of the scope of patent application, wherein the above-mentioned silicon nitride layer Page 20 495905 6. Scope of patent application Deposited by plasma enhanced chemical vapor deposition (PECVD).