JP4570720B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4570720B2
JP4570720B2 JP2000036108A JP2000036108A JP4570720B2 JP 4570720 B2 JP4570720 B2 JP 4570720B2 JP 2000036108 A JP2000036108 A JP 2000036108A JP 2000036108 A JP2000036108 A JP 2000036108A JP 4570720 B2 JP4570720 B2 JP 4570720B2
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trench
insulating film
hole
film
polishing
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JP2001230251A (en
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匡 成田
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Lapis Semiconductor Co Ltd
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Oki Semiconductor Co Ltd
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子の製造方法に係り、特に、ＣＭＰの平坦化方法に関するものである。
【０００２】
【従来の技術】
従来、このような分野の技術としては、以下に示すようなものがあった。
図５はかかる従来の半導体素子の製造方法を示す図である。
まず、図５（ａ）に示すように、下層配線１０１を有する絶縁膜１０２にホール／トレンチ１０３を形成する。
【０００３】
次に、図５（ｂ）に示すように、Ｗ，Ａｌ，Ｃｕ等の金属膜１０４を全面的に堆積させる。
次に、図５（ｃ）に示すように、ＣＭＰによりホール／トレンチ１０３内部にのみ金属を残し、他は除去する。
このような金属の埋め込み方法は、微細なホールを埋め込む際や、ダマシン配線を形成する場合に広く用いられている。
【０００４】
【発明が解決しようとする課題】
しかしながら、上記した従来の方法では、以下のような問題点があった。
まず、図６（ａ）に示すように、ＣＭＰ法により金属の研磨を行う場合には、ホール／トレンチの密度が高い領域Ａにおいて、絶縁膜が薄膜化するエロージョンという現象が発生することが知られている。これはホール／トレンチ密度により、絶縁膜１０２の研磨速度が異なるためと考えられている（高密度領域の方が絶縁膜の研磨速度が大きい）。
【０００５】
このエロージョンが顕著になり絶縁膜１０２が極端に薄膜化すると、下層の基板、下層配線１０１との絶縁性が破壊されて層間リークが生じる。
また、図６（ｂ）に示すように、エロージョンを抑制するために金属の研磨量を極端に少なくすると、絶縁膜１０２上に金属の研磨残り１０５が生じて隣接する配線と層内ショートが発生する。
【０００６】
本発明は、上記問題点を除去し、金属膜ＣＭＰ後の絶縁膜の膜厚を均一に維持することができる半導体素子の製造方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】
本発明は、上記目的を達成するために、
〔１〕金属膜ＣＭＰに使用するスラリーに対する対研磨耐性が上側絶縁膜（３）＞下側絶縁膜（２）＞前記金属膜になっている前記上側絶縁膜（３）を前記下側絶縁膜（２）上に積層で堆積した後、ホール／トレンチが低い密度で形成される領域（Ｂ）の前記上側絶縁膜（３）をホトリソ／エッチングにより除去し、さらにホール／トレンチ（４）を開口した後、前記金属膜（５）を全面に堆積し、さらにＣＭＰによりホール／トレンチ内部を除いて、前記上側絶縁膜（３）をストッパーとして前記金属膜（５）を除去することにより、ホール／トレンチ密度が高い領域（Ａ）に顕著なエロージョンの発生を防止することを特徴とする。
【０００８】
〔２〕ウエハ全面に、トータル膜厚が最終的に所望するホール／トレンチ深さより厚くなるように、膜質が異なる絶縁膜（３３）を含んだ複数の絶縁膜（３２〜３４）を堆積させ、ホール／トレンチ（３５）をパターニングした後、ホール／トレンチの密度が低い領域（Ｂ）に、下側絶縁膜（３２）には達するが下層配線（３１）までは達しない、浅いホール／トレンチ（３６）をパターニングして、ホール／トレンチ密度がウエハ全面で均一になるようにした後に、全面に堆積した金属膜（３７）をＣＭＰする際にホールの無いフラット部の金属膜（３７）が完全に除去された後も、研磨残りを防止するために研磨を続け、ウエハ全面で膜質が異なる絶縁膜（３３）が露出した時点で研磨を終了することを特徴とする。
【０００９】
【発明の実施の形態】
以下、本発明の実施の形態について図を参照しながら詳細に説明する。
図１は本発明の第１実施例を示す半導体素子の製造工程断面図である。
（１）まず、下層配線１を有する下側絶縁膜２と上側絶縁膜３を積層で堆積する。この時、金属膜ＣＭＰに使用するスラリーに対する研磨耐性（ＣＭＰされ難さ）は、以下の通りになっている必要がある。
【００１０】
上側絶縁膜３＞下側絶縁膜２＞金属膜
その後、図１（ａ）に示すように、ホール／トレンチが低い密度で形成される領域Ｂの上側絶縁膜３をホトリソ／エッチングにより除去する。
（２）次に、図１（ｂ）に示すように、ホール／トレンチ４を開口する。
（３）その後、図１（ｃ）に示すように、金属膜５を全面に堆積し、さらにＣＭＰによりホール／トレンチ内部を除いて、金属膜５を除去する。この時、上側絶縁膜３がシリコン窒化膜の場合には、この後にドライ／ウェットエッチングにより上側絶縁膜３を除去しても良い。あるいは、ウエハ全面で下側絶縁膜２が露出する時点まで研磨を継続して、上側絶縁膜３を除去しても良い。
【００１１】
このように、第１実施例によれば、上側絶縁膜３が金属膜ＣＭＰの際にストッパー膜となり、ホール／トレンチ密度の高い領域Ａにおけるエロージョンを抑制する。これにより、局所的なエロージョンの発生が防止される。
次に、本発明の第１参考例について説明する。
図２は本発明の第１参考例を示す半導体素子の製造工程断面図である。
【００１２】
（１）まず、図２（ａ）に示すように、ホール／トレンチが低い密度で形成される領域Ｂの絶縁膜１２の上部をホトリソ／エッチングにより除去し、薄くする。なお、ここで、１１は下層配線である。
（２）次に、図２（ｂ）に示すように、ホール／トレンチ１３を開口する。
（３）その後、図２（ｃ）に示すように、金属膜１４を全面に堆積し、さらにＣＭＰによりホール／トレンチ内部を除いて、金属膜１４を除去する。
【００１３】
このように、第１参考例によれば、ホール／トレンチ密度の低い領域Ｂの絶縁膜１２の膜厚を予め薄くすることにより、ホール／トレンチ密度の高い領域Ａで生じるエロージョンと相殺されて、金属膜ＣＭＰ後の絶縁膜の膜厚を均一に維持できる。
これにより、上側絶縁膜３を積層することなく、第１実施例と同様の効果を得ることができ、より経済的なプロセスが構築可能になる。
【００１４】
次に、本発明の第２参考例について説明する。
図３は本発明の第２参考例を示す半導体素子の製造工程断面図である。
（１）まず、図３（ａ）に示すように、下層配線２１を有する絶縁膜２２が形成されており、そこにホール／トレンチ２３を形成する。その際に、最終的に、所望するホール／トレンチ２３の深さより、厚めに絶縁膜２２を堆積させた後に、ホール／トレンチ２３をパターニングする。
【００１５】
（２）次に、図３（ｂ）に示すように、ホール／トレンチ２３の密度が低い領域Ｂに、下層配線２１（又は基板）まで達しない浅いホール／トレンチ２４をパターニングして、ホール／トレンチ密度がウエハ全面で均一になるようにする。 （３）そこで、図３（ｃ）に示すように、全面に金属膜２５を堆積する。
（４）その後、図３（ｄ）に示すように、金属膜２５をＣＭＰするが、その際にホール／トレンチ２３，２４の無いフラット部の金属膜２５が完全に除去される。
【００１６】
（５）次いで、図３（ｅ）に示すように、研磨残りを防止するために、さらに研磨を続け、浅いホール／トレンチ２４が消失する前に研磨を終了する。
このように、第２参考例によれば、絶縁膜２２のホール／トレンチ２３の密度が低い領域Ｂに形成した浅いホール／トレンチ２４により、ウエハ面内のホール／トレンチ密度が均一になる。これにより、局所的なエロージョンの発生が防止される。
【００１７】
さらに、絶縁膜２２を金属膜２５を堆積させた時点よりも削りこむことにより、フラット部に研磨残りが発生しないという利点がある。これにより第１実施例、第１参考例より、確実に隣接する配線とのショートを防止できる。
次に、本発明の第２実施例について説明する。
図４は本発明の第２実施例を示す半導体素子の製造工程断面図である。
【００１８】
（１）まず、図４（ａ）に示すように、ウエハ全面に、トータル膜厚が最終的に所望するホール／トレンチ深さより厚くなるように、絶縁膜３２〜３４を堆積させ、ホール／トレンチ３５をパターニングする。この場合に絶縁膜３３のみは、絶縁膜３２，３４と膜質（反射率、硬度、対薬液エッチング耐性等）が異なる膜を用いる。一例として、絶縁膜３２，３４、にシリコン酸化物（ＳｉＯ2 ）を用いる場合には、絶縁膜３３にはシリコン窒化物（Ｓｉ3 Ｎ4 ）を用いる。また、パターニングの際には絶縁膜３２〜３４を堆積後に一括で下層配線までホール／トレンチを開口しても良い。
【００１９】
また、絶縁膜３２〜３４を堆積後、及び絶縁膜３４にホール／トレンチ開口後に、このパターンをマスクにして絶縁膜３３、３２に一括でホール／トレンチ開口しても良い。
または、絶縁膜３２〜３４を堆積後、及び絶縁膜３４にホール／トレンチ開口後に、このパターンをマスクにして絶縁膜３３に開口し、さらに絶縁膜３３に形成したパターンをマスクに絶縁膜３２に開口しても良い。
【００２０】
（２）その後、図４（ｂ）に示すように、ホール／トレンチ３５の密度が低い領域Ｂに、絶縁膜３２には達するが下層配線３１までには達しない浅いホール／トレンチ３６をパターニングしてホール／トレンチ密度がウエハ全面で均一になるようにする。ホール／トレンチ３６の開口方法は、先述したホール／トレンチ３５を開口する場合と同様に行う。
【００２１】
（３）その後に、図４（ｃ）に示すように、全面に堆積した金属膜３７をＣＭＰするが、その際にホール／トレンチ３５，３６の無いフラット部の金属膜が完全に除去された後も研磨残りを防止するために研磨を続け、ウエハ全面で絶縁膜３３が露出した時点で研磨を終了する。
（４）さらに、図４（ｄ）に示すように、絶縁膜３３がシリコン窒化物の場合には寄生容量低減のために、この後にドライ／ウエットエッチングにより絶縁膜３３を除去しても良い。あるいは、ウエハ全面で絶縁膜３２が露出する時点まで研磨を継続して、絶縁膜３３を除去しても良い。
【００２２】
このように、第２実施例によれば、絶縁膜３２〜３４に形成した浅いホール／トレンチ３６により、ウエハ面内のホール／トレンチ密度が均一になる。これにより、局所的なエロージョンの発生が防止される。
さらに、絶縁膜３２〜３４を金属膜３７を堆積させた時点よりも削りこむことにより、絶縁膜フラット部に研磨残りが発生しない。これにより、隣接する配線とのショートを防止できる。さらに膜質の異なる絶縁膜３３を、絶縁膜３２と３４の間に挟むことにより、研磨時におけるトルク電流や反射光を信号として検出しながら金属膜３７をＣＭＰする際に、第２参考例よりも所望する時点で再現性良く研磨を止めることが容易になる。
【００２３】
すなわち、研磨を進めていくうち、ウエハ全面で最初に絶縁膜３４が消失して膜質の異なる絶縁膜３３が露出した時点で信号が大きく変化する。つまり、ＣＭＰの終点として検出が容易になる。
同様に、ウエハ全面で絶縁膜３３が消失して膜質の異なる絶縁膜３２が露出した時点においても、信号検出が容易になる。これらの時点をＣＭＰ研磨終了点とすれば、異なるウエハ間においても深さバラツキの少ない、ホール／トレンチ形成が可能となる。
【００２４】
なお、本発明は上記実施例に限定されるものではなく、本発明の趣旨に基づいて種々の変形が可能であり、これらを本発明の範囲から排除するものではない。
【００２５】
【発明の効果】
以上、詳細に説明したように、本発明によれば、以下のような効果を奏することができる。
（１）請求項１記載の発明によれば、上側絶縁膜が金属膜ＣＭＰの際にストッパー膜となり、ホール／トレンチ密度の高い領域におけるエロージョンを抑制する。これにより、局所的なエロージョンの発生が防止される。
【００２６】
（２）請求項２記載の発明によれば、ホール／トレンチ密度の低い領域の絶縁膜に形成した浅いホール／トレンチにより、ウエハ面内のホール／トレンチ密度が均一になる。これにより、局所的なエロージョンの発生が防止される。
また、複数の絶縁膜を金属膜を堆積させた時点よりも削りこむことにより、絶縁膜フラット部に研磨残りが発生しない。これにより、隣接する配線とのショートを防止できる。
【００２７】
さらに、膜質の異なる絶縁膜を、上下の絶縁膜の間に挟むことにより、研磨時におけるトルク電流や反射光を信号として検出しながら金属膜をＣＭＰする際に、所望する時点で再現性良く研磨を止めることが容易になる。
【図面の簡単な説明】
【図１】 本発明の第１実施例を示す半導体素子の製造工程断面図である。
【図２】 本発明の第１参考例を示す半導体素子の製造工程断面図である。
【図３】 本発明の第２参考例を示す半導体素子の製造工程断面図である。
【図４】 本発明の第２実施例を示す半導体素子の製造工程断面図である。
【図５】 従来の半導体素子の製造方法を示す図である。
【図６】 従来技術の問題点の説明図である。
【符号の説明】
１，１１，２１ 下層配線
２ 下側絶縁膜
３ 上側絶縁膜
４，１３，２３，３５ ホール／トレンチ
５，１４，２５，３７ 金属膜
１２，２２，３２，３４ 絶縁膜
２４，３６ 浅いホール／トレンチ
３３ 膜質が異なる絶縁膜
Ａ ホール／トレンチ密度の高い領域
Ｂ ホール／トレンチが低い密度で形成される領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a planarization method for CMP.
[0002]
[Prior art]
Conventionally, there have been the following technologies in such fields.
FIG. 5 is a view showing a method for manufacturing such a conventional semiconductor device.
First, as shown in FIG. 5A, a hole / trench 103 is formed in the insulating film 102 having the lower layer wiring 101.
[0003]
Next, as shown in FIG. 5B, a metal film 104 of W, Al, Cu or the like is deposited over the entire surface.
Next, as shown in FIG. 5C, the metal is left only in the hole / trench 103 by CMP and the others are removed.
Such a metal embedding method is widely used when embedding fine holes or forming damascene wiring.
[0004]
[Problems to be solved by the invention]
However, the conventional method described above has the following problems.
First, as shown in FIG. 6A, when metal polishing is performed by CMP, it is known that a phenomenon called erosion in which the insulating film is thinned occurs in the region A where the hole / trench density is high. It has been. This is presumably because the polishing rate of the insulating film 102 differs depending on the hole / trench density (the polishing rate of the insulating film is higher in the high-density region).
[0005]
When this erosion becomes prominent and the insulating film 102 becomes extremely thin, the insulation between the lower substrate and the lower wiring 101 is destroyed, and interlayer leakage occurs.
Further, as shown in FIG. 6B, if the amount of metal polishing is extremely reduced to suppress erosion, a metal polishing residue 105 is generated on the insulating film 102, and an adjacent wiring and an in-layer short circuit occur. To do.
[0006]
An object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the above-described problems and maintain a uniform film thickness of an insulating film after the metal film CMP.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides
[1] The upper insulating film (3)> the lower insulating film (2)> the upper insulating film (3), which has the resistance to polishing against the slurry used for the metal film CMP, is the lower insulating film. (2) After depositing in a stacked manner, the upper insulating film (3) in the region (B) where holes / trench is formed at a low density is removed by photolithography / etching, and the hole / trench (4) is opened. Then, the metal film (5) is deposited on the entire surface, and further, the inside of the hole / trench is removed by CMP, and the metal film (5) is removed using the upper insulating film (3) as a stopper. It is characterized by preventing the occurrence of significant erosion in the region (A) having a high trench density.
[0008]
[ 2 ] A plurality of insulating films (32 to 34) including insulating films (33) having different film qualities are deposited on the entire surface of the wafer so that the total film thickness is finally greater than the desired hole / trench depth. after patterning the hole / trench (35), the hole / density of trench lower region (B), but does not reach the lower-layer wiring (31) or reaches the lower insulating film (32), a shallow hole / trench ( 36) is patterned so that the hole / trench density is uniform over the entire surface of the wafer, and when the metal film (37) deposited on the entire surface is subjected to CMP, the flat metal film (37) without holes is completely formed. After the removal, the polishing is continued to prevent the polishing residue, and the polishing is terminated when the insulating film (33) having a different film quality is exposed on the entire surface of the wafer.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view of a semiconductor device manufacturing process showing a first embodiment of the present invention.
(1) First, the lower insulating film 2 and the upper insulating film 3 having the lower layer wiring 1 are deposited in a stacked manner. At this time, the polishing resistance (difficulty of CMP) to the slurry used for the metal film CMP needs to be as follows.
[0010]
Upper insulating film 3> Lower insulating film 2> Metal film Thereafter, as shown in FIG. 1A, the upper insulating film 3 in the region B where holes / trench is formed at a low density is removed by photolithography / etching.
(2) Next, as shown in FIG. 1B, the hole / trench 4 is opened.
(3) Thereafter, as shown in FIG. 1C, a metal film 5 is deposited on the entire surface, and the metal film 5 is removed by CMP except the inside of the hole / trench. At this time, when the upper insulating film 3 is a silicon nitride film, the upper insulating film 3 may be removed thereafter by dry / wet etching. Alternatively, polishing may be continued until the lower insulating film 2 is exposed on the entire surface of the wafer, and the upper insulating film 3 may be removed.
[0011]
Thus, according to the first embodiment, the upper insulating film 3 becomes a stopper film during the metal film CMP, and erosion in the region A having a high hole / trench density is suppressed. This prevents the occurrence of local erosion.
Next, a first reference example of the present invention will be described.
FIG. 2 is a cross-sectional view of a manufacturing process of a semiconductor device showing a first reference example of the present invention.
[0012]
(1) First, as shown in FIG. 2A, the upper portion of the insulating film 12 in the region B where holes / trench is formed at a low density is removed by photolithography / etching to make it thin. Here, 11 is a lower layer wiring.
(2) Next, as shown in FIG. 2B, a hole / trench 13 is opened.
(3) Thereafter, as shown in FIG. 2C, a metal film 14 is deposited on the entire surface, and the metal film 14 is removed by CMP except the inside of the hole / trench.
[0013]
As described above, according to the first reference example, by previously reducing the film thickness of the insulating film 12 in the region B with a low hole / trench density, the erosion generated in the region A with a high hole / trench density is offset. The film thickness of the insulating film after the metal film CMP can be kept uniform.
As a result, the same effect as in the first embodiment can be obtained without laminating the upper insulating film 3, and a more economical process can be constructed.
[0014]
Next, a second reference example of the present invention will be described.
FIG. 3 is a cross-sectional view of a manufacturing process of a semiconductor device showing a second reference example of the present invention.
(1) First, as shown in FIG. 3A, an insulating film 22 having a lower layer wiring 21 is formed, and a hole / trench 23 is formed there. At that time, after finally depositing the insulating film 22 thicker than the desired depth of the hole / trench 23, the hole / trench 23 is patterned.
[0015]
(2) Next, as shown in FIG. 3B, a shallow hole / trench 24 that does not reach the lower layer wiring 21 (or the substrate) is patterned in the region B where the density of the holes / trench 23 is low. The trench density should be uniform over the entire wafer surface. (3) Therefore, a metal film 25 is deposited on the entire surface as shown in FIG.
(4) Thereafter, as shown in FIG. 3D, the metal film 25 is subjected to CMP. At this time, the metal film 25 in the flat portion without the holes / trench 23, 24 is completely removed.
[0016]
(5) Next, as shown in FIG. 3E, the polishing is further continued to prevent the polishing residue, and the polishing is finished before the shallow hole / trench 24 disappears.
As described above, according to the second reference example, the shallow hole / trench 24 formed in the region B where the hole / trench 23 density of the insulating film 22 is low makes the hole / trench density in the wafer surface uniform. This prevents the occurrence of local erosion.
[0017]
Further, by scraping the insulating film 22 from the time when the metal film 25 is deposited, there is an advantage that no polishing residue is generated in the flat portion. Thereby, the short circuit with the adjacent wiring can be surely prevented from the first embodiment and the first reference example.
Next, a second embodiment of the present invention will be described.
FIG. 4 is a cross-sectional view of a semiconductor device manufacturing process showing a second embodiment of the present invention.
[0018]
(1) First, as shown in FIG. 4A, insulating films 32 to 34 are deposited on the entire surface of the wafer so that the total film thickness is finally thicker than the desired hole / trench depth. 35 is patterned. In this case, only the insulating film 33 is a film having a different film quality (reflectance, hardness, resistance to chemical etching, etc.) from the insulating films 32 and 34. As an example, when silicon oxide (SiO 2 ) is used for the insulating films 32 and 34, silicon nitride (Si 3 N 4 ) is used for the insulating film 33. Further, in patterning, holes / trench may be opened to the lower layer wiring after the insulating films 32 to 34 are deposited.
[0019]
Alternatively, after depositing the insulating films 32 to 34 and opening the holes / trench in the insulating film 34, the holes / trench openings may be collectively opened in the insulating films 33, 32 using this pattern as a mask.
Alternatively, after the insulating films 32 to 34 are deposited and the hole / trench is opened in the insulating film 34, the pattern is opened in the insulating film 33 as a mask, and the pattern formed in the insulating film 33 is used as the mask in the insulating film 32. You may open it.
[0020]
(2) Thereafter, as shown in FIG. 4 (b), the density is low area B of the hole / trench 35, a shallow hole / trench 36 is reaching the insulating film 32 does not reach the in the lower layer wiring 3 1 or Patterning is performed so that the hole / trench density is uniform over the entire wafer surface. The hole / trench 36 is opened in the same manner as the hole / trench 35 is opened.
[0021]
(3) Thereafter, as shown in FIG. 4C, the metal film 37 deposited on the entire surface is subjected to CMP. At this time, the metal film in the flat portion without the holes / trenches 35 and 36 is completely removed. Thereafter, the polishing is continued to prevent the polishing residue, and the polishing is finished when the insulating film 33 is exposed on the entire surface of the wafer.
(4) Further, as shown in FIG. 4D, when the insulating film 33 is silicon nitride, the insulating film 33 may be removed thereafter by dry / wet etching to reduce parasitic capacitance. Alternatively, the insulating film 33 may be removed by continuing polishing until the insulating film 32 is exposed on the entire surface of the wafer.
[0022]
Thus, according to the second embodiment, the shallow hole / trench 36 formed in the insulating films 32 to 34 makes the hole / trench density in the wafer surface uniform. This prevents the occurrence of local erosion.
Further, by polishing the insulating films 32 to 34 from the time when the metal film 37 is deposited, no polishing residue is generated in the insulating film flat portion. Thereby, a short circuit with the adjacent wiring can be prevented. Further, by sandwiching an insulating film 33 of different film quality between the insulating films 32 and 34, when the metal film 37 is CMPed while detecting torque current and reflected light at the time of polishing as a signal, it is more than that of the second reference example. It becomes easy to stop polishing at a desired time with good reproducibility.
[0023]
That is, as the polishing proceeds, the signal changes greatly when the insulating film 34 disappears first on the entire wafer surface and the insulating film 33 having a different film quality is exposed. That is, it becomes easy to detect the end point of CMP.
Similarly, signal detection is facilitated even when the insulating film 33 disappears on the entire surface of the wafer and the insulating film 32 having a different film quality is exposed. If these points are used as CMP polishing end points, hole / trench formation with little variation in depth between different wafers can be achieved.
[0024]
In addition, this invention is not limited to the said Example, A various deformation | transformation is possible based on the meaning of this invention, and these are not excluded from the scope of the present invention.
[0025]
【The invention's effect】
As described above in detail, according to the present invention, the following effects can be obtained.
(1) According to the invention described in claim 1, the upper insulating film serves as a stopper film during the metal film CMP, and suppresses erosion in a region having a high hole / trench density. This prevents the occurrence of local erosion.
[0026]
(2) According to the invention described in claim 2 , the hole / trench density in the wafer surface is made uniform by the shallow hole / trench formed in the insulating film in the region having a low hole / trench density. This prevents the occurrence of local erosion.
In addition, since the plurality of insulating films are cut away from the time when the metal film is deposited, no polishing residue is generated in the insulating film flat portion. Thereby, a short circuit with the adjacent wiring can be prevented.
[0027]
In addition, by sandwiching insulating films with different film quality between the upper and lower insulating films, polishing is performed with good reproducibility at the desired time when CMP is performed while detecting torque current and reflected light during polishing as signals. It becomes easy to stop.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a manufacturing step of a semiconductor element showing a first embodiment of the invention.
FIG. 2 is a cross-sectional view of a manufacturing process of a semiconductor device showing a first reference example of the invention.
FIG. 3 is a cross-sectional view of a manufacturing process of a semiconductor device showing a second reference example of the invention.
FIG. 4 is a cross-sectional view of a manufacturing process of a semiconductor device showing a second embodiment of the invention.
FIG. 5 is a diagram showing a conventional method for manufacturing a semiconductor element.
FIG. 6 is an explanatory diagram of problems in the conventional technology.
[Explanation of symbols]
1,11,21 Lower layer wiring 2 Lower insulating film 3 Upper insulating film 4, 13, 23, 35 Hole / trench 5, 14, 25, 37 Metal film 12, 22, 32, 34 Insulating film 24, 36 Shallow hole / Trench 33 Insulating film with different film quality A Region with high hole / trench density B Region with low hole / trench density

Claims (2)

金属膜ＣＭＰに使用するスラリーに対する対研磨耐性が上側絶縁膜＞下側絶縁膜＞前記金属膜になっている前記上側絶縁膜を前記下側絶縁膜上に積層で堆積した後、ホール／トレンチが低い密度で形成される領域の前記上側絶縁膜をホトリソ／エッチングにより除去し、さらにホール／トレンチを開口した後、前記金属膜を全面に堆積し、さらにＣＭＰによりホール／トレンチ内部を除いて、前記上側絶縁膜をストッパーとして前記金属膜を除去することにより、ホール／トレンチ密度が高い領域に顕著なエロージョンの発生を防止することを特徴とする半導体素子の製造方法。The resistance against polishing against the slurry used for the metal film CMP is such that the upper insulating film> the lower insulating film> the upper insulating film, which is the metal film, is deposited on the lower insulating film, and then the hole / trench is formed. The upper insulating film in a region formed at a low density is removed by photolithography / etching, and after further opening a hole / trench, the metal film is deposited on the entire surface, and the inside of the hole / trench is further removed by CMP. by removing the metal film upper insulating film as a strike wrapper, a method of manufacturing a semiconductor device characterized by preventing the occurrence of significant erosion in the hole / trench density regions of high. ウエハ全面に、トータル膜厚が最終的に所望するホール／トレンチ深さより厚くなるように、膜質が異なる絶縁膜を含んだ複数の絶縁膜を堆積させ、ホール／トレンチをパターニングした後、ホール／トレンチの密度が低い領域に、下側絶縁膜には達するが下層配線までは達しない、浅いホール／トレンチをパターニングして、ホール／トレンチ密度がウエハ全面で均一になるようにした後に、全面に堆積した金属膜をＣＭＰする際にホールの無いフラット部の金属膜が完全に除去された後も、研磨残りを防止するために研磨を続け、ウエハ全面で膜質が異なる絶縁膜が露出した時点で研磨を終了することを特徴とする半導体素子の製造方法。A plurality of insulating films including insulating films having different film qualities are deposited on the entire surface of the wafer so that the total film thickness is finally thicker than the desired hole / trench depth, and the holes / trench is patterned. the density is low region of, the reach to the lower insulating film does not reach the lower distribution Senma, by patterning a shallow hole / trench, after such hole / trench density becomes uniform in the entire wafer surface, the entire surface Even after the metal film in the flat part without holes is completely removed when CMP is performed on the deposited metal film, polishing is continued to prevent polishing residue, and when an insulating film having a different film quality is exposed on the entire wafer surface. A method of manufacturing a semiconductor device, characterized by terminating polishing.
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US7524758B2 (en) * 2006-02-17 2009-04-28 Toshiba America Electronic Components, Inc. Interconnect structure and method for semiconductor device
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JPH08222632A (en) * 1995-02-13 1996-08-30 Sony Corp Multilayer interconnection forming method and structure thereof
JP2000138220A (en) * 1998-11-02 2000-05-16 Nec Corp Method for forming groove-wiring of semiconductor device
JP2001118845A (en) * 1999-10-20 2001-04-27 Nec Corp Formation of damascene interconnection and semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08222632A (en) * 1995-02-13 1996-08-30 Sony Corp Multilayer interconnection forming method and structure thereof
JP2000138220A (en) * 1998-11-02 2000-05-16 Nec Corp Method for forming groove-wiring of semiconductor device
JP2001118845A (en) * 1999-10-20 2001-04-27 Nec Corp Formation of damascene interconnection and semiconductor device

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