US20030001216A1 - Semiconductor component and method of manufacturing - Google Patents

Semiconductor component and method of manufacturing Download PDF

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Publication number
US20030001216A1
US20030001216A1 US09/893,025 US89302501A US2003001216A1 US 20030001216 A1 US20030001216 A1 US 20030001216A1 US 89302501 A US89302501 A US 89302501A US 2003001216 A1 US2003001216 A1 US 2003001216A1
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Prior art keywords
region
substrate
electrically conductive
electrically
semiconductor component
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US09/893,025
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Inventor
Edouard de Fresart
Patrice Parris
Richard De Souza
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Motorola Solutions Inc
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Motorola Inc
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Priority to US09/893,025 priority Critical patent/US20030001216A1/en
Assigned to MOTOROLA, INC. reassignment MOTOROLA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DE FRESART, EDOUARD D., DE SOUZA, RICHARD JOSEPH, PARRIS, PATRICE
Priority to AU2002315026A priority patent/AU2002315026A1/en
Priority to PCT/US2002/018353 priority patent/WO2003003452A2/fr
Priority to TW091111283A priority patent/TW541696B/zh
Publication of US20030001216A1 publication Critical patent/US20030001216A1/en
Priority to US10/614,553 priority patent/US7074681B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to electronics, in general, and to semiconductor components and methods of manufacturing, in particular.
  • Semiconductor components used in automotive applications typically have semiconductor devices with high breakdown voltages of greater than forty volts. These semiconductor devices occasionally use a REduced SURface Field (RESURF) technique, a trench drift structure, or both. Examples of these semiconductor devices are described in U.S. Pat. No. 5,539,238 and in German Patent Application Publication Number DE 195 35 140 A1. When these semiconductor devices are used in high voltage applications, however, these semiconductor devices have a high drain-to-source on-resistance and a low current drive capability.
  • REduced SURface Field REduced SURface Field
  • FIG. 1 illustrates a cross-sectional view of a portion of a semiconductor component in accordance with an embodiment of the invention
  • FIG. 2 illustrates a cross-sectional view of a portion of a different semiconductor component in accordance with an embodiment of the invention
  • FIG. 3 illustrates a cross-sectional view of a portion of another semiconductor component in accordance with an embodiment of the invention
  • FIG. 4 illustrates a cross-sectional view of a portion of yet another semiconductor component in accordance with an embodiment of the invention
  • FIG. 5 illustrates a cross-sectional view of a portion of still another semiconductor component in accordance with an embodiment of the invention
  • FIG. 6 illustrates a cross-sectional view of a portion of a further semiconductor component in accordance with an embodiment of the invention.
  • FIG. 7 illustrates a flowchart for a method of manufacturing a semiconductor component in accordance with an embodiment of the invention.
  • a semiconductor component includes a trench drift structure in combination with a double RESURF structure.
  • the semiconductor component can be a single or discrete semiconductor device, or the semiconductor component can be an integrated circuit having a plurality of semiconductor devices.
  • the semiconductor device is an Ultra-High Voltage (UHV) or power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) having a lateral structure.
  • UHV Ultra-High Voltage
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • the trench drift structure is located adjacent to a drain region of the semiconductor device. Further in the preferred embodiment, the trench drift structure is integrated in deep submicron technology using Shallow Trench Isolation (STI). Accordingly, the trench in the trench drift structure is preferably manufactured at the same time as the other STI structures in the device.
  • STI Shallow Trench Isolation
  • the trench in the trench drift structure is at least partially surrounded by an electrically floating ring or region that forms an upper RESURF layer in the double RESURF structure.
  • a portion of the semiconductor substrate in which the device is located forms a lower RESURF layer in the double RESURF structure.
  • a portion of a drift region in the trench drift structure is located between and is deflected by the upper and lower RESURF layers.
  • the combination of the trench drift structure and the double RESURF structure provides many advantages.
  • the combined structure increases the breakdown voltage for the semiconductor device.
  • the combined structure permits a doubling of the electrical charge within the drift region of the trench drift structure to lower the drift region resistance and the drain-to-source on-resistance of the semiconductor device.
  • the higher electrical charge or higher doping concentration within the drift region also improves the high side operation of the semiconductor device by preventing premature punch-through in the drift region.
  • the use of the upper RESURF layer improves the robustness of the semiconductor device by reducing the sensitivity of the semiconductor device to semiconductor substrate surface charges.
  • the upper RESURF layer also prevents depletion effects, which originate from within the semiconductor substrate, from reaching the surface of the semiconductor substrate.
  • FIG. 1 illustrates a cross-sectional view of a portion of a semiconductor component 100 .
  • the portion of semiconductor component 100 illustrated in FIG. 1 can represent portions of a single transistor or two transistors depending upon the specific configurations of various doped regions and electrical contacts and electrodes.
  • Component 100 comprises a substrate 110 having a surface 111 .
  • surface 111 of substrate 110 Prior to forming component 100 in substrate 110 , surface 111 of substrate 110 preferably forms a substantially planar plane.
  • substrate 110 is comprised of a semiconductor material. Accordingly, substrate 110 is also referred to as a semiconductor substrate.
  • substrate 110 can comprise a support substrate 113 supporting an overlying epitaxial layer 112 .
  • substrate 110 can consist only of a single semiconductor substrate or a single semiconductor layer.
  • substrate 113 can be comprised of single crystal silicon having a first conductivity type, and layer 112 can be comprised of epitaxial silicon also having the first conductivity type.
  • substrate 110 can be comprised of other semiconductor materials such as, for example, germanium, silicon germanium, or gallium arsenide.
  • substrate 113 can have a very high doping level or concentration, and layer 112 can be grown to have a low doping level or concentration.
  • substrate 113 can be considered P++, and layer 112 can be considered P ⁇ .
  • Semiconductor component 100 also comprises a channel region 120 located in substrate 110 .
  • channel region 120 is illustrated in FIG. 1 to be located within layer 112 of substrate 110 . At least a portion of channel region 120 is located at surface 111 of substrate 110 .
  • channel region 120 can have the first doping type, similar to layer 112 and substrate 113 .
  • the MOSFET of semiconductor component 100 is an n-channel device.
  • Channel region 120 also has a predetermined doping level or concentration.
  • Non-electrically conductive region 130 is substantially located below the substantially planar plane defined by the original surface, or surface 111 , of substrate 110 .
  • Non-electrically conductive region 130 can be a single continuous region encircling or circumscribing channel region 120 .
  • non-electrically conductive region 130 can be comprised of two separate regions.
  • non-electrically conductive region 130 extends only partially into layer 112 of substrate 110 and does not extend into substrate 113 of substrate 110 . At least a portion of non-electrically conductive region 130 is located at surface 111 of substrate 110 .
  • Non-electrically conductive region 130 can be either electrically insulative or electrically semi-insulative.
  • non-electrically conductive region 130 can be formed by etching a trench into surface 111 of substrate 110 and filling the trench with a semi-insulative or dielectric material such as silicon dioxide, silicon nitride, gallium arsenide, or a combination of such materials.
  • non-electrically conductive region 130 can be formed by implanting a high dose of oxygen atoms into surface 111 of substrate 110 .
  • non-electrically conductive region 130 is not formed using a LOCal Oxidation of Silicon (LOCOS) process.
  • LOCS LOCal Oxidation of Silicon
  • Semiconductor component 100 further comprises a doped region 140 located in substrate 110 .
  • doped region 140 is illustrated in FIG. 1 to be located within layer 112 of substrate 110 . At least a portion of doped region 140 is located under channel region 120 .
  • Doped region 140 has a second doping type different from the first doping type of channel region 120 and substrate 110 .
  • doped region 140 can have an n-type conductivity.
  • a drift region 141 is located within doped region 140 .
  • Non-electrically conductive region 130 and drift region 141 form a trench drift structure. At least a portion of drift region 141 is located under non-electrically conductive region 130 . Additionally, at least a portion of drift region 141 is located between channel region 120 and non-electrically conductive region 130 , and at least a portion of drift region 141 is located at surface 111 of substrate 110 .
  • Semiconductor component 100 still further comprises an electrically floating region 150 located in substrate 110 .
  • electrically floating region 150 is illustrated in FIG. 1 to be located in layer 112 of substrate 110 .
  • Electrically floating region 150 is preferably located only between non-electrically conductive region 130 and drift region 141 .
  • electrically floating region 150 is contiguous with both non-electrically conductive region 130 and drift region 141 .
  • At least a portion of electrically floating region 150 is located between non-electrically conductive region 130 and channel region 120 , and at least a portion of electrically floating region 150 is located underneath non-electrically conductive region 130 .
  • Electrically floating region 150 can be a single region encircling or circumscribing channel region 120 . In a different embodiment, electrically floating region 150 can be comprised of two or several separate regions.
  • At least a portion of electrically floating region 150 is located at surface 111 of substrate 110 .
  • a portion of electrically floating region 150 at surface 111 of substrate 110 is located between a portion of drift region 141 at surface 111 of substrate 110 and a portion of non-electrically conductive region 130 at surface 111 of substrate 110 .
  • a portion of electrically floating region 150 is located at a corner or edge of non-electrically conductive region 130 at surface 111 of substrate 110 .
  • This configuration of electrically floating region 150 eliminates or at least reduces any leakage currents emanating from or originating at the corner or edge of non-electrically conductive region 130 .
  • Electrically floating region 150 preferably has the first doping type of channel region 120 and substrate 110 .
  • the doping level or concentration within electrically floating region 150 can be different from or the same as the doping level or concentration within channel region 120 .
  • the doping concentration within electrically floating region 150 can be greater than or less than the doping concentration within channel region 120 . In the preferred embodiment, however, the doping concentration within electrically floating region 150 is twenty-five to fifty percent of the doping concentration within channel region 120 .
  • electrically floating region 150 has a maximum doping concentration of approximately 1 ⁇ 10 17 atoms per centimeter-cubed.
  • Semiconductor component 100 further comprises a drain region 160 in substrate 110 .
  • drain region 160 is illustrated in FIG. 1 to be located within layer 112 of substrate 110 .
  • Non-electrically conductive region 130 is located between drain region 160 and channel region 120 .
  • Electrically floating region 150 is also located between drain region 160 and channel region 120 .
  • Drain region 160 can be a single region encircling or circumscribing channel region 120 , non-electrically conductive region 130 , and electrically floating region 150 .
  • drain region 160 can be comprised of two separate regions.
  • drain region 160 is located in substrate 110 adjacent to and contiguous with a side of non-electrically conductive region 130 facing away from channel region 120 and electrically floating region 150 . At least a portion of drain region 160 is located at surface 111 of substrate 110 . Drain region 160 has the second doping type of doped region 140 . As an example, drain region 160 can have a high doping concentration and can be considered N+.
  • Semiconductor component 100 also comprises a source region 162 in substrate 110 .
  • source region 162 is illustrated in FIG. 1 to be located within layer 112 of substrate 110 .
  • Channel region 120 is located between source region 162 and drift region 141 .
  • Channel region 120 is also located between source region 162 and electrically floating region 150 .
  • Channel region 120 is further located between source region 162 and non-electrically conductive region 130 .
  • At least a portion of source region 162 is located at surface 111 of substrate 110 .
  • source region 162 has the second doping type, has a high doping concentration, and can be considered N+.
  • Semiconductor component 100 further comprises a drain contact 161 and a source contact 163 .
  • Drain contact 161 is located over surface 111 of substrate 110 and drain region 160 . Drain contact 161 is electrically coupled to drain region 160 .
  • Source contact 163 is located over surface 111 of substrate 110 and source region 162 . Source contact 163 is electrically coupled to source region 162 .
  • Semiconductor component 100 additionally comprises a portion 170 of substrate 110 .
  • Portion 170 is located under channel region 120 , non-electrically conductive region 130 , doped region 140 , drift region 141 , electrically floating region 150 , drain region 160 , and source region 162 .
  • a portion of drift region 141 is located between electrically floating region 150 and portion 170 .
  • Portion 170 has the first doping type of channel region 120 and electrically floating region 150 . As illustrated in FIG. 1, channel region 120 is electrically isolated from portion 170 by doped region 140 .
  • Semiconductor component 100 also comprises a body region 171 located in substrate 110 .
  • body region 171 is illustrated in FIG. 1 to be located within layer 112 of substrate 110 .
  • Body region 171 is located over portion 170 of layer 112 .
  • Channel region 120 is located within body region 171 .
  • body region 171 has the first doping type.
  • body region 171 is electrically isolated from portion 170 by doped region 140 .
  • a portion 173 of body region 171 has a high doping concentration to lower the contact resistance between a body contact 172 of component 100 and body region 171 .
  • Portion 173 of body region 171 can be considered P+.
  • Body contact 172 is located over surface 111 of substrate 110 to be electrically coupled to body region 171 through portion 173 .
  • Source region 162 can be a single region encircling or circumscribing portion 173 of body region 171 . In a different embodiment, source region 162 can be comprised of two separate regions.
  • Semiconductor component 100 additionally comprises a gate electrode 180 located over surface 111 of substrate 110 .
  • Gate electrode 180 is preferably located over at least a portion of channel region 120 , non-electrically conductive region 130 , drift region 141 , electrically floating region 150 , portion 170 of layer 112 , and body region 171 .
  • Gate electrode 180 is also preferably located over at least a portion of source region 162 , but is preferably not located over any portion of drain region 160 . In an alternative embodiment, gate electrode 180 can be located over a portion of drain region 160 .
  • gate electrode 180 over the edge or corner of electrically floating region 130 and also over the portion of electrically floating region 150 at surface 111 of substrate 110 adjacent to the edge or corner of electrically floating region 130 both (a) reduces or at least eliminates the leakage current at the edge or corner of non-electrically conductive region 130 and (b) improves the drain-to-source sustaining voltage of the MOSFET in semiconductor component 100 .
  • gate electrode 180 is comprised of a dielectric layer underneath an electrically conductive layer. Gate electrode 180 can also comprise spacers located around a periphery of the electrically conductive layer. In a different embodiment, gate electrode 180 can be devoid of the dielectric material.
  • the semiconductor device in semiconductor component 100 can be a MEtal-Semiconductor Field Effect Transistor (MESFET).
  • Semiconductor component 100 also comprises non-electrically conductive regions 131 , 132 , and 133 . Although not illustrated in FIG. 1, each of regions 131 , 132 , and 133 encircles or circumscribes channel region 120 , non-electrically conductive region 130 , doped region 140 , drift region 141 , electrically floating region 150 , drain region 160 , source region 162 , body region 171 , and portion 170 of layer 112 .
  • Non-electrically conductive regions 130 , 131 , 132 , and 133 are preferably formed simultaneously with each other using a STI process. Drain region 160 is located between non-electrically conductive regions 130 and 131 .
  • Semiconductor component 100 additionally comprises doped regions 164 , 165 , 191 , 192 , 193 , 194 , and 195 .
  • doped regions 164 , 165 , 191 , 192 , 193 , 194 , and 195 encircles or circumscribes channel region 120 , non-electrically conductive regions 130 and 131 , doped region 140 , drift region 141 , electrically floating region 150 , drain region 160 , source region 162 , portion 170 of layer 112 , and body region 171 .
  • Doped regions 165 , 191 , and 193 have the first doping type and electrically couple a substrate contact 197 to substrate 113 and to portion 170 of layer 112 .
  • Doped region 165 has a high doping concentration and is more heavily doped than doped region 191 .
  • Doped region 165 can be formed simultaneously with portion 173 of body region 171 and can be considered P+.
  • Doped regions 165 and 191 are located between non-electrically conductive regions 131 and 132 .
  • Doped regions 192 and 194 also have the first doping type. Doped regions 192 and 194 can be similar to doped regions 191 and 193 , respectively. Doped regions 192 and 194 can also be formed simultaneously with doped regions 191 and 193 , respectively.
  • Doped regions 164 and 195 have the second doping type and, when electrically biased by contact 196 , form an electrically-biased isolation ring around the semiconductor device.
  • Doped region 164 has a high doping concentration and is more heavily doped than doped region 195 .
  • Doped region 164 can be formed simultaneously with drain region 160 and source region 162 and can be considered N+.
  • Doped regions 164 and 195 are located between non-electrically conductive regions 132 and 133 .
  • semiconductor component 100 in FIG. 1 illustrates a single semiconductor device having a trench drift structure in combination with a double RESURF structure.
  • Non-electrically conductive region 130 and drift region 141 form the trench drift structure
  • electrically floating region 150 and portion 170 of layer 112 form the double RESURF structure.
  • the use of the trench drift structure and the double RESURF structure enables the use of a higher doping concentration in doped region 140 to lower the drift region resistance and the drain-to-source on-resistance.
  • the drain-to-source on-resistance of semiconductor component 100 can be at least as low as 0.5 milliohms-cm 2 for an n-channel MOSFET device with a sustaining voltage of 45 volts.
  • FIG. 2 illustrates a cross-sectional view of a semiconductor component 200 , which is different embodiment of semiconductor component 100 in FIG. 1.
  • Semiconductor component 200 in FIG. 2 is a bi-directional device and is symmetric about a line drawn through the center of the channel.
  • Semiconductor component 100 in FIG. 1 is an uni-directional device and is symmetrical about a line drawn through a center of portion 173 in body region 171 .
  • Semiconductor component 200 in FIG. 2 is similar to semiconductor component 100 in FIG. 1.
  • Semiconductor component 200 in FIG. 2 has a different drift region, a different body region, and a different channel region.
  • the drift, body, and channel regions are mainly different only in structure and/or location, but not in function. At least the drift region is also different in doping.
  • semiconductor component 200 comprises a doped region 240 that has an opening in the middle in which a body region 271 is located.
  • a drift region 241 is located in doped region 240
  • a channel region 220 is located in body region 271 .
  • Doped region 240 , non-electrically conductive region 130 , and electrically floating region 150 can each be a single region encircling or circumscribing body region 271 .
  • doped region 241 , non-electrically conductive region 130 , and electrically floating region 150 can each be comprised of two separate regions.
  • semiconductor component 200 comprises a portion 270 of layer 112 , which is electrically coupled to channel region 220 .
  • Doped region 240 does not electrically isolate channel region 220 from portion 270 of layer 112 . As a consequence, semiconductor component 200 does not include a separate top side body contact.
  • Semiconductor component 200 also comprises a drain region 260 , a drain contact 261 , a source region 262 , and a source contact 263 .
  • Drain region 160 , drain contact 261 , source region 262 , and source contact 263 in FIG. 2 are mainly different from drain region 160 , drain contact 161 , source region 162 , and source contact 163 , respectively, in FIG. 1 only in structure and/or location, but not in function.
  • drain region 260 and source region 262 in FIG. 2 do not encircle or circumscribe any portions of the semiconductor device.
  • drain region 260 in FIG. 2 can be identical to drain region 160 .
  • Semiconductor component 200 further comprises a gate electrode 280 , which is mainly different from gate electrode 180 in FIG. 1 only in structure and/or location, but not in function.
  • gate electrode 280 in FIG. 2 does not have a hole in which a source contact or top-side body contact is located.
  • Gate electrode 280 does not overlie drain region 260 or source region 262 , but does overlie at least portions of electrically floating region 150 , drift region 241 , and non-electrically conductive region 130 .
  • FIG. 3 illustrates a cross-sectional view of a portion of a semiconductor component 300 , which is also a different embodiment of semiconductor component 100 in FIG. 1.
  • Semiconductor component 300 in FIG. 3 has an electrically floating region 350 , which is mainly different from electrically floating region 150 in FIG. 1 only in doping and structure and/or location, but not in function.
  • electrically floating region 350 is located mainly only underneath non-electrically conductive region 130 .
  • Electrically floating region 350 is contiguous with non-electrically conductive region 130 .
  • Electrically floating region 350 is not located at surface 111 of substrate 110 .
  • electrically floating region 350 is not located adjacent to a corner or edge of non-electrically conductive region 130 at surface 111 of substrate 110 . Accordingly, semiconductor component 300 in FIG. 3 may have a higher magnitude leakage current than semiconductor component 100 in FIG. 1.
  • FIG. 4 illustrates a cross-sectional view of a portion of a semiconductor component 400 , which is a different embodiment of semiconductor component 100 in FIG. 1.
  • Semiconductor component 400 in FIG. 4 has an electrically floating region 450 , which is mainly different from electrically floating region 150 in FIG. 1 only in doping and structure and/or location, but not in function.
  • electrically floating region 450 surrounds non-electrically conductive region 130 within substrate 110 .
  • Electrically floating region 450 is located between non-electrically conductive region 130 and drain region 160 .
  • Electrically floating region 450 is also located between non-electrically conductive region 130 and channel region 120 .
  • electrically floating region 450 does not contact drain region 160 .
  • a portion of drift region 141 is located between electrically floating region 450 and drain region 160 . Therefore, semiconductor component 400 in FIG. 4 is a larger device than semiconductor component 100 in FIG. 1, and semiconductor component 400 in FIG. 4 has a higher drain-to-source on-resistance than semiconductor component 100 in FIG. 1.
  • electrically floating region 450 can contact drain region 160 , but even this embodiment of semiconductor component 400 is larger than and has a higher drain-to-source on-resistance than semiconductor component 100 in FIG. 1.
  • FIG. 5 illustrates a cross-sectional view of a portion of a semiconductor component 500 , which is a different embodiment of semiconductor component 100 in FIG. 1.
  • Semiconductor component 500 in FIG. 5 has an electrically floating region 550 , which is mainly different from electrically floating region 150 in FIG. 1 only in doping and structure and/or location, but not in doping or function.
  • electrically floating region 550 is located between non-electrically conductive region 130 and drain region 160 and is not located between non-electrically conductive region 130 and channel region 120 .
  • Semiconductor component 500 in FIG. 5 may have a higher magnitude leakage current than semiconductor component 100 in FIG. 1.
  • a portion of electrically floating region 550 is still located underneath non-electrically conductive region 130 .
  • FIG. 6 illustrates a cross-sectional view of a portion of a semiconductor component 600 , which is a different embodiment of semiconductor component 100 in FIG. 1.
  • Semiconductor component 600 in FIG. 6 has an electrically floating region, which is mainly different from electrically floating region 150 in FIG. 1 only in doping and structure and/or location, but not in function.
  • the electrically floating region of semiconductor component 500 is comprised of two separate portions 650 and 651 .
  • Portion 650 can be similar to electrically floating region 350 of component 300 in FIG. 3.
  • the addition of portion 651 in component 600 of FIG. 6 eliminates the potential leakage current disadvantage of component 300 in FIG. 3.
  • Portion 651 in component 600 of FIG. 6 can also be added to component 500 of FIG. 5 for the same reason.
  • FIG. 7 illustrates a flowchart 700 for a method of manufacturing a semiconductor component.
  • the semiconductor component can be similar to semiconductor components 100 , 200 , 300 , 400 , 500 , and/or 600 of FIGS. 1, 2, 3 , 4 , 5 , and 6 , respectively.
  • a substrate having a surface is provided.
  • the substrate and the surface of step 705 can be similar to substrate 110 and surface 111 , respectively, in FIGS. 1, 2, 3 , 4 , 5 , and 6 .
  • the substrate of step 705 comprises an epitaxial layer
  • the dopant in the epitaxial layer forms a portion of the semiconductor device. This portion of the semiconductor device is similar to portion 170 in FIGS. 1, 3, 4 , 5 , and 6 and is also similar to portion 270 in FIG. 2.
  • a non-electrically conductive region is formed to be substantially located below a substantially planar plane defined by the surface of the substrate.
  • the non-electrically conductive region of step 710 can be similar to non-electrically conductive region 130 in FIGS. 1, 2, 3 , 4 , 5 , and 6 .
  • Step 710 also simultaneously forms non-electrically conductive regions 131 , 132 , and 133 with non-electrically conductive region 130 .
  • step 710 is performed using a STI process.
  • a STI process For example, trenches can be etched into surface 111 of substrate 110 , and then a thermal liner oxide layer can be formed along the walls of the trenches. Subsequently, silicon dioxide can be deposited to fill the trenches, and then the silicon dioxide can be densified and planarized. Other techniques can also be used to form the non-electrically conductive regions of step 710 .
  • the non-electrically conductive region of step 710 is preferably not formed by using a LOCOS process.
  • a doped region is formed in the substrate.
  • a drift region is located in the doped region.
  • the doped region of step 715 can be similar to doped region 140 in FIGS. 1, 3, 4 , 5 , and 6 , and can also be similar to doped region 240 in FIG. 2.
  • Step 715 can be performed by, for example, forming an implant mask over the surface of the substrate and implanting a dopant into the substrate. A single implant or a plurality of implants with varying implant doses and energies can be used with the implant mask to form the drift region.
  • a body region is formed in the substrate.
  • a channel region is located in the body region.
  • the drift region can be located between the channel region and the non-electrically conductive region.
  • the body region of step 720 can be similar to body region 171 in FIGS. 1, 3, 4 , 5 , and 6 , and can also be similar to body region 271 in FIG. 2.
  • Step 720 can be performed by, for example, forming an implant mask over the surface of the substrate and implanting a dopant into the substrate. A single implant or a plurality of implants at different implant doses and different implant energies can be performed with the implant mask to form the channel region.
  • an electrically floating region is formed in the substrate.
  • the electrically floating region is preferably contiguous with the non-electrically conductive region of step 710 .
  • the electrically floating region of step 725 can be similar to electrically floating region 150 in FIGS. 1 and 2, electrically floating region 350 in FIG. 3, electrically floating region 450 in FIG. 4, electrically floating region 550 in FIG. 5, or portions 650 and 651 of the electrically floating region in FIG. 6.
  • the formation of the electrically floating region in step 725 of FIG. 7 can be performed by forming an implant mask over the surface of the substrate and implanting a dopant into the substrate. A single implant or a plurality of implants having different implant doses and different implant energies can be used with a single or a plurality of implant masks to form the electrically floating region.
  • steps 720 and 725 are performed simultaneously with each other. Accordingly, the body region and the electrically floating region can be formed simultaneously with each other. Therefore, a single implant mask can be used to define the body region and the electrically floating region. Similarly, the same implant or a single set of implants can be used to form the body region and the electrically floating region.
  • additional doped regions are formed in the substrate.
  • additional doped regions can include regions 191 , 192 , 193 , 194 , and 195 in FIGS. 1 and 2.
  • regions 193 and 194 are formed simultaneously with each other and before the formation of regions 191 and 192 .
  • Regions 191 and 192 are also preferably formed simultaneously with each other.
  • Regions 191 , 192 , 193 , and 194 are preferably formed using a single implant mask.
  • a different implant mask is used to form region 195 , which can be formed before or after regions 191 , 192 , 193 , and 194 .
  • a gate electrode is formed over the surface of the substrate.
  • the gate electrode of step 735 can be similar to gate electrode 180 in FIGS. 1, 3, 4 , 5 , and 6 , and can also be similar to gate electrode 280 in FIG. 2.
  • Step 735 can be performed by, for example, forming a gate oxide layer over the surface of the substrate and forming a doped polysilicon layer over the gate oxide layer. Next, this structure can be etched, and then spacers can be formed around the etched structure.
  • source and drain regions are formed in the substrate.
  • the gate electrode can also be implanted simultaneously with the source and drain regions in step 740 .
  • the source region and the drain region in step 740 can be similar to source region 162 and drain region 160 , respectively, in FIGS. 1, 3, 4 , 5 , and 6 , and can also be similar to source region 262 and drain region 260 , respectively, in FIG. 2.
  • Step 740 can be performed by, for example, forming an implant mask over the surface of the substrate and the gate electrode and implanting a dopant into the substrate and the gate electrode.
  • the source and drain regions are simultaneously formed with each other and with the doping of the gate electrode such that a single implant mask and a single implant can be used to simultaneously form the source and drain regions and dope the gate electrode.
  • region 164 in FIGS. 1 and 2 is simultaneously formed with the source and drain regions and with the doping of the gate electrode.
  • a different implant mask and implant process is used to simultaneously form regions 165 and 173 in FIG. 1.
  • step 745 of flowchart 700 in FIG. 7 additional electrical contacts are formed over the surface of the substrate.
  • the electrical contacts of step 745 can include drain contact 161 and source contact 163 of FIGS. 1, 3, 4 , 5 , and 6 can also include drain contact 261 and source contact 263 of FIG. 2, and can further include gate contacts located over the gate electrodes in FIGS. 1, 2, 3 , 4 , 5 , and 6 .
  • the electrical contacts of step 745 can further include body contact 172 in FIG. 1 and contact 196 and substrate contact 197 in FIGS. 1 and 2.
  • Step 745 can be performed by, for example, performing a self-aligned silicide, or salicide, process.
  • each of the electrical contacts of step 745 are formed simultaneously with each other.
  • an interconnect system is formed over the semiconductor device and also over the surface of the substrate.
  • the interconnect system of step 750 can be a single-layered interconnect system or a multi-level interconnect system. Both types of interconnect systems are known in the art.
  • an opposite surface or back surface of the substrate is processed.
  • the back surface of the substrate can be thinned, and then a metal layer can be formed over the back surface of the substrate.
  • This metal layer can serve as a back metal for mounting the semiconductor component onto, for example, a lead frame.

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US9159803B2 (en) * 2012-08-21 2015-10-13 Freescale Semiconductor, Inc. Semiconductor device with HCI protection region
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EP1890335A1 (fr) 2006-08-16 2008-02-20 Austriamicrosystems AG Dispositif DMOS latéral et sa méthode de fabrication
US20090160015A1 (en) * 2007-12-20 2009-06-25 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
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WO2011125043A1 (fr) * 2010-04-09 2011-10-13 X-Fab Semiconductor Foundries Ag Transistors ldmos pour des technologies cmos et procédé de fabrication associé
US9159803B2 (en) * 2012-08-21 2015-10-13 Freescale Semiconductor, Inc. Semiconductor device with HCI protection region
US9559097B2 (en) * 2014-10-06 2017-01-31 Nxp Usa, Inc. Semiconductor device with non-isolated power transistor with integrated diode protection
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US9831232B2 (en) * 2015-10-02 2017-11-28 Nxp Usa, Inc. ESD protection device
US10134891B2 (en) * 2016-08-30 2018-11-20 United Microelectronics Corp. Transistor device with threshold voltage adjusted by body effect
CN111354798A (zh) * 2020-03-16 2020-06-30 吴健 双向非对称双通道开关器件及其制造方法
CN111354799A (zh) * 2020-04-10 2020-06-30 吴健 双向非对称双通道开关器件及其制造方法

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WO2003003452A2 (fr) 2003-01-09
US20040097019A1 (en) 2004-05-20

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