US20020089353A1 - Current mode logic gates for low-voltage high-speed applications - Google Patents

Current mode logic gates for low-voltage high-speed applications Download PDF

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Publication number
US20020089353A1
US20020089353A1 US09/114,780 US11478098A US2002089353A1 US 20020089353 A1 US20020089353 A1 US 20020089353A1 US 11478098 A US11478098 A US 11478098A US 2002089353 A1 US2002089353 A1 US 2002089353A1
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Prior art keywords
flip
flop
output
input
coupled
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Abandoned
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US09/114,780
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English (en)
Inventor
Abdellatif Bellaouar
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to US09/114,780 priority Critical patent/US20020089353A1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BELLAOUAR, ABDELLATIF
Priority to JP11197792A priority patent/JP2000049590A/ja
Priority to EP99202261A priority patent/EP0973262B1/de
Priority to AT99202261T priority patent/ATE442704T1/de
Priority to DE69941383T priority patent/DE69941383D1/de
Priority to US09/669,021 priority patent/US6492840B1/en
Priority to US09/669,025 priority patent/US6265898B1/en
Publication of US20020089353A1 publication Critical patent/US20020089353A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic

Definitions

  • This patent relates to current-mode logic (CML) circuitry and more specifically to a new low-voltage, high-speed gate family consisting of both OR/NOR and AND/NAND logic functions, as well as other more complex functions.
  • CML current-mode logic
  • CML Current mode logic
  • ECL emitter coupled logic
  • FIG. 1 shows one version of a conventional OR/NOR gate implemented in MOS CML.
  • the circuit is made up of stacked transistors pairs 3 - 4 and 5 - 6 which allows for differential inputs A/ ⁇ overscore (A) ⁇ and B/ ⁇ overscore (B) ⁇ to be applied, respectively.
  • Current source 7 maintains a constant current I through the legs of the circuit at all times.
  • FIG. 2 shows another commonly used CML circuit which overcomes the problems of the circuit in FIG. 1, but as will be discussed, has its own set of problems.
  • Singled-ended input signals A and B are inserted at the gates of transistors 10 and 11 .
  • Resistor 8 connects the drains of transistors 10 and 11 to V DD to provide a path for current to flow into current source 13 when either or both of these inputs are high (logic level 1).
  • This circuit is not limited to two inputs, although only two are shown, and overcomes the DC level shifting problem of the previous circuit by operating all the transistors at the same voltage level.
  • transistor 12 and resistor 9 are used to provide another path for current I to flow into current source 13 when both of the input transistors 10 and 11 are OFF.
  • the V ref input is a DC level which biases transistor 12 at the mid-point of the A and B input signal's voltage swing. If both A and B inputs are low (logic level 0), all the current I will flow through V ref transistor 12 . Then as inputs A and/or B turn on (logic level 1) current will switch and flow through transistors 10 and/or 11 .
  • OR (A+B) and it's complementary NOR ( ⁇ overscore (A+B) ⁇ ) outputs are generated.
  • Emitter coupled logic (ECL) circuits represent one family that has been extensively used in wireless applications such as the phase lock loop (PLL) in prescalers and optical communication systems. And more recently CMOS current mode logic is becoming prevalent in the GHz domain.
  • PLL phase lock loop
  • This invention describes a new family of current mode logic (CML) gates which includes OR/NOR, AND/NAND gates, and other more complex functions, all of which use a complementary feedback signal to drive the gate of the V ref transistor 12 (FIG. 2) rather than a DC voltage often found in more conventional CML gate circuits.
  • CML current mode logic
  • the circuit operates in a pseudo differential manner although it uses only single-ended inputs.
  • FCML feedback current mode logic circuit
  • FIG. 1 is a schematic diagram of a conventional OR/NOR gate in MOS CML.
  • FIG. 2 is a schematic diagram of another conventional OR/NOR gate with voltage reference in MOS CML.
  • FIG. 3 is a schematic diagram of an OR/NOR gate in MOS CML according to one embodiment of the invention.
  • FIG. 4 is a schematic diagram of an OR/NOR gate in bipolar technology according to another embodiment of the invention.
  • FIG. 5 is a schematic diagram of an AND/NAND gate implementation of the invention in MOS CML.
  • FIG. 6 illustrates simulation results of the DC characteristics for the basic OR/NOR gate of this invention in MOS CML.
  • FIG. 7 illustrates simulation results of the transient response for the basic OR/NOR gate of this invention in MOS CML.
  • FIG. 8 a shows a 3-input FCML gate in a D-type flip-flop function in the prescaler of a cellular phone.
  • FIG. 8 b is a 3-input FCML OR gate used as the mode select function in the prescaler application in a cellular phone.
  • FIG. 8 c is a block diagram of a prescaler circuit showing three FCML circuits used in flip-flop and OR gate functions.
  • FIG. 8 d is a block diagram of a phase-lock-loop in a cellular phone showing the prescaler function.
  • FIG. 8 e is a block diagram for a typical cellular phone showing the phase-lock-loop function.
  • FIG. 3 shows the schematic for the current mode logic gate 14 , according to the invention, which overcomes most of the problems discussed in the prior art.
  • the basic circuit is comprised of resistor 15 and transistors 17 and 18 . Additional inputs, indicating by shadowed transistor 21 at input C, can be provided by adding additional transistors in parallel with transistors 17 and 18 .
  • Resistor 16 and transistor 19 provide a path for current to flow when both inputs A and B (all inputs) are inhibited.
  • the sources of all the transistors 17 - 19 and 21 are tied together and connected to a constant current source 20 .
  • the power supply voltages are shown as V DD and V SS .
  • V DD may be quite small, for example 1.8 volts or less while the input voltage swings will typically range from 400 to 800 mVolts.
  • V SS is commonly operated at ground potential.
  • the current paths in the circuit are clearly seen to be through a) resistor 15 , transistor 17 , and current source 20 and/or b) resistor 15 , transistor 18 , and current source 20 or c) resistor 16 , transistor 19 , and current source 20 .
  • resistor 16 and transistor 19 provide a path for current to flow when both input signals, A and B, are low (0 state).
  • the gate of transistor 19 is controlled by tying it to the common drain connection of transistors 17 and 18 .
  • FCML complementary outputs O and ⁇ overscore (O) ⁇ , as shown. Operation of the circuit is as follows, assume that initially both inputs, A and B, are low (0) and transistors 17 and 18 are off such that output ⁇ overscore (O) ⁇ is high (1). In this initial condition, the feedback in the circuit causes transistor 19 to turn on and as a result output O is low (0).
  • FIG. 4 shows the same OR/NOR FCML circuit 14 implemented with bipolar technology. As shown, the resistors 22 - 23 , transistors 24 - 26 , and current source 27 match those of the MOS version discussed above, with the exception that now transistors 24 - 26 are bipolar transistors.
  • FIG. 5 shows another embodiment of the invention for an AND/NAND circuit which is the same circuit 14 as shown in FIG. 3, but with the inputs now being ⁇ overscore (A) ⁇ and ⁇ overscore (B) ⁇ . Therefore, all that is necessary to generate the AND/NAND function is to provide the complements A and B at the inputs to the circuit, as shown in FIG. 5. As in the earlier OR/NOR circuit, additional inputs can be included. The logic functions at the O and ⁇ overscore (O) ⁇ outputs then become ⁇ overscore (A) ⁇ + ⁇ overscore (B) ⁇ and ⁇ overscore (A) ⁇ + ⁇ overscore (B) ⁇ , respectively.
  • FIG. 6 shows simulation results for the DC characteristics of the OR/NOR FCML gate.
  • V DD is 1.8 volts
  • V SS is ground
  • the current source has 0.1 mA flowing through it. Only one input, a DC level, is used in this simulation.
  • the outputs O and ⁇ overscore (O) ⁇ have a swing of approximately 0.4 volts from 1.4 to 1.8 volts.
  • the output transition crossover point occurs at mid-range, 1.6 volts, of the required input voltage swing.
  • FIG. 7 shows simulation results of the transient response for the same circuit discussed in FIG. 6.
  • input A is low (0) and input B uses a pulse generator with amplitude varying from 1.4 to 1.8 volts.
  • the rise and fall times for the two outputs, O and ⁇ overscore (O) ⁇ , are shown.
  • the abscissa represents time in nSeconds.
  • FIGS. 8 a - 8 e show an example of this application with the gates used as both D-type flip-flops and OR gate functions in a PLL prescaler circuit.
  • FIG. 8 a is the schematic diagram of a D-type flip-flop 28 used in the prescaler function of a cellular phone.
  • the input to this flip-flop consists of a 3-input FCML gate 14 merged with other functions in the flip-flop circuit.
  • This identical 3-input flip-flop circuit 28 as well as another 2-input version of the same circuit 29 is used in the prescaler 31 function of the cellular phone, as shown below in FIG. 8 c.
  • FIG. 8 b shows the schematic for a 3-input FCML OR gate 14 used as the mode selection function 30 , also in the prescaler circuit 31 of FIG. 8 c.
  • FIG. 8 c is the block diagram for a prescaler 31 in a cellular phone. As illustrated, this circuit merges three (3) of the FCML gates; (i) a 3-input D-type flip-flop 28 , (ii) another 2-input D-type flip-flop 29 , and (iii) a 3-input FCML OR gate 30 with other conventional circuitry in the prescaler circuit.
  • FIG. 8 d is a block diagram for a typical phase-lock-loop (PLL) circuit 32 used in a cellular phone. This shows how the prescaler 31 , with the FCML gates, is used in the loop.
  • PLL phase-lock-loop
  • FIG. 8 e is a typical block diagram for a cellular phone showing the receiver and transmitter RF/IF portions, the baseband controller functions, the power supply, and the user input/output functions.
  • PLL phase-lock-loop
  • PLL phase-lock-loop
  • each of these phase-lock-loops has at least three (3) high speed gate circuits which can be enhanced through the use of the high-speed, low-voltage FCML gates of this invention.
  • a single analog/digital baseband is shown, a cellular phone could also use separate analog and digital basebands.
  • FCML gate family Although this represents one important application of the FCML gate family, many other uses where high-speed, very low voltage logic gates are needed will gain an advantage from this family of gate circuits.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
US09/114,780 1998-07-13 1998-07-13 Current mode logic gates for low-voltage high-speed applications Abandoned US20020089353A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US09/114,780 US20020089353A1 (en) 1998-07-13 1998-07-13 Current mode logic gates for low-voltage high-speed applications
JP11197792A JP2000049590A (ja) 1998-07-13 1999-07-12 低電圧高速アプリケ―ション用電流モ―ド論理ゲ―ト
EP99202261A EP0973262B1 (de) 1998-07-13 1999-07-12 Logische Schaltung in Stromschaltertechnik
AT99202261T ATE442704T1 (de) 1998-07-13 1999-07-12 Logische schaltung in stromschaltertechnik
DE69941383T DE69941383D1 (de) 1998-07-13 1999-07-12 Logische Schaltung in Stromschaltertechnik
US09/669,021 US6492840B1 (en) 1998-07-13 2000-09-25 Current mode logic gates for low-voltage high-speed applications
US09/669,025 US6265898B1 (en) 1998-07-13 2000-09-25 Current mode logic gates for low-voltage high speed applications

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US09/114,780 US20020089353A1 (en) 1998-07-13 1998-07-13 Current mode logic gates for low-voltage high-speed applications

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US09/669,021 Division US6492840B1 (en) 1998-07-13 2000-09-25 Current mode logic gates for low-voltage high-speed applications
US09/669,025 Division US6265898B1 (en) 1998-07-13 2000-09-25 Current mode logic gates for low-voltage high speed applications

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US09/669,021 Expired - Lifetime US6492840B1 (en) 1998-07-13 2000-09-25 Current mode logic gates for low-voltage high-speed applications
US09/669,025 Expired - Lifetime US6265898B1 (en) 1998-07-13 2000-09-25 Current mode logic gates for low-voltage high speed applications

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US09/669,025 Expired - Lifetime US6265898B1 (en) 1998-07-13 2000-09-25 Current mode logic gates for low-voltage high speed applications

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EP (1) EP0973262B1 (de)
JP (1) JP2000049590A (de)
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DE (1) DE69941383D1 (de)

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US20050285630A1 (en) * 2004-06-28 2005-12-29 Technion Research & Development Foundation Ltd. Multiple-output transistor logic circuit

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Publication number Publication date
US6492840B1 (en) 2002-12-10
EP0973262B1 (de) 2009-09-09
US6265898B1 (en) 2001-07-24
EP0973262A2 (de) 2000-01-19
JP2000049590A (ja) 2000-02-18
ATE442704T1 (de) 2009-09-15
DE69941383D1 (de) 2009-10-22
EP0973262A3 (de) 2000-10-11

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