US20010055022A1 - Serial access memory and data write/read method - Google Patents

Serial access memory and data write/read method Download PDF

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Publication number
US20010055022A1
US20010055022A1 US09/773,024 US77302401A US2001055022A1 US 20010055022 A1 US20010055022 A1 US 20010055022A1 US 77302401 A US77302401 A US 77302401A US 2001055022 A1 US2001055022 A1 US 2001055022A1
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data
write
read
register
memory cells
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Shigemi Yoshioka
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Assigned to OKI ELECTRIC INDUSTRY CO., LTD. reassignment OKI ELECTRIC INDUSTRY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YOSHIOKA, SHIGEMI
Publication of US20010055022A1 publication Critical patent/US20010055022A1/en
Priority to US10/307,399 priority Critical patent/US6728155B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

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  • the present invention relates to a serial access memory and a data write/read method applicable thereto.
  • the prior art serial access memory 1 is provided with a memory cell array 11 , a memory control portion 12 , an X-address means 13 , a Y-address means on the write side(referred to “write Y-address means” hereinafter) 14 , a Y-address means on the read side (referred to “read Y-address means”) 15 , the first transfer means group on the write side(referred to as “write side first transfer means group” hereinafter) 16 , a register group on the write side (referred to as “write register group” hereinafter) 17 , the second transfer means group on the write side (referred to as “write side second transfer means group” hereinafter) 18 , the first transfer means group on the read side (referred to “read side second transfer means group”) 19 , a register group on the read side (referred to as “read register group”) 20 , the second transfer means group on the read side (referred to as “read side second transfer means group” hereinafter) 21 , an
  • the X-address means 13 is controlled to select one word line from a plurality of word lines WL 1 to WLn (n: positive integer) and to put the selected word line in a logical high-level state (referred to as “H-level” hereinafter) by the memory control portion 12 .
  • the memory cell array 11 is made up of a plurality of memory cells MC 11 to MCmn (m: positive integer), each of which is arranged at each of intersections made by the plural word lines WL 1 to WLn and the plural bit line pairs BL 1 , /BL 1 to BLm, /BLm.
  • Each of the memory cells MC 11 to MCmn includes one each of a transistor (not shown) and a capacitor (not shown).
  • bit line pairs BL 1 , /BL 1 to BL 1 , /BLm are respectively connected with corresponding sense amplifiers SA 1 to SAm, with which the potential variation appearing on the bit line pairsBL 1 , /BL 1 to BLm, /BLm is amplified.
  • the bit line pairs BL 1 , /BL 1 to BLm, /BLm are connected with the write register group 17 through the write side first transfer means group 16 .
  • the write side first transfer means group 16 is made up of a plurality of write side first transfer means 16 - 1 to 16 -m of which each corresponds to each of the bit line pairs BL 1 , /BL 1 to BLm, /BLm.
  • the write register group 17 is made up of a plurality of write registers Wreg- 1 to Wreg-m of which each corresponds to each of the bit line pairs BL 1 , /BL 1 to BLm, /BLm.
  • Each of the write side first transfer means 16 - 1 to 16 -m is made up of two transistors.
  • the bit line BL 1 is connected with the write register Wreg- 1 through the drain and source of one transistor forming the write side first transfer means 16 - 1 while the bit line /BL 1 is connected with the write register Wreg- 1 through the drain and source of the another transistor forming the write side first transfer means 16 - 1 .
  • the ON/OFF control of these 2 ⁇ m transistors forming the write side first transfer means 16 - 1 to 16 -m is carried out with a control signal WT.
  • the write register group 17 is connected with write data buses WD, /WD through the write side second transfer means group 18 .
  • This write side second transfer means group 18 is made up of a plurality of write side second transfer means 18 - 1 to 18 -m, which correspond to the write registers Wreg- 1 to Wreg-m making up the write register group 17 , respectively.
  • Each of the write side second transfer means 18 - 1 to 18 -m is made up of two transistors.
  • the write register Wreg- 1 is connected with write data buses WD, /WD through respective drains and sources of two transistors forming the write side second transfer means 18 - 1 .
  • Each of the write side second transfer means 18 - 1 to 18 -m is made up so as to receive the write Y-address signals YW 1 to YWm outputted from the write Y-address means 14 , and the ON/OFF control of two transistors forming each of the write side second transfer means 18 - 1 to 18 -m is carried out with the write Y-address signals YW 1 to YWm.
  • the write data buses WD, /WD are connected with an input terminal DIN through the input means 22 .
  • the bit line pairs BL 1 , /BL 1 to BLm, /BLm are connected with the read register group 20 through the read side first transfer means group 19 .
  • the read side first transfer means group 19 is made up of a plurality of read side first transfer means 19 - 1 to 19 -m, of which each corresponds to each of the bit line pairs BL 1 , /BL 1 to BLm, /BLm.
  • the read register group 20 is made up of a plurality of read registers Rreg- 1 to Rreg-m, of which each corresponds to each of the bit line pairs BL 1 , /BL 1 to BLm, /BLm.
  • Each of the read side first transfer means 19 - 1 to 19 -m is composed of two transistors.
  • the bit line BL 1 is connected with the read register Rreg- 1 through the drain and source of one transistor forming the read side first transfer means 19 - 1 while the bit line /BL 1 is connected with the read register Rreg- 1 through the drain and source of the another transistor forming the read side first transfer means 19 - 1 .
  • the ON/OFF control of these 2 ⁇ m transistors forming the read side first transfer means 19 - 1 to 19 -m is carried out with a control signal RT.
  • the read register group 20 is connected with read data buses RD, /RD through the read side second transfer means group 21 .
  • This read side second transfer means group 21 is composed of a plurality of read side second transfer means 21 - 1 to 21 -m respectively corresponding to the read registers Rreg- 1 to Rreg-m which make up the read register group 20 .
  • Each of the read side second transfer means 21 - 1 to 21 -m is made up of two transistors.
  • the read register Rreg- 1 is connected with read data buses RD, /RD through the respective drains and sources of two transistors forming the read side second transfer means 21 - 1 .
  • Each of the read side second transfer means 21 - 1 to 21 -m is formed so as to receive the read Y-address signals YR 1 to YRm outputted from the read Y-address means 15 , and the ON/OFF control of two transistors forming each of the read side second transfer means 21 - 1 to 21 -m is carried out with the read Y-address signals YR 1 to YRm.
  • the read data buses RD, /RD are connected with an output terminal DOUT through an output means 23 .
  • FIG. 12 is a timing chart for describing the write operation of the serial access memory 1 . The write operation will be described with the passage of time as shown in the figure.
  • ⁇ Time t 1 The write operation is commenced when a write X-address WXAD is serially inputted to the memory control portion 12 .
  • a write address enable signal WADE of the H-level is inputted in advance to the memory control portion 12 .
  • the most significant bit (MSB) data Am of the write X-address WXAD is taken in the memory control portion 12 .
  • each bit data of the write X-address WXAD is taken in sequence in the memory control portion 12 in synchronism with a clock signal CLK.
  • the memory control portion 12 detects the write enable signal WE of the H-level in the rise timing of the clock signal CLK. With this, the substantial write operation is commenced.
  • the write Y-address means 14 selects the write Y-address signal YW 1 from the write Y-address signals YW 1 to YWm and puts it in the H-level.
  • the input data DI 1 inputted from the input terminal DIN has been transmitted to the write data buses WD, /WD through the input means 22 . Since the write side second transfer means 18 - 1 is put in the ON state with the write Y-address signal YW 1 , the input data DI 1 is stored in the write register Wreg- 1 .
  • the write Y-address means 14 selects the write Y-address signals YW 2 to YWm in sequence from the write Y-address signals YW 1 to YWm in synchronism with the clock signal CLK and puts each of them in the H-level.
  • the input data DI 2 to DIm are inputted to the input terminal DIN in sequence, and each of the input data DI 2 to DIm is stored in the write registers Wreg- 2 to Wreg-m.
  • serial access memory 1 of the line access type it is made possible to execute the write operation on the basis of X-address by X-address (although described about only the word line WL 1 here).
  • FIG. 13 is a timing chart for describing the read operation in connection with the serial access memory 1 . The read operation will now be described with the passage of time as shown in the figure.
  • ⁇ Time t 1 The read operation is commenced when serially inputting a read X-address RXAD to the memory control portion 12 .
  • a read address enable signal RADE of the H-level is inputted in advance to the memory control portion 12 .
  • the most significant bit (MSB) data Am of the read X-address RXAD is taken in the memory control portion 12 .
  • each bit data of the read X-address RXAD is taken in sequence in the memory control portion 12 in synchronism with a clock signal CLK.
  • the memory control portion 12 detects the read enable signal RE of the H-level in the rise timing of the clock signal CLK. With this, the substantial read operation is commenced.
  • the read Y-address means 15 selects the read Y-address signal YR 1 from the read Y-address signals YR 1 to YRm and puts it in the H-level. Since the read side second transfer means 21 - 1 is put in the ON state with the read Y-address signal YR 1 of the H-level, the data stored in the read register Rreg- 1 is transmitted to the read data buses RD, /RD. The data transmitted to the read data buses RD, /RD is outputted as an output data DO 1 from the output terminal DOUT through the output means 23 .
  • the read Y-address means 15 selects in sequence the read Y-address signals YR 2 to YRm from the read Y-address signals YR 1 to YRm in synchronism with the clock signal CLK and puts each of them in the H-level. As this goes on, each data stored in the read registers Rreg- 2 to Rreg-m is transmitted in sequence to read data buses RD, /RD. Each of data transmitted in sequence to the data buses RD, /RD is outputted as the output data D 02 to DOm from the output terminal DOUT through the output means 23 .
  • serial access memory 1 of the line access type it is made possible to execute the read operation on the basis of X-address by X-address (although described about only the word line WL 1 here).
  • a write data transfer time a read data transfer time
  • a wait time period of time t 3 through t 4 , which is about 1.5 ⁇ s
  • the invention has been made in view of the problems as described above and a main object thereof is to provide an improved serial access memory capable of reducing the test time thereof and a data write/read method applicable thereto.
  • a data write/read method applicable to a serial access memory of the class in which there are provided a plurality of memory cells arranged at each of intersections made by a plurality of word lines and a plurality of bit lines, the first register having a capacity capable of storing one word data stored in the plural memory cells connected with each word line, and the second register having a capacity capable of storing one word data stored in the plural memory cells connected with each word line.
  • This method is characterized by including the first write step of storing the first input serial data of one word in the first register, and the second write step of transferring the one word data stored in the first register in the first write step, to the plural memory cells connected with each of a plurality of first selected word lines selected from the plural word lines. According to this method, if the first input serial data is stored in the first register only once, the data come to be written in the memory cells connected with plural word lines. Thus, it is made possible to reduce the time required for the data write.
  • another data write/read method applicable to the serial access memory further includes the following two steps in addition to the steps of the method according to the first aspect of the invention, that is, the third write step of storing the second input serial data of one word in the first register, the second input serial data of one word being obtained by inverting the logical level of each bit of the first input serial data, and the fourth write step of transferring the one word data stored in the first register in the third write step, to a plurality of memory cells connected with each of a plurality of the second selected word lines selected from the plural word lines. Furthermore, according to the third aspect of the invention, there is provided still another data write/read method applicable to the serial access memory.
  • This method further includes the following steps in addition to the steps of the method according to the first aspect of the invention, that is, the third write step of transferring the data stored in the first register in the first write step, through a logic level inversion and transfer means serving to invert the logical level of the data on the basis of bit by bit, to a plurality of memory cells connected with each of a plurality of the second selected word lines selected from the plural word lines.
  • the one word data stored in the plural memory cells connected with the first selected word line and the one word data stored in the plural memory cells connected with the second selected word line have such a relation there between that the logical level of each bit of the latter one word data is obtained by inverting the logical level of each corresponding bit of the former one word data.
  • this method further includes the following two steps in addition to the steps of the method according to the first aspect of the invention, that is, the first read step of selecting two word lines from the plural first selected word lines, transferring the storage data of a plurality of memory cells connected with one of the selected two word lines to the second register, and transferring the storage data of a plurality of memory cells connected with the other word line of the selected two word line to the first register, and the second read step of serially reading out the data transferred to the first register in the first read step and serially reading out the data transferred to the second register.
  • the data write/read method applicable to the serial access memory according to the invention is characterized by including the first read step of selecting one first selected word line from the plural first selected word lines and transferring the data stored in a plurality of memory cells connected with the one first selected word line to the second register, the second read step of selecting one second selected word line from the plural second selected word lines and transferring the storage data of a plurality of memory cells connected with the one second selected word line to the first register, and the third read step of serially reading out the data transferred to the second register according to the first read step and serially reading out the data transferred to the first register according to the second read step. Since the first register and the second register are used when reading the data, it becomes possible to read out the storage data from the memory cells connected with each of two word lines at the same time. The time needed for reading the data can be reduced, accordingly.
  • the data write/read method applicable to the serial access memory includes a step of comparing the data serially read out from the first register with the data serially read out from the second register on the bit by bit basis. According to this method, it is made easier to judge whether or not the data is correctly stored in each memory cell and whether or not the data is rightly read out from each memory cell as well.
  • the data write/read method applicable to the serial access memory according to the invention is characterized by including the logical level inversion step of inverting the logical level of each bit of the data which is serially read out from the first register prior to the data comparison step.
  • the serial data read out from the first register and the serial data read out from the second register have such a relation there between that the logical level of each bit of the data from the second register is obtained by inverting the logical level of each corresponding bit of the data from the first register, the comparison of the above two data from the first and second registers is made easier if inverting the logical level of each bit of the data from the first register before executing the step of comparison.
  • a serial access memory wherein there are provided a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines, a register having a capacity capable of storing one word data stored in the plural memory cells connected with each word line and storing input serial data of one word, and a register data transfer means transferring the one word data stored in the register as it is or after inverting the logical level of each bit thereof, to a plurality of memory cells connected with one selected word line selected from the plural word lines.
  • the serial access memory it becomes possible to write the data in the memory cells connected with a plurality of word lines when writing and storing an input serial data in the first register only once. Moreover, it becomes possible to selectively store either the data stored in the register or the logical level inverted data stored in the register on the word line by word line basis.
  • a serial access memory wherein there are provided a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines, a register having m pieces of a data storage region (referred to as “m data storage regions ” hereinafter) and transferring the data stored in m data storage regions, to each of m pieces of memory cell (referred to as “m memory cells” hereinafter) connected with one selected word line selected from the plural word lines, m pieces of a bus data transfer means (referred to as “m bus data transfer means” hereinafter) being assigned to each of m data storage regions and transferring the data transmitted to the data bus to each data storage region, and a bus data transfer instruction means selecting in sequence m bus data transfer means one each or a plurality of them each and instructing the selected bus data transfer means to transfer the data transmitted in sequence to the data buses, to m data storage regions in sequence.
  • a serial access memory wherein there are provided a plurality of memory cells which are arranged at each of intersections made by a plurality of word lines and a plurality of bit lines, a register having the m data storage regions and transferring the data stored in the m data storage regions to each of the m memory cells connected with one selected word line selected from the plural word lines, an address means for asserting the m address signals in sequence and outputting the asserted address signals, and the m data transfer means being assigned to each of the m data storage regions and having the function of transferring the m address signals to each of the data storage regions as the data, and also having the function of transferring the input serial data transmitted to the data bus, to each of the m data storage regions with the m address signals.
  • the logical level of the data stored in one of the data storage regions comes to be different from that of the data stored in all the other data storage regions in a certain timing, and the address of the data storage region storing the data having the logical level which is different from that of the other data, is shifted every change of the address signal to be asserted. Therefore, the position of the memory cell storing the data having the different logical level is shifted by incrementing the address of the word line selected from the plural word lines by one, every time of asserting the address signal in sequence.
  • FIG. 1 is a circuit diagram for showing the constitution of a serial access memory according to the first embodiment of the invention.
  • FIG. 2 is a timing chart for describing the test write operation of the serial access memory illustrated in FIG. 1.
  • FIG. 3 is a timing chart for describing the test read operation of the serial access memory illustrated in FIG. 1.
  • FIG. 4 is a circuit diagram for showing the constitution of a serial access memory according to the second embodiment of the invention.
  • FIG. 5 is a timing chart for describing the test write operation of the serial access memory illustrated in FIG. 4.
  • FIG. 6 is a circuit diagram for showing the constitution of a serial access memory according to the third embodiment of the invention.
  • FIG. 7 is a timing chart for describing the test write operation of the serial access memory illustrated in FIG. 6.
  • FIG. 8 is a circuit diagram for showing the constitution of a serial access memory according to the fourth embodiment of the invention.
  • FIG. 9 is a circuit diagram for showing the constitution of a serial access memory according to the fifth embodiment of the invention.
  • FIG. 10 is a timing chart for describing the test write operation of the serial access memory shown in FIG. 9.
  • FIG. 11 is a circuit diagram for showing the constitution of a prior art serial access memory.
  • FIG. 12 is a timing chart for describing the write operation of the prior art serial access memory shown in FIG. 11.
  • FIG. 13 is a timing chart for describing the read operation of the prior art serial access memory shown in FIG. 11.
  • FIG. 1 is a diagrammatic view showing the constitution of a serial access memory 101 according to the first embodiment of the invention.
  • the serial access memory 101 is provided with a memory cell array 11 , a memory control portion 112 , an X-address means 13 , a write Y-address means 14 , a read Y-address means 15 , a write side first transfer means group 16 , a write register group 17 , a write side second transfer means group 18 , a read side first transfer means group 19 , a read register group 20 , a read side second transfer means group 21 , an input/output means 122 , and an output means 123 .
  • the serial access memory 101 has such a structure that the memory control portion 12 , the input means 22 and the output means 23 of the prior art serial access memory 1 are replaced by the memory control portion 112 , the input/output means 122 and the output means 123 , respectively.
  • the X-address means 13 is controlled to select one word line from a plurality of word lines WL 1 to WLn (n: positive integer) and to put the selected word line in the H-level by the memory control portion 112 .
  • the memory cell array 11 is made up of a plurality of memory cells MC 11 to MCmn (m: positive integer), each of which is arranged at each of intersections made by a plurality of word lines WL 1 to WLn and a plurality of bit line pairs BL 1 , /BL 1 to BLm, /BLm.
  • Each of the memory cells MC 11 to MCmn is made up of one each of a transistor (not shown) and a capacitor (not shown).
  • bit line pairs BL 1 , /BL 1 to BLm, /BLm are connected with a plurality of sense amplifiers SA 1 to SAm, by which a potential variation appearing on the bit line pairs BL 1 , /BL 1 to BLm, /BLm is amplified.
  • the bit line pairs BL 1 , /BL 1 to BLm, /BLm are connected with the write register group 17 through the write side first transfer means group 16 .
  • the write side first transfer means group 16 is made up of a plurality of write side first transfer means 16 - 1 to 16 -m which correspond to the bit line pairs BL 1 , /BL 1 to BLm, /BLm, respectively.
  • the write register group 17 is composed of a plurality of write registers Wreg- 1 to Wreg-m which correspond to the bit line pairs BL 1 , /BL 1 to BLm, /BLm, respectively.
  • Each of the write side first transfer means 16 - 1 to 16 -m is made up of two transistors.
  • the bit line BL 1 is connected with the write register Wreg- 1 through the drain and source of one transistor forming the write side first transfer means 16 - 1 while the bit line /BL 1 is connected with the write register Wreg- 1 through the drain and source of the other transistor forming the write side first transfer means 16 - 1 .
  • the ON/OFF control of these 2 ⁇ m transistors forming the write side first transfer means 16 - 1 to 16 -m is carried out with a control signal WT.
  • the write register group 17 is connected with write data buses WD, /WD through the write side second transfer means group 18 .
  • This write side second transfer means group 18 is made up of a plurality of write side second transfer means 18 - 1 to 18 -m corresponding to the write registers Wreg- 1 to Wreg-m, respectively, which make up the write register group 17 .
  • Each of the write side second transfer means 18 - 1 to 18 -m is made up of two transistors.
  • the write register Wreg- 1 is connected with write data buses WD, /WD through respective drains and sources of two transistors making up the write side second transfer means 18 - 1 .
  • Each of the write side second transfer means 18 - 1 to 18 -m is arranged so as to receive the write Y-address signals YW 1 to YWm outputted from the write Y-address means 14 , and the ON/OFF control of two transistors making up each of the write side second transfer means 18 - 1 to 1 8 -m is carried out with the write Y-address signals YW 1 to YWm.
  • the write data buses WD, /WD are connected with an input terminal DIN through an input/output means 122 .
  • the bit line pairs BL 1 , /BL 1 to BLm, /BLm are connected with the read register group 20 through the read side first transfer means group 19 .
  • the read side first transfer means group 19 is made up of a plurality of read side first transfer means 19 - 1 to 19 -m which correspond to the bit line pairs BL 1 ,/BL 1 to BLm, /BLm, respectively.
  • the read register group 20 is made up of a plurality of read registers Rreg- 1 to Rreg-m which correspond to the bit line pairs BL 1 , /BL 1 to BLm, /BLm, respectively.
  • Each of the read side first transfer means 19 - 1 to 19 -m is made up of two transistors.
  • the bit line BL 1 is connected with the read register Rreg- 1 through the drain and source of one transistor forming the read side first transfer means 19 - 1 while the bit line /BL 1 is connected with the read register Rreg- 1 through the drain and source of the other transistor forming the read side first transfer means 19 - 1 .
  • the ON/OFF control of 2 ⁇ m transistors forming the read side first transfer means 19 - 1 to 19 -m is carried out with a control signal RT.
  • the read register group 20 is connected with read data buses RD, /RD through the read side second transfer group 21 .
  • This read side second transfer means group 21 is made up of a plurality of read side second transfer means 21 - 1 to 21 -mrespectively corresponding to the read registers Rreg- 1 to Rreg-m, which make up the read register group 20 .
  • Each of the read side second transfer means 21 - 1 to 21 -m is made up of two transistors.
  • the read register Rreg- 1 is connected with read data buses RD, /RD through respective drains and sources of two transistors forming the read side second transfer means 21 - 1 .
  • Each of the read Y-address signals YR 1 to YRm outputted from the read Y-address means 15 is inputted to each of the read side second transfer means 21 - 1 to 21 -m, and the ON/OFF control of two transistors forming each of the read side second transfer means 21 - 1 to 21 -m is carried out with the read Y-address signals YR 1 to YRm.
  • the read data buses RD, /RD are connected with an output terminal DOUT through the output means 123 .
  • the input/output means 122 located on the write side is connected with the output means 123 located on the read side through the second data buses RD 2 , /RD 2 .
  • serial access memory 101 As arranged above will now be describe with reference to FIGS. 2 and 3.
  • This serial access memory 101 is prepared for the purpose of reducing the test time thereof, so that the data write/read operation thereof will be described in connection with the test by which it is judged whether or not a predetermined data as written in the serial access memory 101 can be correctly read out without any failure.
  • FIG. 2 is a timing chart for describing the write operation executed during the test of the serial access memory 101 , that is, the test write operation.
  • the test write operation will be described with the passage of time as indicated in the figure.
  • ⁇ Time t 1 In starting the test write operation, a test mode signal TM is inputted to the memory control portion 112 .
  • the test write operation is commenced by serially inputting a write X-address WXAD to the memory control portion 112 .
  • a write address enable signal WADE of the H-level is inputted in advance to the memory control portion 112 in order to make it possible for the memory control portion 112 to take in the write X-address WXAD.
  • the most significant bit (MSB) data Am of the write X-address WXAD is taken in the memory control portion 112 , and thereafter, each bit data of the write X-address WXAD is taken in sequence in the memory control portion 112 in synchronism with a clock signal CLK.
  • the memory control portion 112 detects the write enable signal WE of the H-level in the rise timing of the clock signal CLK. With this, the substantial test write operation is commenced.
  • the write Y-address means 14 selects the write Y-address signal YW 1 from the write Y-address signals YW 1 to YWm and puts it in the H-level.
  • the input data DI 1 inputted from the input terminal DIN is transmitted to the write data buses WD, /WD through the input/output means 122 . Since the write side second transfer means 18 - 1 is put in the ON state with the write Y-address signal YW 1 of the H-level, the input data DI 1 is stored in the write register Wreg- 1 .
  • the write Y-address means 14 selects in sequence the write Y-address signals YW 2 to YWm from the write Y-address signals YW 1 to YWm in synchronism with the clock signal CLK and puts each of them in the H-level.
  • the input data D 12 to DIm are being inputted in sequence to the input terminal DIN, and each of the input data D 12 to DIm is stored in each of the write registers Wreg- 2 to Wreg-m, correspondingly.
  • the write operation for writing the input data DI 1 to DIm to the write register group 17 is executed only once, and the input data DI 1 to DIm written in the write register group 17 are then transferred to all the memory cells MC 11 to MCmn. Therefore, the time needed for storing the data in all the memory cells MC 11 to MCmn can be reduced to a great extent as compared with the prior art write operation in which the input data is written in the write register group 17 on the word line byword line basis.
  • FIG. 3 is a timing chart for describing the read operation executed during the test of the serial access memory 101 , that is, the test read operation executed following the test write operation as shown in FIG. 2. The test read operation will be described with the passage of time as indicated in the figure.
  • ⁇ Time t 1 In starting the test read operation, a test mode signal TM is inputted to the memory control portion 112 .
  • the test read operation is commenced by serially inputting a read X-address RXAD to the memory control portion 112 .
  • a read address enable signal RADE of the H-level is inputted in advance in order to make it possible for the memory control portion 112 to take in the read X-address RXAD.
  • the most significant bit (MSB) data Am of the read X-address RXAD is taken in the memory control portionl 12 , and thereafter, each bit data of the read X-address RXAD is taken in the memory control portion 112 in sequence in synchronism with a clock signal CLK.
  • the memory control portion 112 detects the read enable signal RE of the H-level in the rise timing of the clock signal CLK. With this, the substantial read operation is commenced.
  • the read Y-address means 15 selects a read Y-address signal YR 1 from the read Y-address signals YR 1 to YRm and puts it in the H-level. Since the read side second transfer means 21 - 1 is put in the ON state with the read Y-address signal YR 1 of the H-level, the data stored in the read register Rreg- 1 is transmitted to the output means 123 through the read data buses RD, /RD.
  • the write Y-address means 14 selects the write Y-address signal YW 1 from the write Y-address signals YW 1 to YWm and puts it in the H-level. Since the write side second transfer means 18 - 1 is put in the ON state with the write Y-address signal YW 1 of the H-level, the data stored in the write register Wreg- 1 is transmitted to the input/output means 122 through the write data buses WD, /WD, and further transmitted to the output means 123 through the second read data buses RD 2 , /RD 2 .
  • the output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from the second read data buses RD 2 , /RD 2 and determines if they coincide with each other or not.
  • the comparison result is outputted from the output terminal DOUT as an output data DOIc.
  • a comparison means provided in the output means 123 maybe an exclusive-OR gate (ExOR), for instance.
  • the read Y-address means 15 selects in sequence the read Y-address signals YR 2 to YRm from the read Y-address signals YR 1 to YRm in synchronism with the clock signal CLK and puts each of them in the H-level. As this goes on, each data stored in the read registers Rreg- 2 to Rreg-m is transmitted in sequence to the output means 123 through the read data buses RD, /RD.
  • the write Y-address means 14 selects in sequence the write Y-address signals YW 2 to YWm from the write Y-address signals YW 1 to YWm in synchronism with the clock signal CLK and put seach of them in the H-level.
  • each data stored in the write registers Wreg- 2 to Wreg-m is transmitted to the output means 123 through the input/output means 122 and the second read data buses RD 2 , /RD 2 .
  • the output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from the second read data buses RD 2 ,/RD 2 and judges if they coincide with each other or not.
  • the comparison result is outputted from the output terminal DOUT as an output data DO 2 c, DO 3 c, . . . , and DOmc.
  • the wait time can be reduced to about a half, and the time required for the test read operation can be reduced to a great extent.
  • the read Y-address signals YR 1 to YRm are selected in sequence and put in the H-level by the read Y-address means 15 at time t 5 and thereafter.
  • the write Y-address signals YW 1 to YWm are also selected in sequence and put in the H-level by the write Y-address means 14 .
  • the data train stored in the read register group 20 and the same stored in the write register group 17 are transmitted to the output means 123 on the basis of bit by bit, and are compared with each other by the data comparison means provided in the output means 123 on the bit by bit basis.
  • the output means 123 if provided with a switch means, can alternately output the data transmitted from the read data buses RD, /RD and the data transmitted from the second read data buses RD 2 , /RD 2 from the output terminal DOUT by means of that switch means. Accordingly, there is no need for the output means 123 to be provided with any data comparison circuit. This allows the output means 123 to have a more compact structure.
  • the sequential selection of the write Y-address signals YW 1 to YWm by the write Y-address means 14 maybe carried out after finishing the sequential selection of the read Y-address signals YR 1 to YRm by the read Y-address means 15 .
  • each data stored in the write registers Wreg- 1 to Wreg-m is transmitted to the output means 123 after all data stored in the read Y-address registersRreg- 1 to Rreg-m have been transmitted to the output means 123 .
  • the control of the read Y-address means 15 and the write Y-address means 14 are made easier as compared with the case where the sequential selection of the read Y-address signals YR 1 to YRm by the read Y-address means 15 and the sequential selection of the write Y-address signals YW 1 to YWm by the write Y-address means 14 are carried out alternately.
  • the scale of the memory control portion 112 can be reduced in both of the hardware and the software thereof.
  • FIG. 4 is a diagrammatic view showing the structure of a serial access memory 201 according to the second embodiment of the invention.
  • This serial access memory 201 can be made up by adding two inverters 211 , 212 to the serial access memory 101 according to the first embodiment of the invention. These inverters 211 , 212 are arranged between the second read data buses RD 2 , /RD 2 and the output means 123 . These inverters invert the logical level of the data outputted from the input/output means 122 to the second read data buses RD 2 , /RD 2 and supply the data having the inverted logical level to the output means 123 . As to the parts other than the inverters 211 , 212 , the serial access memory 201 has the same structure and parts as the serial access memory 101 .
  • serial access memory 201 As arranged above will be described with reference to FIG. 5.
  • the serial access memory 201 is provided for the purpose of reducing the test time thereof. Therefore, the write/read operation will be described in connection with the test for determining whether or not a predetermined data as written in the serial access memory 201 can be correctly read out without any failure.
  • FIG. 5 is a timing chart for describing the test write operation executed during the test of the serial access memory 201 .
  • the test write operation will be described with the passage of time as indicated in the figure.
  • ⁇ Time t 1 In starting the test write operation, a test mode signal TM is inputted to the memory control portion 112 .
  • the test write operation is commenced by serially inputting a write X-address WXAD to the memory control portion 112 .
  • a write address enable signal WADE of the H-level is inputted in advance to the memory control portion 112 in order to make it possible for the memory control portion 112 to take in the write X-address WXAD.
  • the most significant bit (MSB) data Am of the write X-address WXAD is taken in the memory control portion 112 , and thereafter, each bit data of the write X-address WXAD is taken in sequence in the memory control portion 112 in synchronism with a clock signal CLK.
  • the memory control portion 112 detects the write enable signal WE of the H-level in the rise timing of the clock signal CLK. With this, the substantial write operation is commenced.
  • the write Y-address means 14 selects the write Y-address signal YW 1 from the write Y-address signals YW 1 to YWm and puts it in the H-level.
  • the input data DI 1 inputted from the input terminal DIN is transmitted to the write data buses WD, /WD through the input/output means 122 . Since the write side second transfer means 18 - 1 is put in the ON state by the write Y-address signal YW 1 of the H-level, the input data DI 1 is stored in the write register Wreg- 1 .
  • the write Y-address means 14 selects in sequence the write Y-address signals YW 2 to YWm from the write Y-address signals YW 1 to YWm in synchronism with the clock signal CLK and puts each of them in the H-level.
  • the input data DI 2 to DIm are being inputted in sequence to the input terminal DIN, and each of the input data D 12 to DIm is stored in the write registers Wreg- 2 to Wreg-m.
  • the serial access memory 201 repeats the similar test write operation as shown in FIG. 5, thereby storing the input data /DI 1 to /DIm in the memory cells MC 12 to MCm 2 , MC 14 to MCm 4 , MC 16 to MCm 6 , . . . respectively connected with word lines given an even number (n), that is,WL 2 , WL 4 , WL 6 , . . . , and so on.
  • the input data /DI 1 to /DIm are the data obtained by inverting the logical level of the input data DI 1 to DIm. For instance, if the input data DI 1 is “0”, the input data /DI 1 becomes “1”.
  • the data transfer to all the word lines WL 1 to WLn is carried out after the storage operation of the input data to the write register group 17 is carried out once each with respect to the input data DI 1 to DIm and the input data /DI 1 to /DIm. Therefore, the time required for storing the data in all the memory cells MC 11 to MCmn is reduced to a great extent as compared with the write operation of the prior art serial access memory 1 wherein the input data is stored in the write register group 17 every access to each word line.
  • the serial access memory 201 performs the test read operation following the test write operation as shown in FIG. 5.
  • the test read operation of the serial access memory 201 is executed in the same manner as that of the serial access memory 101 as shown in FIG. 3. That is, the data stored in the memory cells connected with one of the paired word lines is transferred to the read register group 20 while the data stored in the memory cells connected the other of the paired word lines is transferred to the write register group 17 , and the data train stored in the read register group 20 and the data train stored in the write register group 17 are compared with each other by the output means 123 on the bit by bit basis.
  • the data train “0101 . . . 1” stored in the read register group 20 is transmitted to the output means 123 on the basis of bit by bit, through the read data buses RD, /RD.
  • the data train “1010 . . . 0” stored in the write register group 17 is transmitted to the input/output means 122 on the basis of bit by bit through the write data buses WD,/WD and is further transmitted to the output means 123 through the second read data buses RD 2 , /RD 2 and the inverters 211 , 212 as well. Since the data train “1010 . . . 0” stored in the write register group 17 passes through the inverters 211 , 212 on the way to the output means 123 , the logical level thereof is inverted passing there through and then inputted to the output means 123 as the data train “0101 . . . 1”.
  • the output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from the second read data buses RD 2 , /RD 2 and determines if they coincide with each other or not. At this time, since the logical level of the data from the second read data buses RD 2 ,/RD 2 is inverted in advance by the inverters 211 , 212 , the comparison means provided in the output means 123 can compare the data from the second read data buses RD 2 , /RD 2 with the data from the read data buses RD, /RD, leaving the data from the second read data buses RD 2 , /RD 2 as it stands. The comparison result is outputted as the output data DO 1 c from the output terminal DOUT.
  • word lines WL 1 and WL 2 are paired, two adjacent word lines of the word lines WL 3 to WLn are paired, and the data stored in the memory cells connected with each of those paired word lines are compared with each other by means of the output means 123 on the pair by pair basis.
  • a plurality of word lines are divided into a plurality of word line pairs of which each is made up of two adjacent word lines, and the data stored in the memory cells connected with one of the paired word line is transferred to the read register group 20 while the data stored in memory cells connected with the other of the paired word line is transferred to the write register group 17 .
  • the data train stored in the read register group 20 is compared with the data stored in the write register group 17 by means of the output means 123 on the bit by bit basis. Therefore, the time needed for executing the test read operation is reduced to a great extent as compared with the read operation of the prior art serial access memory 1 in which the storage data is transferred to the read register group 20 every access to each word line and then is read out.
  • the same data train is stored in the memory cells connected with each word line.
  • the data stored in the memory cells MC 11 to MCm 1 connected with the word line WL 1 coincides with the data stored in the memory cells MC 12 to MCm 2 connected with the word line WL 2 , it might be hardly possible to judge whether or not word lines WL 1 , WL 2 have been rightly selected without any error, relying only on this result in the test write operation or the test read operation.
  • the serial access memory 201 since the data train having a logical level that is inverted on every other word line, are stored and read to be compared with each other, it becomes naturally possible to judge whether or not the data is correctly stored in each memory cell, and it further becomes possible to judge whether or not the word line is selected rightly.
  • FIG. 6 is a diagrammatic view showing the structure of a serial access memory 301 according to the third embodiment of the invention.
  • This serial access memory 301 can be made up by adding a write side third transfer means group 311 to the serial access memory 201 according to the second embodiment of the invention.
  • This write side third transfer means group 311 is made up of write side third transfer means 311 - 1 to 311 -m corresponding to the bit line pairs BL 1 , /BL 1 to BLm, /BLm, respectively.
  • Each of the write side third transfer means 311 - 1 to 311 -m is made up of two transistors. The ON/OFF control of these 2 ⁇ m transistors forming the write side third transfer means 311 - 1 to 311 -m is carried out with a control signal WT 2 .
  • the serial access memory 301 further includes write side first transfer means 16 - 1 to 16 -m in addition to the write side third transfer means 311 - 1 to 311 -m.
  • the write side first transfer means 16 - 1 to 16 -m serve to connect bit line pairs BL 1 , /BL 1 to BLm, /BLm with write registers Wreg- 1 to Wreg-m respectively, and the ON/OFF control thereof is carried out with the control signal WT.
  • the control signal WT or the control signal WT 2 is put in the H-level.
  • the complementary data is stored in each of the write register Wreg- 1 to Wreg-m is stored. This complementary data is transferred to bit line pairs BL 1 , /BL 1 to BLm, /BLm by either the write side first transfer means 16 - 1 to 16 -m or the write side third transfer means 311 - 1 to 311 -m.
  • the complementary data outputted to each of bit lines BL 1 to BLm when transferred by the write side first transfer means 16 - 1 to 16 -m is outputted to each of bit lines /BL 1 to /BLm when transferred by the write side third transfer means 311 - 1 to 311 -m.
  • the complementary data outputted to each of bit lines /BL 1 to /BLm when transferred by the write side first transfer means 16 - 1 to 16 -m is outputted to each of bit lines BL 1 to BLm when transferred by the write side transfer means 311 - 1 to 311 -m.
  • serial access memory 301 As arranged above according to the third embodiment.
  • This serial access memory 301 is made up for the purpose of reducing the test time thereof. Therefore, the read operation and the write operation will be described in connection with the test by which it is judged whether or not a predetermined data as written in the serial access memory 301 can be correctly read out without any failure.
  • FIG. 7 is a timing chart for describing the test write operation of the serial access memory 301 , that is. The test write operation will be described with the passage of time as indicated in the figure.
  • ⁇ Time t 1 In starting the test write operation, a test mode signal TM is inputted to the memory control portion 112 .
  • the test write operation is commenced by serially inputting a write X-address WXAD to the memory control portion 112 .
  • a write address enable signal WADE of the H-level is inputted in advance to the memory control portion 112 in order to make it possible for the memory control portion 112 to take in the write X-address WXAD.
  • the most significant bit (MSB) data Am of the write X-address WXAD is taken in the memory control portion 112 , and thereafter, each bit data of the write X-address WXAD is taken in sequence in the memory control portion 112 in synchronism with a clock signal CLK.
  • the memory control portion 112 detects the write enable signal WE of the H-level in the rise timing of the clock signal CLK. With this, the substantial test write operation is commenced.
  • the write Y-address means 14 selects the write Y-address signal YW 1 from the write Y-address signals YW 1 to YWm and puts it in the H-level.
  • the input data DI 1 inputted from the input terminal DIN is transmitted to the write data buses WD, /WD through the input/output means 122 . Since the write side second transfer means 18 - 1 is put in the ON state with the write Y-address signal YW 1 of the H-level, the input data DI 1 is stored in the write register Wreg- 1 .
  • the write Y-address means 14 selects in sequence the write Y-address signals YW 2 to YWm from the write Y-address signals YW 1 to YWm in synchronism with the clock signal CLK and puts each of them in the H-level.
  • the input data D 12 to DIm are inputted in sequence to the input terminal DIN, and each of the input data D 12 to DIm is stored in the write registers Wreg- 2 to Wreg-m.
  • control signal WT 2 is put in the H-level when transferring the data to the memory cells MC 12 to MCm 2 , MC 14 to MCm 4 , . . . connected with even numbered word lines WL 2 , WL 4 , . . . , and so on.
  • the input data DI 1 to DIm stored in the write register group 17 are transferred all at once to the memory cells MC 1 n to MCmn connected with word lines WLn, thereby completing the transfer operation of input data DI 1 to DIm from the write register group 17 to the memory cell array 11 .
  • the input data DI 1 to DIm are stored in the memory cells MC 11 to MCm 1 , MC 13 to MCm 3 , . . . connected with odd numbered word lines WL 1 , WL 3 , . . . , and so on, while the input data /DI 1 to /DIm having the logical level that is obtained by inverting that of the input data DI 1 to DIm, are stored in the memory cells MC 12 to MCm 2 , MC 14 to MCm 4 , . . . connected with even numbered word lines WL 2 , WL 4 , . . . , and so on.
  • the serial access memory 301 executes the test read operation that is the almost same operation as has been performed by the serial access memory 201 according to the second embodiment.
  • FIG. 8 is a diagrammatic view showing the structure of a serial access memory 401 according to the fourth embodiment of the invention.
  • This serial access memory 401 can be made up by adding a test write Y-address means 411 , inverters 413 - 1 to 413 -m (m pieces), and NOR gates 415 - 1 to 415 -m (m pieces) to the serial access memory 201 according to the second embodiment.
  • Gates of two transistors making up each of the write side second transfer means 18 - 1 to 18 -m are connected with respective output terminals of the inverters 413 - 1 to 413 -m.
  • Each output terminal of the NOR gates 415 - 1 to 415 -m is connected with each input terminal of the inverters 413 - 1 to 413 -m. Furthermore, each first input terminal of the NOR gates 415 - 1 to 415 -m is connected with a transmission line for the write Y-address signals YW 1 to YWm outputted from the write Y-address means 14 .
  • the NOR gates 415 - 1 to 415 -m are divided into a plurality of groups composed of four NOR gates each. Each second input terminal of the NOR gates 415 - 1 to 415 - 4 belonging to the first NOR gate group is commonly connected with the transmission line for the test write Y-address signal TYW 1 outputted from a test write Y-address means 411 .
  • each second input terminal of the NOR gates 415 - 5 to 415 -m belonging to each NOR gate group from the second group to the kth group is commonly connected with each transmission line for the test write Y-address signals TYW 2 to TYWk outputted from the test write Y-address means 411 .
  • serial access memory 401 having the structure as mentioned above will now be described in the following.
  • the serial access memory 401 is made up for the purpose of further reducing the time needed for the test write operation of the serial access memory 201 according to the second embodiment. Accordingly, the following description will be made focusing on the test write operation of the serial access memory 401 .
  • all the write Y-address signals YW 1 to YWm outputted from the write Y-address means 14 are fixed to the L-level.
  • the test write Y-address means 411 selects in sequence the test write Y-address signals TYWI to TYWk in synchronism with the clock signal CLK and puts them in the H-level, respectively.
  • the input data DI 1 to DIk are inputted in sequence to the input terminal DIN, and each of the input data DI 1 to DIk is stored in the write registers Wreg- 1 to Wreg-m.
  • each of the same input data come to be stored in each of the write register Wreg- 1 to Wreg-m.
  • the input data DI 1 is stored in each of the write registers Wreg- 1 to Wreg- 4 while the input data DIk is stored in each of the write registers Wreg-(m- 3 ) to Wreg-m.
  • the serial access memory 401 carries out the almost same test write operation as has been performed by the serial access memory 201 according to the second embodiment. That is, the control signal WT is put in the H-level by the memory control portion 211 , and the word lines WL 1 to WLn are respectively put in the H-level in sequence by the X-address means 13 .
  • the input data DI 1 to DIk stored in the write register 17 are transferred to the memory cells MC 11 to MCm 1 , . . . , and MC 1 n to MCmn connected with word lines WL 1 to WLn through the write side first transfer means 16 - 1 to 16 -m on the word line by word line basis.
  • the length of the input data DI 1 to DIk to be inputted thereto becomes one fourth ( ⁇ fraction (1/4) ⁇ ) of that of the input data DI 1 to DIm to be inputted to the serial access memory 201 according to the second embodiment. That is, the time needed for storing the input data DI 1 to DIk in the write register Wreg- 1 to Wreg-m becomes one fourth as compared with the case of the serial access memory 201 . As the result of this, the time needed for the test write operation can be remarkably reduced.
  • the NOR gates 415 - 1 to 415 -m are divided into groups of 4 NOR gates each, but it may be possible to increase or decrease the number of NOR gates included in each group, depending on the contents of the test.
  • FIG. 9 is a diagrammatic view indicating a serial access memory 501 according to the fifth embodiment of the invention.
  • the serial access memory 501 can be made up by adding a write side fourth transfer means group 511 , write data bus separating means 513 - 1 to 513 -m, inverters 515 - 1 to 515 -m (m pieces), and NOR gates 517 - 1 to 517 -m (m pieces) to the serial access memory 201 according to the second embodiment.
  • the write side fourth transfer means group 511 is made up of the write side fourth transfer means 511 - 1 to 511 -m corresponding to each of the write register Wreg- 1 to Wreg-m.
  • Each of the write side fourth transfer means 511 - 1 to 511 -m is composed of two transistors and an inverter. For instance, one of two transistors making up the write side fourth transfer means 511 - 1 transmits the write Y-address signal YW 1 outputted from the write Y-address means 14 to the write side second transfer means 18 - 1 , through the drain/source of the above one transistor.
  • the inverter making up the write side fourth transfer means 511 - 1 inverts the logical level of a write Y-address signal YW 1 outputted from the write Y-address means 14 and generates a logical level inverted write Y-address signal /YW 1 .
  • the other of two transistors making up the write side fourth transfer means 511 - 1 transmits the inverted write Y-address signal /YWI to the write side second transfer means 18 - 1 through the drain/source of the above other transistor.
  • the ON/OFF control of 2 ⁇ m transistors making up the write side fourth transfer means 511 - 1 to 511 -m are carried out with a control signal TWA.
  • Two gates of the two transistors making up each of the write side second transfer means 18 - 1 to 18 -m is connected with each output terminal of the inverters 515 - 1 to 515 -m.
  • Each input terminal of the inverters 515 - 1 to 515 -m is connected with each output terminal of the NOR gates 517 - 1 to 517 -m.
  • Each first input terminal of the NOR gates 517 - 1 to 517 -m is commonly connected with the transmission line of the control signal TWA.
  • Each second input terminal of the NOR gates 517 - 1 to 517 -m is connected with each transmission line of the write Y-address signals YW 1 to YWm outputted from the write Y-address means 14 .
  • Each of the write data bus separating means 513 - 1 to 513 -m is respectively made up of two transfer gates and an inverter. Each first control terminal of two transfer gates commonly receives a control signal WDC while each second terminal of the same commonly receives an inverted logical level signal that is obtained by inverting the logical level of the control signal WDC.
  • the control signal WDC of the H-level is inputted to the write data bus separating means 513 - 1 to 513 -m, the write data buses WD, /WD are separated from the input/output means 122 .
  • FIG. 10 is a timing chart for describing the test write operation of the serial access memory 501 .
  • the test write operation will be described with the passage of time as shown in the figure.
  • the control signal WDC of the H-level is inputted to the write data bus separating means 513 , thereby separating write data buses WD,/WD from the input/output means 122 .
  • the write address enable signal WADE of the H-level is inputted to the memory control portion 112 in the rise timing of the clock signal CLK.
  • the memory control portion 112 instructs the write Y-address means 14 to output the write Y-address signal YW 1 of the H-level and the write Y-address signals YW 2 to YWm of the L-level as well.
  • the control signal TWA generated from the clock signal CLK becomes the H-level.
  • this control signal TWA of the H-level all the 2 ⁇ m transistors making up the write side fourth transfer means 511 - 1 to 511 -m are put in the ON state. Since each second input terminal of the NOR gates 517 - 1 to 517 -m is put in the H-level, all the 2 ⁇ m transistors making up the write side second transfer means 18 - 1 to 18 -m are also put in the ON state. Accordingly, the write Y-address signals YW 1 to YWm outputted from the write Y-address means 14 are stored, as the data, in the write registers Wreg- 1 to Wreg-m, respectively.
  • the data “ 1 ” is stored in the write register Wreg- 1 while the data “ 0 ” is stored in the write register Wreg- 2 to Wreg-m.
  • the writ Y-address means 14 outputs the write Y-address signal YW 2 of the H-level and the write Y-address signals YW 1 and YW 3 to YWm of the L-level as well. Since the control signal TWA is the H-level, the data “ 1 ” is stored in the write register Wreg- 2 while the data “ 0 ” is stored in all the write registers Wreg- 1 and Wreg- 2 to Wreg-m as well.
  • the data stored in the write register group 17 is transferred all at once to the memory cells MC 1 n to MCmn connected with word lines WLn, and a series of the test write operation is completed.
  • the data “ 1 ” is stored in only one memory cell among the m memory cells connected with each of the n word lines while the data “ 0 ” is stored in all the other memory cells.
  • the data “ 1 ” is aligned along the diagonal line of the matrix.
  • the data “ 1 ” is stored in the memory cell array 11 such that the data “ 1 ” is aligned along the diagonal line of the memory cell array i.e. the memory cell matrix.
  • the data “ 0 ” it is possible for the data “ 0 ” to be aligned along the diagonal line of the memory cell matrix.
  • the serial access memory 501 since the write Y-address signals YW 1 to YWm outputted from the write Y-address means 14 are stored as the data in each of the write register Wreg- 1 to Wreg-m, there is no need for any input data to be externally inputted during the test write operation, thus the test time being further reduced as compared with the test time of the serial access memories 101 to 401 as have been described so far according to the first to fourth embodiments of the invention.
  • test time of the serial access memory can be reduced to a great extent, and the measurement of the data transfer margin can be more easily carried out.

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US7782682B2 (en) * 2001-03-09 2010-08-24 Fujitsu Semiconductor Limited Semiconductor device with circuitry for efficient information exchange

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US6728155B2 (en) 2004-04-27
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