US20010017423A1 - Semiconductor device having sidewall spacers manifesting a self-aligned contact hole - Google Patents
Semiconductor device having sidewall spacers manifesting a self-aligned contact hole Download PDFInfo
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- US20010017423A1 US20010017423A1 US09/813,834 US81383401A US2001017423A1 US 20010017423 A1 US20010017423 A1 US 20010017423A1 US 81383401 A US81383401 A US 81383401A US 2001017423 A1 US2001017423 A1 US 2001017423A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 125000006850 spacer group Chemical group 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000012212 insulator Substances 0.000 claims abstract description 16
- 239000004020 conductor Substances 0.000 claims description 47
- 239000012535 impurity Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 abstract description 28
- 238000004519 manufacturing process Methods 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 77
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 238000007796 conventional method Methods 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
Definitions
- the present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a self-aligned contact hole and a method for manufacturing the same.
- a general process of forming a self-aligned contact hole which can be easily and precisely made, does not require fitting a mask using a location-fitting margin. Accordingly, high integration can be achieved without utilizing a highly skilled process or highly precise equipment to perform the process.
- FIGS. 1 a to 1 c are cross-sectional views showing a method for manufacturing a semiconductor device according to one conventional method and FIGS. 2 a to 2 c are cross-sectional views showing a method for manufacturing a semiconductor device according to another conventional method.
- FIG. 3 is a cross-sectional view showing a structure of a semiconductor device manufactured according to a conventional method, which illustrates problems arising from manufacturing the semiconductor device according to a conventional method.
- an active region and a field region are defined on a substrate 1 and then a field oxide layer is formed on the field region.
- an oxide layer, a polysilicon layer, and a nitride layer are successively formed on the entire surface of the substrate 1 .
- a photoresist layer is coated on the resultant surface and then selectively patterned. With the patterned photoresist layer serving as a mask, the nitride layer, the polysilicon layer, and the oxide layer are successively etched to form a first and second gate structure 3 a and 3 b , respectively.
- the first and second gate structures 3 a and 3 b comprise a gate oxide layer 2 , a gate electrode 3 , and a gate cap insulating layer 4 . Thereafter, the remaining patterned photoresist layer is removed.
- first and second gate structures 3 a and 3 b serving as a mask, lightly doped impurity ions are implanted into the exposed surface of the substrate 1 thereby forming lightly doped source and drain regions 5 .
- a nitride layer is deposited over the substrate 1 and anisotropically etched to form sidewall spacers 6 on the sides of the first and second gate structures 3 a and 3 b , respectively.
- heavily doped impurity ions are implanted into the exposed surface of the substrate 1 thereby forming a heavily doped source/drain region 7 .
- FIG. 1 b there is formed an interlayer insulating layer 8 over the substrate 1 . Then a photoresist layer is formed on the interlayer insulating layer 8 and exposed and developed to form the patterned photoresist layer 9 .
- the interlayer insulating layer 8 is anisotropically etched using a high selective etch rate of the oxide and nitride layers until the surface of the substrate 1 is exposed, thus forming a contact hole.
- the high selective etch rate is described as the nitride or oxide layer being easily etched and the polysilicon layer not being easily etched or vice-versa.
- a conductive material such as polysilicon, aluminum, or tungsten that are patterned to form a bit line 10 .
- FIGS. 2 a - 2 c Another conventional method for manufacturing a semiconductor device will be explained with reference to FIGS. 2 a - 2 c.
- FIG. 2 a there are defined an active region and a field region in the substrate 11 .
- a field oxide layer is formed on the field region.
- a first oxide layer, a polysilicon layer, and a second oxide layer are successively formed on the entire surface of the substrate 11 .
- a photoresist layer is coated on the resultant surface and then exposed and developed to form a patterned photoresist layer. With the patterned photoresist layer serving as a mask, the first oxide layer, the polysilicon layer, and the second oxide layer are successively etched to form a first and second gate structure 13 a and 13 b , respectively.
- the first and second gate structures 3 a and 3 b comprise a gate oxide layer 12 , a gate electrode 13 , and a gate cap insulating layer 14 on a predetermined portion of the substrate 11 . Thereafter, the remaining patterned photoresist layer is removed.
- first and second gate structures 13 a and 13 b serving as a mask, lightly doped impurity ions are implanted into the exposed surface of the substrate 11 thereby forming lightly doped source and drain regions 15 .
- an oxide layer is formed on the resultant surface and then anisotropically etched to form sidewall spacers 16 on sides of the first and second gate structures 13 a and 13 b.
- heavily doped impurity ions are implanted into the substrate 11 thereby forming a heavily doped source/drain region 17 .
- an interlayer insulating layer 18 using a chemical vapor deposition (CVD) method.
- a photoresist layer is coated on the resultant surface and then exposed and developed to form a patterned photoresist layer 19 .
- the interlayer insulating layer 18 is anisotropically etched in between the first and second gate structures 13 a and 13 b to expose the surface of the source/drain region 17 thereby forming a contact hole. Then, an oxide layer is formed on the resultant surface and then anisotropically etched to form oxide sidewall spacers 20 on sides of the interlayer insulating layer 8 . Subsequently, a conductive material such as polysilicon, aluminum, or tungsten is formed on the entire surface and then patterned to form a bit line 21 . In this case, the oxide sidewall spacers 20 serve to insulate the gate electrode 13 from the bit line 21 .
- the present invention is directed to a semiconductor device and a method for manufacturing the same that substantially obviate one or more of problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a semiconductor device having a self-aligned contact hole and a method for manufacturing the same.
- Another object of the present invention is to provide a semiconductor device having unsymmetrical source and drain regions and a method for manufacturing the same.
- a semiconductor device having a self-aligned contact hole, the device comprising: a substrate; a first conductor structure and a second conductor structure formed on the substrate; an insulator structure formed on the first and second conductor structure and on the substrate except over the substrate in a region between the first and second conductor structures; and sidewall spacers formed on a side of the first and second conductor structures and on a side of the insulator structure, the sidewall spacers defining the self-aligned contact hole in the region between the first and second conductor structures.
- a method for self-aligning a contact hole between two conductor structures in a semiconductor device comprising the steps of: providing a substrate; forming a first conductor structure on the substrate; forming an insulator structure on the first conductor structure and substrate; and selectively removing a portion of the insulator structure and a portion of the first conductor structure to split the first conductor structure into a second conductor structure and a third conductor structure and to concurrently expose the substrate thereby producing a self-aligned contact hole between the second and third conductor structures.
- an unsymmetrical semiconductor device using a self-aligned contact hole comprising: a substrate having impurity regions formed therein; a first conductor structure and a second conductor structure formed on the substrate; an insulator structure formed on the first and second conductor structures and on the substrate except over the substrate in a region between the first and second conductor structures; first sidewall spacers formed on a side of the first and second conductor structures and on a side of the insulator structure, the first sidewall spacers defining the self-aligned contact hole in the region between the first and second conductor structures; and second sidewall spacers formed on sides of the first and second conductor structures opposite of the self-aligned contact hole.
- a method for forming an unsymmetrical semiconductor device using a precisely aligned contact hole comprising the steps of: providing a substrate; forming a first conductor structure on the substrate; forming a first impurity region in the semiconductor substrate at sides of the first conductor structure; forming an insulator structure on the first conductor structure and substrate; selectively removing a portion of the insulator structure and a portion of the first conductor structure to split the first conductor structure into a second and third conductor structure and to concurrently expose the substrate thereby producing a self-aligned contact hole between the second and third conductor structures; and forming a second impurity region in the self-aligned contact hole.
- FIGS. 1 a to 1 c are cross-sectional views showing a conventional method for manufacturing a semiconductor device
- FIGS. 2 a to 2 c are cross-sectional views showing another conventional method for manufacturing a semiconductor device
- FIG. 3 is a cross-sectional view of a semiconductor device manufactured according to a conventional method.
- FIG. 4 is a plan view of a semiconductor device according to the present invention.
- FIG. 5 is a cross-sectional view across the line V-V in FIG. 4 according to the present invention.
- FIGS. 6 a to 6 d are cross-sectional views showing a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention.
- FIGS. 4, 5, and 6 a - 6 b Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in FIGS. 4, 5, and 6 a - 6 b.
- FIG. 4 the plan view of the semiconductor device according to the present invention illustrates a first source/drain region 35 and a second source/drain region 39 .
- a gate line which had a width of X, is divided into a first gate line 43 a and a second gate line 43 b having a width of X′ and X′′, respectively.
- the area 42 having an “X” drawn therethrough represents a contact plug area wherein a contact plug is in contact with a second source/drain region 39 .
- the contact plug is also in contact with the bit line 41 .
- the cross-sectional view of the semiconductor device taken along the line V-V of FIG. 4 illustrates a field region and an active region defined on a substrate 30 and a field oxide layer 31 formed on the field region.
- a gate line 43 (see FIG. 6 a ) having a width of X is formed over the active region of the substrate 30 .
- the gate line 43 preferably, comprises a gate oxide layer 32 formed on the substrate 30 , a conductive line 33 , which is also a gate electrode, formed on the gate oxide layer 32 , and a gate cap insulator layer formed on the conductive line 33 .
- the gate line 43 is divided into two gate lines which are the first and second gate lines 33 a and 33 b having widths of X′ and X′′, respectively, as shown in FIG. 5.
- the first gate line 43 a comprises a gate oxide layer 32 formed on the substrate 30 , a conductive line 33 a formed on the gate oxide layer 32 , and a gate cap insulator layer 34 formed on the conductive line 33 a.
- the second gate line 43 b has the same structure of the first gate line 43 a having a conductive line 33 b instead of a conductive line 33 a.
- a contact hole is formed between the first and second gate lines 43 a and 43 b and an interlayer insulating layer 37 is formed on the first and second gate lines 43 a and 43 b and on the substrate 30 .
- Source and drain regions 35 are formed in the substrate 30 at outer sides of the first and second gate lines 43 a and 43 b.
- a second source/drain region 39 is formed in the substrate 30 between the first and second gate lines 43 a and 43 b. While gate insulating sidewalls 36 are formed on the outer sides of the gate lines 43 a and 43 b , oxide sidewall spacers 40 are formed on the inner sides of the gate lines 43 a and 43 b and the interlayer insulating layer 37 .
- a contact plug 41 a is formed in contact with the second source/drain region 39 . Structures on the field oxide layer 31 serve as “dummy” structures which do not serve any functional purpose.
- the semiconductor devices according to the invention can have transistors in field regions as well as active regions, and are described in terms of structures in the field regions that correspond to the structures in the active regions.
- structures corresponding to the gate electrodes 33 a and 33 b , the gate cap insulators 34 , the sidewall spacers 36 and 40 and the plug 41 a are formed on the field oxide layers 31 . But because they are formed on the field oxide layers 31 , they represent inoperative transistors. Forming these inoperative transistors in the field regions is not necessary to practice the invention. But it has been determined that forming the structures in the field regions as well as in the active regions has advantages, from an ease-of-manufacturing point of view. Thus, it is preferable but not necessary to form the inoperative transistors in the field regions at the same time that the corresponding transistors are formed in the active regions.
- FIGS. 6 a - 6 d A method for manufacturing a semiconductor device having the aforementioned structure of FIG. 5 according to the present invention will be explained with reference to FIGS. 6 a - 6 d.
- a field region and an active region are defined in a substrate 30 and then a field oxide layer is formed on the field region.
- a first thin oxide layer is formed on the entire surface of the substrate 30 using a thermal oxidation process, and then a polysilicon layer and a second oxide layer are successively formed on the first thin oxide layer.
- a nitride layer can be deposited in place of the second oxide layer.
- the first oxide layer, the polysilicon layer, and the second oxide layer are anisotropically etched to form a gate line 43 that comprises a gate oxide layer 32 , a conductive line 33 , and a gate cap insulating layer 34 , which has a width of X.
- lightly doped impurity ions of either an N type or P types are implanted into the substrate 30 thereby forming first source and drain regions 35 .
- either of an oxide layer or a nitride layer is formed and then anisotropically etched to form gate insulating sidewalls 36 on the sides of the gate line 43 .
- an interlayer insulating layer 37 of an oxide is formed on the entire surface of the substrate 30 using a chemical vapor deposition (CVD) method, and then a photoresist layer is coated on the entire surface and patterned using a contact hole mask to form a patterned photoresist layer 38 .
- CVD chemical vapor deposition
- the interlayer insulating layer 37 and the gate line 33 are etched such that the gate line 33 is divided into two gate lines.
- the two gate lines form a first gate line 43 a having a width of X′ and a second gate line 43 b having a width of X′′ (See FIG. 4).
- the remaining patterned photoresist layer 38 is removed. Impurity ions are implanted into the exposed surface of the substrate 30 between the first and second gate lines 43 a and 43 b , thus forming a second source/drain region 39 .
- the second source/drain region 39 has the same impurity ions as the first source/drain regions 35 .
- the concentration of the first and second source/drain regions 35 and 39 are different.
- the ions of a different concentration are implanted and a thermal diffusion is carried out, forming an unsymmetrical device, (i.e., source and drain regions having different ion concentrations).
- oxide sidewall spacers 40 are then subsequently formed and anisotropically etched to form oxide sidewall spacers 40 on inner sides of the first and second gate lines 43 a and 43 b and on a side surface of the interlayer insulating layer 37 .
- a conductive material is formed on the entire surface and then patterned to form a contact plug 41 a and a bit line 41 whereby the bit line 41 connects with the contact plug 41 a .
- the conductive material for the bit line plug 41 a and the bit line 41 are preferably a polysilicon, aluminum, or tungsten type material.
- a method for manufacturing a semiconductor device of the present invention has the following advantages.
- oxide sidewall spacers 40 are formed (after dividing a gate line into two gate lines) on an inner side surface between the two gate lines, a contact plug, which is in contact with a bit line, is not formed over the gate lines avoiding a short between the gate lines and a bit line. As a result, a device having of good reliability can be manufactured.
- a mask to divide the gate line can be replaced with a conventional mask to define a contact hole.
- the manufacturing process becomes simplified, e.g., because the mask inventory can be reduced by one mask.
- a contact hole is concurrently formed along with the two gate lines, which permits a single masking step to replace the separate masking steps needed to form the two gate lines and for the contact hole.
- first source drain regions at both sides of the gate lines and a second source/drain in between the divided gate lines are formed, respectively, by ion implantation of different concentrations, thereby forming an unsymmetrical device.
- a more precise contact hole is formed by dividing a single gate line into two gate lines that avoid aligning a contact hole between the two gate lines.
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Abstract
A semiconductor device and a method for manufacturing the same that forms a self-aligned contact hole between two gate lines. A substrate is provided that has a first gate line formed thereon. An insulator is formed on the first gate line and substrate. Then a portion of the insulator and a portion of the first gate line is selectively removed to split the first gate line into a second gate line and a third gate line and to concurrently expose the substrate. Thus, producing a self-aligned contact hole between the second and third gate lines.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a self-aligned contact hole and a method for manufacturing the same.
- 2. Discussion of the Related Art
- A general process of forming a self-aligned contact hole, which can be easily and precisely made, does not require fitting a mask using a location-fitting margin. Accordingly, high integration can be achieved without utilizing a highly skilled process or highly precise equipment to perform the process.
- There are two conventional methods for forming a self-aligned contact hole. In one method, selective etch rates are used. In another method, which is a semi self-alignment method, a contact hole is formed and then an oxide sidewall is formed.
- A conventional method for manufacturing a semiconductor device will be explained with reference to the accompanying drawings.
- FIGS. 1a to 1 c are cross-sectional views showing a method for manufacturing a semiconductor device according to one conventional method and FIGS. 2a to 2 c are cross-sectional views showing a method for manufacturing a semiconductor device according to another conventional method. FIG. 3 is a cross-sectional view showing a structure of a semiconductor device manufactured according to a conventional method, which illustrates problems arising from manufacturing the semiconductor device according to a conventional method.
- Referring initially to FIG. 1a, an active region and a field region are defined on a
substrate 1 and then a field oxide layer is formed on the field region. Next, an oxide layer, a polysilicon layer, and a nitride layer are successively formed on the entire surface of thesubstrate 1. Subsequently, a photoresist layer is coated on the resultant surface and then selectively patterned. With the patterned photoresist layer serving as a mask, the nitride layer, the polysilicon layer, and the oxide layer are successively etched to form a first andsecond gate structure 3 a and 3 b, respectively. The first andsecond gate structures 3 a and 3 b comprise agate oxide layer 2, agate electrode 3, and a gatecap insulating layer 4. Thereafter, the remaining patterned photoresist layer is removed. - With the first and
second gate structures 3 a and 3 b serving as a mask, lightly doped impurity ions are implanted into the exposed surface of thesubstrate 1 thereby forming lightly doped source anddrain regions 5. Next, a nitride layer is deposited over thesubstrate 1 and anisotropically etched to formsidewall spacers 6 on the sides of the first andsecond gate structures 3 a and 3 b, respectively. With the first andsecond gate structures 3 a and 3 b and thesidewall spacers 6 serving as a mask, heavily doped impurity ions are implanted into the exposed surface of thesubstrate 1 thereby forming a heavily doped source/drain region 7. - Referring to FIG. 1b, there is formed an
interlayer insulating layer 8 over thesubstrate 1. Then a photoresist layer is formed on theinterlayer insulating layer 8 and exposed and developed to form the patternedphotoresist layer 9. - Referring to FIG. 1c, with the patterned
photoresist layer 9 serving as a mask, theinterlayer insulating layer 8 is anisotropically etched using a high selective etch rate of the oxide and nitride layers until the surface of thesubstrate 1 is exposed, thus forming a contact hole. The high selective etch rate is described as the nitride or oxide layer being easily etched and the polysilicon layer not being easily etched or vice-versa. Next, on the entire surface of thesubstrate 1, there is formed a conductive material such as polysilicon, aluminum, or tungsten that are patterned to form abit line 10. - Another conventional method for manufacturing a semiconductor device will be explained with reference to FIGS. 2a-2 c.
- Referring initially to FIG. 2a, there are defined an active region and a field region in the
substrate 11. A field oxide layer is formed on the field region. Then, a first oxide layer, a polysilicon layer, and a second oxide layer are successively formed on the entire surface of thesubstrate 11. Subsequently, a photoresist layer is coated on the resultant surface and then exposed and developed to form a patterned photoresist layer. With the patterned photoresist layer serving as a mask, the first oxide layer, the polysilicon layer, and the second oxide layer are successively etched to form a first andsecond gate structure 13 a and 13 b, respectively. The first andsecond gate structures 3 a and 3 b comprise agate oxide layer 12, agate electrode 13, and a gatecap insulating layer 14 on a predetermined portion of thesubstrate 11. Thereafter, the remaining patterned photoresist layer is removed. - With the first and
second gate structures 13 a and 13 b serving as a mask, lightly doped impurity ions are implanted into the exposed surface of thesubstrate 11 thereby forming lightly doped source anddrain regions 15. Next, an oxide layer is formed on the resultant surface and then anisotropically etched to formsidewall spacers 16 on sides of the first andsecond gate structures 13 a and 13 b. With thesidewall spacers 16 and first andsecond gate structures 13 a and 13 b serving as a mask, heavily doped impurity ions are implanted into thesubstrate 11 thereby forming a heavily doped source/drain region 17. - Referring to FIG. 2b, on the resultant surface, there is deposited an
interlayer insulating layer 18 using a chemical vapor deposition (CVD) method. Next, a photoresist layer is coated on the resultant surface and then exposed and developed to form a patternedphotoresist layer 19. - Referring to FIG. 2c, with the patterned
photoresist layer 19 serving as a mask, theinterlayer insulating layer 18 is anisotropically etched in between the first andsecond gate structures 13 a and 13 b to expose the surface of the source/drain region 17 thereby forming a contact hole. Then, an oxide layer is formed on the resultant surface and then anisotropically etched to formoxide sidewall spacers 20 on sides of theinterlayer insulating layer 8. Subsequently, a conductive material such as polysilicon, aluminum, or tungsten is formed on the entire surface and then patterned to form abit line 21. In this case, theoxide sidewall spacers 20 serve to insulate thegate electrode 13 from thebit line 21. - Problems arising from semiconductor devices manufactured according to the conventional methods will be explained with reference to FIG. 3.
- As shown in FIG. 3, when an alignment tolerance is beyond the limit of a photolithography process, formation of a contact hole is misaligned on a
gate electrode 13. Consequently, a short between thegate electrode 13 and thebit line 21 is generated even after theoxide sidewall spacers 20 are formed. - Conventional methods for manufacturing a semiconductor device have the following problems.
- First, it is difficult to carry out an etch process over materials such as a nitride and an oxide having a high selective etch rate. If a selective etch rate is high, a polymer may be generated that blocks a contact hole and stops the etch process. Moreover, it is difficult to simplify the overall process.
- Second, for a high density device, alignment tolerance easily goes beyond the limit of a photolithography process that causes misalignment when forming a contact hole. Because of misalignment, a short between a gate electrode and a bit line is generated that destroys the operability of a unit device.
- Therefore, the present invention is directed to a semiconductor device and a method for manufacturing the same that substantially obviate one or more of problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a semiconductor device having a self-aligned contact hole and a method for manufacturing the same.
- Another object of the present invention is to provide a semiconductor device having unsymmetrical source and drain regions and a method for manufacturing the same.
- To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a semiconductor device having a self-aligned contact hole, the device comprising: a substrate; a first conductor structure and a second conductor structure formed on the substrate; an insulator structure formed on the first and second conductor structure and on the substrate except over the substrate in a region between the first and second conductor structures; and sidewall spacers formed on a side of the first and second conductor structures and on a side of the insulator structure, the sidewall spacers defining the self-aligned contact hole in the region between the first and second conductor structures.
- In another aspect of the invention, there is provided a method for self-aligning a contact hole between two conductor structures in a semiconductor device, the method comprising the steps of: providing a substrate; forming a first conductor structure on the substrate; forming an insulator structure on the first conductor structure and substrate; and selectively removing a portion of the insulator structure and a portion of the first conductor structure to split the first conductor structure into a second conductor structure and a third conductor structure and to concurrently expose the substrate thereby producing a self-aligned contact hole between the second and third conductor structures.
- In another aspect of the present invention, there is provided an unsymmetrical semiconductor device using a self-aligned contact hole, the device comprising: a substrate having impurity regions formed therein; a first conductor structure and a second conductor structure formed on the substrate; an insulator structure formed on the first and second conductor structures and on the substrate except over the substrate in a region between the first and second conductor structures; first sidewall spacers formed on a side of the first and second conductor structures and on a side of the insulator structure, the first sidewall spacers defining the self-aligned contact hole in the region between the first and second conductor structures; and second sidewall spacers formed on sides of the first and second conductor structures opposite of the self-aligned contact hole.
- In still another aspect of the present invention, there is provided a method for forming an unsymmetrical semiconductor device using a precisely aligned contact hole, the method comprising the steps of: providing a substrate; forming a first conductor structure on the substrate; forming a first impurity region in the semiconductor substrate at sides of the first conductor structure; forming an insulator structure on the first conductor structure and substrate; selectively removing a portion of the insulator structure and a portion of the first conductor structure to split the first conductor structure into a second and third conductor structure and to concurrently expose the substrate thereby producing a self-aligned contact hole between the second and third conductor structures; and forming a second impurity region in the self-aligned contact hole.
- The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
- The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein
- FIGS. 1a to 1 c are cross-sectional views showing a conventional method for manufacturing a semiconductor device;
- FIGS. 2a to 2 c are cross-sectional views showing another conventional method for manufacturing a semiconductor device;
- FIG. 3 is a cross-sectional view of a semiconductor device manufactured according to a conventional method.
- FIG. 4 is a plan view of a semiconductor device according to the present invention;
- FIG. 5 is a cross-sectional view across the line V-V in FIG. 4 according to the present invention; and
- FIGS. 6a to 6 d are cross-sectional views showing a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention.
- Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in FIGS. 4, 5, and6 a-6 b.
- Referring to FIGS. 4 and 5, the structure of the semiconductor device according to the present invention will first be described. In FIG. 4, the plan view of the semiconductor device according to the present invention illustrates a first source/
drain region 35 and a second source/drain region 39. A gate line, which had a width of X, is divided into afirst gate line 43 a and asecond gate line 43 b having a width of X′ and X″, respectively. Thearea 42 having an “X” drawn therethrough represents a contact plug area wherein a contact plug is in contact with a second source/drain region 39. The contact plug is also in contact with thebit line 41. - In FIG. 5, the cross-sectional view of the semiconductor device taken along the line V-V of FIG. 4 illustrates a field region and an active region defined on a
substrate 30 and afield oxide layer 31 formed on the field region. A gate line 43 (see FIG. 6a) having a width of X is formed over the active region of thesubstrate 30. Thegate line 43, preferably, comprises agate oxide layer 32 formed on thesubstrate 30, aconductive line 33, which is also a gate electrode, formed on thegate oxide layer 32, and a gate cap insulator layer formed on theconductive line 33. Thegate line 43 is divided into two gate lines which are the first andsecond gate lines first gate line 43 a comprises agate oxide layer 32 formed on thesubstrate 30, aconductive line 33 a formed on thegate oxide layer 32, and a gatecap insulator layer 34 formed on theconductive line 33 a. Thesecond gate line 43 b has the same structure of thefirst gate line 43 a having aconductive line 33 b instead of aconductive line 33 a. - A contact hole is formed between the first and
second gate lines layer 37 is formed on the first andsecond gate lines substrate 30. - Source and
drain regions 35 are formed in thesubstrate 30 at outer sides of the first andsecond gate lines drain region 39 is formed in thesubstrate 30 between the first andsecond gate lines gate insulating sidewalls 36 are formed on the outer sides of the gate lines 43 a and 43 b,oxide sidewall spacers 40 are formed on the inner sides of the gate lines 43 a and 43 b and the interlayer insulatinglayer 37. A contact plug 41 a is formed in contact with the second source/drain region 39. Structures on thefield oxide layer 31 serve as “dummy” structures which do not serve any functional purpose. The semiconductor devices according to the invention can have transistors in field regions as well as active regions, and are described in terms of structures in the field regions that correspond to the structures in the active regions. In particular, on the field oxide layers 31, structures corresponding to thegate electrodes gate cap insulators 34, thesidewall spacers plug 41 a are formed. But because they are formed on the field oxide layers 31, they represent inoperative transistors. Forming these inoperative transistors in the field regions is not necessary to practice the invention. But it has been determined that forming the structures in the field regions as well as in the active regions has advantages, from an ease-of-manufacturing point of view. Thus, it is preferable but not necessary to form the inoperative transistors in the field regions at the same time that the corresponding transistors are formed in the active regions. - A method for manufacturing a semiconductor device having the aforementioned structure of FIG. 5 according to the present invention will be explained with reference to FIGS. 6a-6 d.
- Referring initially to FIG. 6a, a field region and an active region are defined in a
substrate 30 and then a field oxide layer is formed on the field region. Next, a first thin oxide layer is formed on the entire surface of thesubstrate 30 using a thermal oxidation process, and then a polysilicon layer and a second oxide layer are successively formed on the first thin oxide layer. In this case, a nitride layer can be deposited in place of the second oxide layer. - Subsequently, the first oxide layer, the polysilicon layer, and the second oxide layer are anisotropically etched to form a
gate line 43 that comprises agate oxide layer 32, aconductive line 33, and a gatecap insulating layer 34, which has a width of X. - Referring to FIG. 6b, with the
gate line 43 serving as a mask, lightly doped impurity ions of either an N type or P types are implanted into thesubstrate 30 thereby forming first source and drainregions 35. Next, either of an oxide layer or a nitride layer is formed and then anisotropically etched to formgate insulating sidewalls 36 on the sides of thegate line 43. - Referring to FIG. 6c, an
interlayer insulating layer 37 of an oxide is formed on the entire surface of thesubstrate 30 using a chemical vapor deposition (CVD) method, and then a photoresist layer is coated on the entire surface and patterned using a contact hole mask to form a patternedphotoresist layer 38. - Subsequently, with the patterned
photoresist layer 38 serving as a mask, theinterlayer insulating layer 37 and thegate line 33 are etched such that thegate line 33 is divided into two gate lines. The two gate lines form afirst gate line 43 a having a width of X′ and asecond gate line 43 b having a width of X″ (See FIG. 4). - Referring to FIG. 6d, the remaining patterned
photoresist layer 38 is removed. Impurity ions are implanted into the exposed surface of thesubstrate 30 between the first andsecond gate lines drain region 39. In this case, the second source/drain region 39 has the same impurity ions as the first source/drain regions 35. However, the concentration of the first and second source/drain regions - An oxide layer is then subsequently formed and anisotropically etched to form
oxide sidewall spacers 40 on inner sides of the first andsecond gate lines layer 37. Subsequently, a conductive material is formed on the entire surface and then patterned to form acontact plug 41 a and abit line 41 whereby thebit line 41 connects with the contact plug 41 a. Thus, the above process completes the semiconductor device of the present invention. Also, the conductive material for the bit line plug 41 a and thebit line 41 are preferably a polysilicon, aluminum, or tungsten type material. - A method for manufacturing a semiconductor device of the present invention has the following advantages.
- First, since
oxide sidewall spacers 40 are formed (after dividing a gate line into two gate lines) on an inner side surface between the two gate lines, a contact plug, which is in contact with a bit line, is not formed over the gate lines avoiding a short between the gate lines and a bit line. As a result, a device having of good reliability can be manufactured. - Second, a mask to divide the gate line can be replaced with a conventional mask to define a contact hole. Thus, the manufacturing process becomes simplified, e.g., because the mask inventory can be reduced by one mask.
- Third, by splitting a single gate line structure in the present invention, a contact hole is concurrently formed along with the two gate lines, which permits a single masking step to replace the separate masking steps needed to form the two gate lines and for the contact hole.
- Fourth, first source drain regions at both sides of the gate lines and a second source/drain in between the divided gate lines are formed, respectively, by ion implantation of different concentrations, thereby forming an unsymmetrical device.
- Fifth, a more precise contact hole is formed by dividing a single gate line into two gate lines that avoid aligning a contact hole between the two gate lines.
- The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
Claims (9)
1. A semiconductor device having a self-aligned contact hole, the device comprising:
a substrate;
a first conductor structure and a second conductor structure formed on the substrate;
an insulator structure formed on the first and second conductor structure and on the substrate except over the substrate in a region between the first and second conductor structures; and
sidewall spacers, each sidewall spacer being formed to abut against both a side of the first or second conductor structures and a side of the insulator structure, the sidewall spacers manifesting the self-aligned contact hole in the region between the first and second conductor structures.
2. The semiconductor device of , wherein the first and second conductor structures are first and second gate structures, respectively.
claim 1
3. The semiconductor device of , wherein the first and second conductor structures comprise:
claim 1
a gate oxide layer formed on the substrate;
a conductive layer formed on the gate oxide layer; and
a gate cap insulating layer formed on the conductive layer.
4. The semiconductor device of , further comprising:
claim 1
a contact plug formed in the self-aligned contact hole.
5. An unsymmetrical semiconductor device using a self-aligned contact hole, the device comprising:
a substrate having impurity regions formed therein;
a first conductor structure and a second conductor structure formed on the substrate except over the substrate in a region between the first and second conductor structures;
first sidewall spacers, each first sidewall spacer being formed to abut against both a side of the first or second conductor structures and a side of an insulator structure, the first sidewall spacers manifesting the self-aligned contact hole in the region between the first and second conductor structures; and
second sidewall spacers formed on sides of the first and second conductor structures opposite of the self-aligned contact hole.
6. The unsymmetrical semiconductor device of , wherein the ion concentration of a first impurity region is different than the ion concentration of a second impurity region.
claim 5
7. The unsymmetrical semiconductor device of , further comprising:
claim 5
a contact plug formed in the self-aligned contact hole, the contact plug being in contact with the first sidewall spacers and the first impurity region.
8. The unsymmetrical semiconductor device of , wherein the contact plug is also in contact with a bit line.
claim 7
9. The unsymmetrical semiconductor device of , wherein the contact plug is not disposed directly above the first and second conductor structures.
claim 7
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/813,834 US20010017423A1 (en) | 1996-12-27 | 2001-03-22 | Semiconductor device having sidewall spacers manifesting a self-aligned contact hole |
Applications Claiming Priority (5)
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---|---|---|---|
KR1019960073475A KR100223832B1 (en) | 1996-12-27 | 1996-12-27 | Method of manufacturing semiconductor device |
KR73475/1996 | 1996-12-27 | ||
US08/931,238 US6060346A (en) | 1996-12-27 | 1997-09-16 | Semiconductor device and method for manufacturing the same |
US45965699A | 1999-12-13 | 1999-12-13 | |
US09/813,834 US20010017423A1 (en) | 1996-12-27 | 2001-03-22 | Semiconductor device having sidewall spacers manifesting a self-aligned contact hole |
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US45965699A Continuation | 1996-12-27 | 1999-12-13 |
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US20010017423A1 true US20010017423A1 (en) | 2001-08-30 |
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US08/931,238 Expired - Lifetime US6060346A (en) | 1996-12-27 | 1997-09-16 | Semiconductor device and method for manufacturing the same |
US09/813,834 Abandoned US20010017423A1 (en) | 1996-12-27 | 2001-03-22 | Semiconductor device having sidewall spacers manifesting a self-aligned contact hole |
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US08/931,238 Expired - Lifetime US6060346A (en) | 1996-12-27 | 1997-09-16 | Semiconductor device and method for manufacturing the same |
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US (2) | US6060346A (en) |
JP (1) | JP3083495B2 (en) |
KR (1) | KR100223832B1 (en) |
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EP1935012A2 (en) * | 2005-09-14 | 2008-06-25 | Texas Instruments Incorporated | Transistor formed with self-aligned contacts |
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Also Published As
Publication number | Publication date |
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JP3083495B2 (en) | 2000-09-04 |
JPH10199979A (en) | 1998-07-31 |
KR100223832B1 (en) | 1999-10-15 |
US6060346A (en) | 2000-05-09 |
KR19980054327A (en) | 1998-09-25 |
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