US11869425B2 - Display device - Google Patents

Display device Download PDF

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Publication number
US11869425B2
US11869425B2 US17/434,271 US201917434271A US11869425B2 US 11869425 B2 US11869425 B2 US 11869425B2 US 201917434271 A US201917434271 A US 201917434271A US 11869425 B2 US11869425 B2 US 11869425B2
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Prior art keywords
electrode
light emitting
sub
transistor
pixel
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US20220139319A1 (en
Inventor
Won Sik Oh
Hyun Min Cho
Sin Chul KANG
Dae Hyun Kim
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, DAE HYUN, OH, WON SIK, CHO, HYUN MIN, KANG, SIN CHUL
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • Various embodiments of the disclosure relate to a display device.
  • Each pixel which forms a display device may include a driving transistor and subminiature light emitting elements electrically connected to the driving transistor.
  • driving current provided from the driving transistor is evenly distributed to the light emitting elements so that the light emitting elements uniformly emit light
  • the driving current may be focused on a specific light emitting element (e.g., a light emitting element having a lowest forward voltage drop (Vf)) because of a characteristic deviation (e.g., a Vf deviation attributable to a light emitting element) of the light emitting elements, whereby only the specific light emitting element may emit light.
  • Vf forward voltage drop
  • An object of the disclosure is to provide a display device in which light emitting elements in each pixel may uniformly emit light.
  • a display device in accordance with an embodiment of the disclosure may include a first power line; a second power line; a data line that transmits a data signal; a scan line that transmits a scan signal; and a plurality of pixels electrically connected to the first power line, the second power line, the data line, and the scan line.
  • Each of the plurality of pixels may include light emitting elements electrically connected between the first power line and the second power line; and a first transistor that provides driving current to the light emitting elements in response to the data signal.
  • each of the light emitting elements may include a rod-shaped light emitting diode having a size in a range of a nanometer scale to a micrometer scale.
  • the plurality of pixels may be disposed in a pixel area defined by the data line, an adjacent data line adjacent to the data line, the scan line, and an adjacent scan line adjacent to the scan line.
  • each of the plurality of pixels may include a second transistor electrically connected between the data line and the first transistor, and transmit the data signal to the first transistor in response to the scan signal.
  • each of the plurality of pixels may include a capacitor electrically connected between a gate electrode of the first transistor and the first power line.
  • the display device may further include a common circuit electrically connected between the data line and the plurality of pixels.
  • the common circuit may include a second transistor that transmits the data signal to the first transistor of each of the plurality of pixels in response to the scan signal.
  • the display device may further include a third power line.
  • the common circuit may include a capacitor electrically connected between a gate electrode of the first transistor of each of the plurality of pixels and the first power line; and a third transistor electrically connected to the third power line and an electrode of the capacitor.
  • each of the plurality of pixels may include a fourth transistor electrically connected between anode electrodes of the light emitting elements and the third power line.
  • each of the plurality of pixels may include a capacitor electrically connected to a gate electrode of the first transistor and an electrode of the first transistor.
  • the display device may further include a third power line.
  • Each of the plurality of pixels may include a capacitor coupled between a gate electrode of the first transistor of each of the plurality of pixels and the first power line; a third transistor electrically connected to the third power line and one electrode of the capacitor; and a fourth transistor electrically connected between anode electrodes of the light emitting elements and the third power line.
  • the display device may further include a sensing line.
  • Each of the plurality of pixels may include a fifth transistor electrically connected between anode electrodes of the light emitting elements and the sensing line.
  • At least some of the light emitting elements included in each of the plurality of pixels may be electrically connected in series between the first power line and the second power line.
  • a display device in accordance with an embodiment of the disclosure may include a first power line; a second power line; a data line that transmits a data signal; a scan line that transmits a scan signal; and a pixel electrically connected to the first power line, the second power line, the data line, and the scan line.
  • the pixel may include a plurality of light source units electrically connected between the first power line and the second power line, each of the plurality of light source units comprising a plurality of light emitting elements; and a plurality of pixel circuits that independently provide, to each of the plurality of light source units, driving current corresponding to the data signal provided in response to the scan signal.
  • each of the plurality of pixel circuits may include a first transistor that provides driving current to the plurality of light emitting elements in response to the data signal.
  • the pixel may further include a common circuit electrically connected to the data line, the scan line, and the plurality of pixel circuits.
  • the common circuit may include a second transistor that transmits the data signal to the first transistor of each of the plurality of pixel circuits in response to the scan signal.
  • a display device in accordance with an embodiment of the disclosure may include a substrate including an emission area; a first electrode disposed on the emission area of the substrate; second electrodes disposed on the emission area of the substrate, facing the first electrode, and spaced apart from each other and electrically disconnected from each other; first light emitting elements disposed between a first sub-electrode of the second electrodes and the first electrode; and second light emitting elements disposed between a second sub-electrode of the second electrodes and the first electrode.
  • the display device may further include a bank disposed on the substrate along a perimeter of the emission area.
  • the bank may not be disposed between the second electrodes in the emission area.
  • the first electrode may extend in a first direction.
  • the second electrodes may extend in the first direction and be spaced apart from each other in the first direction.
  • the first electrode may extend in a first direction.
  • the second electrodes may extend in the first direction and be spaced apart from each other in a second direction perpendicular to the first direction.
  • the display device may further include a third electrode disposed between the first sub-electrode and the first electrode, and spaced apart from the first sub-electrode and the first electrode.
  • the first light emitting elements each may be disposed between two adjacent electrodes among the first sub-electrode, the first electrode, and the third electrode.
  • light emitting elements distributed to sub-emission areas which form each pixel may be independently driven by sub-emission areas, so that the light emitting elements in each pixel can uniformly emit light.
  • FIGS. 1 A and 1 B are respectively a perspective view and a cross-sectional view schematically illustrating a light emitting element in accordance with an embodiment of the disclosure.
  • FIGS. 2 A and 2 B are respectively a perspective view and a cross-sectional view schematically illustrating a light emitting element in accordance with an embodiment of the disclosure.
  • FIGS. 3 A and 3 B are respectively a perspective view and a cross-sectional view schematically illustrating a light emitting element in accordance with an embodiment of the disclosure.
  • FIG. 4 is a plan view schematically illustrating a display device in accordance with an embodiment of the disclosure.
  • FIG. 5 is a circuit diagram schematically illustrating an example of a sub-pixel included in the display device of FIG. 4 .
  • FIGS. 6 A to 6 D are circuit diagrams schematically illustrating an example of a unit pixel included in the sub-pixel of FIG. 5 .
  • FIG. 6 E is a waveform diagram schematically illustrating examples of signals to be applied to the sub-pixel of FIG. 6 C .
  • FIG. 7 is a plan view schematically illustrating an example of a sub-pixel included in the display device of FIG. 4 .
  • FIG. 8 is a plan view schematically illustrating an example of a first unit pixel included in a first sub-pixel of the sub-pixels of FIG. 7 .
  • FIGS. 9 A to 9 D are cross-sectional views schematically illustrating examples of the unit pixel, taken along line I-I′ of FIG. 8 .
  • FIGS. 10 A and 10 B are plan views schematically illustrating other examples of a sub-pixel included in the display device of FIG. 4 .
  • FIG. 11 is a circuit diagram schematically illustrating an example of a sub-pixel included in the pixel of FIG. 4 .
  • FIG. 12 is a circuit diagram schematically illustrating an example of a sub-pixel included in the pixel of FIG. 4 .
  • FIG. 13 is a circuit diagram schematically illustrating an example of a sub-pixel included in the pixel of FIG. 4 .
  • FIG. 14 is a circuit diagram schematically illustrating an example of a sub-pixel included in the pixel of FIG. 4 .
  • the light emitting element LD may be provided in the form of a rod extending in a direction.
  • the light emitting element LD may have a first end and a second end in a direction.
  • one of the first and second conductive semiconductor layers 11 and 13 may be disposed on the first end of the light emitting element LD, and the other of the first and second conductive semiconductor layers 11 and 13 may be disposed on the second end of the light emitting element LD.
  • the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod.
  • the term “rod-like shape” embraces a rod-like shape and a bar-like shape such as a cylindrical shape and a prismatic shape that is longer in a longitudinal direction than in a width direction (for example, having an aspect ratio greater than one), and the cross-sectional shape thereof is not limited to a particular shape.
  • a length L of the light emitting element LD may be greater than a diameter D thereof (or a width of the cross-section thereof).
  • the first conductive semiconductor layer 11 may include at least one n-type semiconductor layer.
  • the first conductive semiconductor layer 11 may include an n-type semiconductor layer which includes a semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and is doped with a first conductive dopant such as Si, Ge, or Sn.
  • a material for forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.
  • the active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single or multiple quantum well structure.
  • a cladding layer (not shown) doped with a conductive dopant may be formed over and/or under the active layer 12 .
  • the cladding layer may be formed of an AlGaN layer or an InAlGan layer.
  • a material such as AlGaN or AlInGaN may be used to form the active layer 12 , and various other materials may be used to form the active layer 12 .
  • the insulating film INF may expose an end of each of the first and second conductive semiconductor layers 11 and 13 that are disposed on the respective opposite ends of the light emitting element LD in the longitudinal direction, and, e.g., may expose two surfaces (for example, top and bottom surfaces) of the cylinder rather than covering (or overlapping) them.
  • the insulating film INF may include at least one insulating material of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), and titanium dioxide (TiO 2 ), but the disclosure is not limited thereto.
  • a material that forms the insulating film INF is not limited to a particular material, and the insulating film INF may be formed of various insulating materials.
  • the light emitting element LD may further include additional other components as well as the first conductive semiconductor layer 11 , the active layer 12 , the second conductive semiconductor layer 13 , and/or the insulating film INF.
  • the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers, and/or one or more electrode layers disposed on ends of the first conductive semiconductor layer 11 , the active layer 12 , and/or the second conductive semiconductor layer 13 .
  • the light emitting element LD may further include at least one electrode layer 15 disposed on an end of the first conductive semiconductor layer 11 .
  • each of the electrode layers 14 and 15 may be an ohmic contact electrode, but the disclosure is not limited thereto. Furthermore, each of the electrode layers 14 and 15 may include metal or conductive metal oxide. For example, each of the electrode layers 14 and 15 may be formed of transparent electrode materials such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides or alloys thereof, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO) alone or in combination. The electrode layers 14 and 15 may be substantially transparent or semitransparent. Therefore, light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15 .
  • the insulating film INF may at least partially enclose outer surfaces of the electrode layers 14 and 15 , or may not enclose them. In other words, the insulating film INF may be selectively formed on surfaces of the electrode layers 14 and 15 . Furthermore, the insulating film INF may be formed to expose the opposite ends of the light emitting element LD that have different polarities and, for example, may expose at least an area of each of the electrode layers 14 and 15 . However, the disclosure is not limited thereto, and the insulating film INF may not be provided.
  • the active layer 12 may be prevented from short-circuiting with at least one electrode, e.g., at least one contact electrode of contact electrodes electrically connected to the opposite ends of the light emitting element LD, etc. Consequently, the electrical stability of the light emitting element LD may be ensured.
  • the insulating film INF may be formed on the surface of the light emitting element LD, thereby minimizing surface defects of the light emitting element LD and improving the lifespan and efficiency of the light emitting element LD. Moreover, the insulating film INF is formed on the surface of the light emitting element LD, thereby preventing an undesired short circuit between the light emitting elements LD from occurring even if multiple light emitting elements LD are arranged in close proximity to each other.
  • the light emitting element LD may be manufactured by a surface treatment process (e.g., coating).
  • a surface treatment process e.g., coating
  • the light emitting elements LD when the light emitting elements LD is mixed with fluid solution (or solvent) and supplied to each emission area (e.g., an emission area of each pixel), the light emitting elements LD may be uniformly dispersed without being non-uniformly aggregated in the solution.
  • the emission area is an area in which light is emitted by the light emitting elements LD.
  • the emission area may be distinguished from a non-emission area in which light is not emitted.
  • the insulating film INF itself may be formed of a hydrophobic film using hydrophobic material, or an additional hydrophobic film formed of hydrophobic material may be formed on the insulating film INF.
  • the hydrophobic material may be a material containing fluorine to exhibit hydrophobicity.
  • the hydrophobic material may be applied to the light emitting elements LD in the form of a self-assembled monolayer (SAM).
  • SAM self-assembled monolayer
  • the hydrophobic material may include octadecyl trichlorosilane, fluoroalkyl trichlorosilane, perfluoroalkyl triethoxysilane, etc.
  • the hydrophobic material may be a commercially available fluorine containing material such as TeflonTM or CytopTM or a corresponding material.
  • a light emitting device including the light emitting element LD described above may be used in various devices including a display device which requires a light source.
  • at least one subminiature light emitting element LD e.g., subminiature light emitting elements LD each having a size ranging from the nanometer scale to the micrometer scale, may be disposed in each pixel area of the display panel to form a light source (or a light source unit) of the corresponding pixel using the subminiature light emitting elements LD.
  • the field of application of the light emitting element LD according to the disclosure is not limited to a display device.
  • the light emitting element LD may also be used in other types of devices such as a lighting device, which requires a light source.
  • FIG. 4 is a plan view schematically illustrating a display device in accordance with an embodiment.
  • FIG. 4 illustrates a display device, particularly, a display panel PNL provided in the display device, as an example of a device which may use, as a light source, the light emitting elements LD described with reference to FIGS. 1 A to 3 B .
  • FIG. 4 schematically illustrates the structure of the display panel PNL, focusing on a display area DA.
  • at least one driving circuit component e.g., at least one of a scan driver and a data driver
  • lines may be further provided on the display panel PNL.
  • the display panel PNL may include a base layer SUB 1 (or substrate) and a pixel PXL disposed on the base layer SUB 1 .
  • the display panel PNL and the base layer SUB 1 may include a display area DA configured to display an image, and a non-display area NDA formed in a predetermined area other than the display area DA.
  • the display area DA may be disposed in a central area of the display panel PNL, and the non-display area NDA may be disposed along a border of the display panel PNL in such a way as to enclose the display area DA.
  • the locations of the display area DA and the non-display area NDA are not limited thereto, and the locations thereof may be changed.
  • the base layer SUB 1 may form a base of the display panel PNL.
  • the base layer SUB 1 may form a base of a lower panel (e.g., a lower plate of the display panel PNL).
  • the base layer SUB 1 may be a rigid or flexible substrate, and the material or properties thereof are not particularly limited.
  • the base layer SUB 1 may be a rigid substrate made of glass or reinforced (or tempered) glass, or a flexible substrate formed of a thin film made of plastic or metal.
  • the base layer SUB 1 may be a transparent substrate, but the disclosure is not limited thereto.
  • the base layer SUB 1 may be a translucent substrate, an opaque substrate, or a reflective substrate.
  • the pixel PXL may include at least one light emitting element LD, e.g., at least one rod-type light emitting diode according to an embodiment shown in FIGS. 1 A to 3 B , which is driven by a corresponding scan signal and a corresponding data signal.
  • the pixel PXL may include rod-type light emitting diodes, each of which has a small size ranging from the nanometer scale to the micrometer scale, and which are electrically connected in parallel to each other.
  • the rod-type light emitting diodes may form a light source of each pixel PXL.
  • the pixel PXL may include sub-pixels.
  • the pixel PXL may include a first sub-pixel SPX 1 , a second sub-pixel SPX 2 , and a third sub-pixel SPX 3 .
  • the first, second, and third sub-pixels SPX 1 , SPX 2 , and SPX 3 may emit different colors of light.
  • the first sub-pixel SPX 1 may be a red sub-pixel for emitting red light
  • the second sub-pixel SPX 2 may be a green sub-pixel for emitting green light
  • the third sub-pixel SPX 3 may be a blue sub-pixel for emitting blue light.
  • each pixel PXL the colors, types, and/or numbers of sub-pixels forming each pixel PXL are not particularly limited.
  • the color of light which is emitted from each sub-pixel may be changed in various ways.
  • FIG. 4 illustrates an embodiment where the pixels PXL are arranged in the display area DA in a stripe shape, the disclosure is not limited thereto.
  • the pixels PXL may be arranged in various pixel array forms.
  • each of the first to third sub-pixels SPX 1 , SPX 2 , and SPX 3 may include unit pixels.
  • the first sub-pixel SPX 1 may be electrically connected to a scan line Si and a data line Dj and also be electrically connected to a first power line and a second power line.
  • a first power supply VDD may be applied to the first power line
  • a second power supply VSS may be applied to the second power line.
  • Each of the first and second power lines may be a common line electrically connected to the first to third sub-pixels SPX 1 , SPX 2 , and SPX 3 .
  • the first and second power supplies VDD and VSS may have different potentials to allow the first sub-pixel SPX 1 to emit light.
  • the first power supply VDD may have a voltage level higher than that of the second power supply VSS.
  • the first sub-pixel SPX 1 may include first to k-th unit pixels SSPX 1 to SSPXk (where k is an integer of two or more).
  • Each of the unit pixel SSPX 1 to SSPXk may be electrically connected to the scan line Si and the data line Dj and also be electrically connected to the first power line and the second power line.
  • Each of the first to k-th unit pixels SSPX 1 to SSPXk may emit light having a luminance corresponding to a data signal transmitted through the data line Dj in response to a scan signal transmitted through the scan line Si.
  • the first to k-th unit pixels SSPX 1 to SSPXk may include substantially a same pixel structure or pixel circuit.
  • the first sub-pixel SPX 1 may include first to k-th unit pixels SSPX 1 to SSPXk that independently emit light, in response to a scan signal and a data signal.
  • each of the first to k-th unit pixels SSPX 1 to SSPXk may be configured as an active pixel.
  • the types, structures, and/or driving methods of the unit pixels capable of being applied to the display device according to the disclosure are not particularly limited.
  • the unit pixel may be configured of a pixel of the display device having various passive or active structures.
  • FIGS. 6 A to 6 D are circuit diagrams schematically illustrating an example of a unit pixel included in the sub-pixel of FIG. 5 .
  • the unit pixel SSPX may include a light source unit LSU that emits light having a luminance corresponding to a data signal.
  • the unit pixel SSPX may selectively further include a pixel circuit PXC configured to drive the light source unit LSU.
  • the light source unit LSU may include light emitting elements LD that are electrically connected to each other between the first power supply VDD and the second power supply VSS.
  • the light emitting elements LD may be electrically connected in parallel to each other, but the disclosure is not limited thereto.
  • light emitting elements LD may be electrically connected in a serial/parallel combination structure between the first power supply VDD and the second power supply VSS.
  • the first and second power supplies VDD and VSS may have different potentials to allow the light emitting elements LD to emit light.
  • the first power supply VDD may be set as a high-potential power supply
  • the second power supply VSS may be set as a low-potential power supply.
  • a difference in potential between the first and second power supplies VDD and VSS may be set to a threshold voltage of the light emitting elements LD or greater at least during a light emitting period of the unit pixel SSPX (or the first sub-pixel SPX 1 ).
  • FIG. 6 A illustrates an embodiment in which the light emitting elements LD are electrically connected in parallel to each other in a same direction (e.g., in a forward direction) between the first power supply VDD and the second power supply VSS
  • the disclosure is not limited thereto.
  • some of the light emitting elements LD may be electrically connected to each other in the forward direction between the first and second power supplies VDD and VSS, thereby forming respective effective light sources, and other light emitting elements LD may be electrically connected to each other in a reverse direction.
  • the unit pixel SSPX may include only a single light emitting element LD (e.g., a single effective light source electrically connected in the forward direction between the first and second power supplies VDD and VSS).
  • the light source unit LSU may emit light having a luminance corresponding to driving current supplied thereto through the corresponding pixel circuit PXC. Therefore, a predetermined image may be displayed in the display area DA (see FIG. 4 ).
  • the pixel circuit PXC may be electrically connected to the scan line Si and the data line Dj of the corresponding sub-pixel (for example, the first sub-pixel SPX 1 ).
  • the pixel circuit PXC of the unit pixel SSPX may be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA.
  • the pixel circuit PXC may include a first transistor T 1 , a second transistor T 2 , and a storage capacitor Cst.
  • the first transistor (or driving transistor) T 1 may be electrically connected between the first power supply VDD and the light source unit LSU.
  • a gate electrode of the first transistor T 1 may be electrically connected to a first node N 1 .
  • the first transistor T 1 may control driving current to be supplied to the light source unit LSU in response to a voltage of the first node N 1 .
  • the second transistor T 2 may be turned on to electrically connect the first node N 1 to the data line Dj.
  • a gate-on voltage e.g., a low voltage
  • a data signal of a corresponding frame is supplied to the data line Dj.
  • the data signal may be transmitted to the first node N 1 via the second transistor T 2 . Therefore, a voltage corresponding to the data signal may be stored in the storage capacitor Cst.
  • An electrode of the storage capacitor Cst may be electrically connected to the first power supply VDD, and another electrode thereof may be electrically connected to the first node N 1 .
  • the storage capacitor Cst may store a voltage corresponding to a data signal supplied to the first node N 1 during each frame period and maintain the stored voltage until a data signal of a subsequent frame is supplied.
  • the first and second transistors T 1 and T 2 may be N-type transistors.
  • the gate-on voltage of the scan signal for writing the data signal, supplied to the data line Dj in each frame period, in the unit pixel SSPX may be a high-level voltage.
  • the voltage of the data signal for turning on the first transistor T 1 may be a voltage having a waveform opposite to that of the embodiment of FIG. 6 A .
  • a data signal having a higher voltage level may be supplied.
  • the unit pixel SSPX shown in FIG. 6 B is substantially similar in configuration and operation to the unit pixel SSPX of FIG. 6 A , except that the connection positions of some circuit elements and the voltage levels of control signals (e.g., a scan signal and a data signal) are changed depending on a change in type of the transistor. Therefore, detailed descriptions of the unit pixel SSPX of FIG. 6 B will be omitted.
  • the pixel circuit PXC may be electrically connected not only to a corresponding scan line Si but also to at least another scan line (or another control line).
  • the pixel circuit PXC of the sub-pixel SPX (or the unit pixel SSPX included therein) disposed in the i-th row of the display area DA may be further electrically connected to an i ⁇ 1-th scan line Si ⁇ 1 and/or an i+1-th scan line Si+1.
  • the pixel circuit PXC may be electrically connected not only to the first and second power supplies VDD and VSS but also to other power supplies.
  • the pixel circuit PXC may also be electrically connected to an initialization power supply Vint.
  • the second transistor T 2 may be electrically connected between the data line Dj and the first electrode of the first transistor T 1 .
  • a gate electrode of the second transistor T 2 may be electrically connected to the corresponding scan line Si.
  • the second transistor T 2 may be turned on to electrically connect the data line Dj to the first electrode of the first transistor T 1 .
  • a data signal supplied from the data line Dj may be transmitted to the first transistor T 1 .
  • the third transistor T 3 may be electrically connected between the second electrode (e.g., the drain electrode) of the first transistor T 1 and the first node N 1 .
  • a gate electrode of the third transistor T 3 may be electrically connected to the corresponding scan line Si. In case that a scan signal of a gate-on voltage is supplied from the scan line Si, the third transistor T 3 may be turned on to electrically connect the first transistor T 1 in the form of a diode.
  • the fourth transistor T 4 may be electrically connected between the first node N 1 and the initialization power supply Vint.
  • a gate electrode of the fourth transistor T 4 may be electrically connected to a preceding scan line, e.g., an i ⁇ 1-th scan line Si ⁇ 1.
  • the fourth transistor T 4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N 1 .
  • the voltage of the initialization power supply Vint may be a minimum voltage of a data signal or less.
  • the fifth transistor T 5 may be electrically connected between the first power supply VDD and the first transistor T 1 .
  • a gate electrode of the fifth transistor T 5 may be electrically connected to a corresponding emission control line, e.g., an i-th emission control line Ei.
  • the fifth transistor T 5 may be turned off in case that an emission control signal having a gate-off voltage (e.g., a high voltage) is supplied to the emission control line Ei, and may be turned on in other cases.
  • a gate-off voltage e.g., a high voltage
  • the sixth transistor T 6 may be electrically connected between the first transistor T 1 and the first electrode of the light source unit LSU.
  • a gate electrode of the sixth transistor T 6 may be electrically connected to a corresponding emission control line, e.g., the i-th emission control line Ei.
  • the sixth transistor T 6 may be turned off in case that an emission control signal of a gate-off voltage is supplied to the emission control line Ei, and may be turned on in other cases.
  • a control signal for controlling an operation of the seventh transistor T 7 may be variously changed.
  • the gate electrode of the seventh transistor T 7 may be electrically connected to a scan line of a corresponding horizontal line, for example, an i-th scan line Si.
  • the seventh transistor T 7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.
  • the storage capacitor Cst may be electrically connected between the first power supply VDD and the first node N 1 .
  • the storage capacitor Cst may store a voltage corresponding to the data signal applied to the first node N 1 during each frame period and to the threshold voltage of the first transistor T 1 .
  • FIG. 6 E is a waveform diagram schematically illustrating examples of signals to be applied to the sub-pixel SSPX of FIG. 6 C .
  • a first scan signal GI (or a preceding scan signal) may be provided to the i ⁇ 1-th scan line Si ⁇ 1 shown in FIG. 6 C
  • a second scan signal GW may be provided to the i-th scan line Si (or the corresponding scan line) shown in FIG. 6 C
  • the first scan signal GI may also be provided to the i+1-th scan line Si+1 shown in FIG. 6 C
  • An emission control signal EM may be provided to the i-th emission control line Ei shown in FIG. 6 C .
  • the first scan signal GI may transition from a voltage level of a gate-off voltage OFF (e.g., a high voltage) to a voltage level of a gate-on voltage ON (e.g., a low voltage) and maintain the voltage level of the gate-on voltage until a second time point t 2 .
  • the second scan signal GW and the emission control signal EM may have the voltage level of the gate-off voltage.
  • the fourth transistor T 4 may be turned on in response to the first scan signal GI having the gate-on voltage, and the third node N 3 and the storage capacitor Cst may be initialized by the voltage of the initialization power supply Vint.
  • the seventh transistor T 7 may be turned on in response to the first scan signal GI having the gate-on voltage, and a voltage of the first electrode of the light source unit LSU may be initialized by the voltage of the initialization power supply Vint.
  • the unit pixel SSPX may be initialized by the voltage of the initialization power supply Vint.
  • the first scan signal GI may transition to the voltage level of the gate-off voltage
  • the second scan signal GW may transition to the voltage level of the gate-on voltage.
  • the voltage level of the second scan signal GW may be maintained at the voltage level of the gate-on voltage (e.g., the low voltage) until a third time point t 3 .
  • the second transistor T 2 and the third transistor T 3 may be turned on in response to the second scan signal GW having the gate-on voltage.
  • a data signal may be transmitted from the data line Dj to the storage capacitor Cst through the second transistor T 2 , the first transistor T 1 , and the third transistor T 3 .
  • the storage capacitor Cst may store the data signal.
  • a data signal may be provided to and stored in the unit pixel SSPX.
  • the emission control signal EM may transition from the voltage level of the gate-off voltage to the voltage level of the gate-on voltage and be maintained at the voltage level of the gate-on voltage until a fifth time point t 5 .
  • the first scan signal GI and the second scan signal GW each may have the voltage level of the gate-off voltage.
  • the fifth transistor T 5 and the sixth transistor T 6 may be turned on in response to the emission control signal EM having the gate-on voltage.
  • a current movement path for driving current may be formed from the first power supply VDD to the light source unit LSU through the fifth transistor T 5 , the first transistor T 1 , and the sixth transistor T 6 .
  • Driving current corresponding to the voltage of the first node N 1 (for example, a data signal stored in the storage capacitor Cst) may be supplied to the light source unit LSU. Therefore, the light source unit LSU may emit light having a luminance corresponding to the data signal.
  • the unit pixel SSPX may emit light having a luminance corresponding to the data signal.
  • waveforms of the first scan signal GI, the second scan signal GW, and the emission control signal EM may be identical to waveforms of the first scan signal GI, the second scan signal GW, and the emission control signal EM at the first time point t 1 .
  • the first to sixth time points t 1 to t 6 may form a frame FRAME 1 , and the unit pixel SSPX may be repeatedly operated on a frame basis.
  • FIG. 6 C illustrates that the transistors included in the pixel circuit PXC, e.g., the first to seventh transistors T 1 to T 7 , are P-type transistors, the disclosure is not limited thereto.
  • at least one of the first to seventh transistors T 1 to T 7 may be changed to an N-type transistor.
  • the pixel circuit PXC may be further electrically connected to another line as well as the data line Dj.
  • the pixel circuit PXC may be electrically connected to a sensing line SENj.
  • the pixel circuit PXC may include first to third transistors T 1 to T 3 and a storage capacitor Cst. Since the first and second transistors T 1 and T 2 and the storage capacitor Cst are substantially identical or similar to the first and second transistors T 1 and T 2 and the storage capacitor Cst described with reference to FIG. 6 B , repetitive descriptions thereof will be omitted.
  • the third transistor T 3 may be electrically connected between the sensing line SENj and a second node N 2 .
  • the gate electrode of the third transistor T 3 may be electrically connected to a second scan line S 2 different from a first scan line Si (e.g., a i+1-th scan line Si+1 different from a i-th scan line Si).
  • the light source unit LSU may be electrically connected between the second node N 2 and the second power line (for example, a power line to which the second power supply VSS is applied).
  • the third transistor T 3 may be turned on in response to a scan signal of the gate-on voltage transmitted from the second scan line S 2 to electrically connect the sensing line SENj to the second node N 2 .
  • the driving current flowing through the first transistor T 1 may be provided to an external sensing device through the third transistor T 3 and the sensing line SENj, and a signal corresponding to the characteristics of the first transistor T 1 (e.g., the threshold voltage) based on the driving current may be output through the sensing line SENj to an external device.
  • a signal corresponding to the characteristics of the first transistor T 1 e.g., the threshold voltage
  • the structure of the unit pixel SSPX which may be applied to the disclosure is not limited to that in the embodiments shown in FIGS. 6 A to 6 D , and the unit pixel S SPX may have various structures.
  • the pixel circuit PXC included in the unit pixel SSPX may be formed of a pixel circuit which may have various structures and/or be operated by various driving methods.
  • the unit pixel SSPX may be formed in a passive light emitting display panel or the like. In this case, the pixel circuit PXC may be omitted, and each of the first and second electrodes of the light source unit LSU may be directly and electrically connected to the scan line Si, the data line Dj, a power line, and/or a control line.
  • FIG. 7 is a plan view schematically illustrating an example of sub-pixels included in the display device of FIG. 4 .
  • FIG. 7 illustrates the structure of first to third sub-pixels SPX 1 to SPX 3 based on a light source unit LSU (refer to FIGS. 6 A to 6 D ) (or a light emitting element layer) included in the first to third sub-pixels SPX 1 to SPX 3 .
  • FIG. 8 is a plan view schematically illustrating an example of a first unit pixel included in a first sub-pixel of the sub-pixels of FIG. 7 .
  • the first to third sub-pixels SPX 1 to SPX 3 may be identical with each other.
  • first and second unit pixels SSPX 1 and SSPX 2 included in each of the first to third sub-pixels SPX 1 to SPX 3 may be top-and-bottom symmetrical structure based on a reference line L_REF, the light source unit LSU will be described, focusing on the first sub-pixel SPX 1 and the first unit pixel SSPX 1 .
  • the first sub-pixel SPX 1 may include a first electrode ELT 1 and a second electrode ELT 2 disposed at positions spaced apart from each other in a first sub-pixel area SPA 1 , and at least one light emitting element LD electrically connected between the first and second electrodes ELT 1 and ELT 2 .
  • first, second, and third light emitting elements LD 1 , LD 2 , and LD 3 included in each of the first to third sub-pixels SPX 1 to SPX 3 may emit light having the same color or different colors.
  • each first light emitting element LD 1 may be a red light emitting diode configured to emit red light.
  • Each second light emitting element LD 2 may be a green light emitting diode configured to emit green light.
  • Each third light emitting element LD 3 may be a blue light emitting diode configured to emit blue light.
  • all of the first, second, and third light emitting elements LD 1 , LD 2 , and LD 3 may be formed of blue light emitting diodes configured to emit blue light.
  • a light conversion layer for converting the color of light emitted from the corresponding sub-pixel SPX and/or a color filter may be disposed on at least some of the first to third sub-pixels SPX 1 , SPX 2 , and SPX 3 .
  • the first electrode ELT 1 and the second electrode ELT 2 may be disposed at positions spaced apart from each other in the first sub-pixel area SPA 1 such that at least predetermined areas thereof face each other.
  • the first and second electrodes ELT 1 and ELT 2 each may extend in the first direction DR 1 and may be spaced apart from each other by a predetermined distance in the second direction DR 2 that is substantially perpendicular to or intersects the first direction DR 1 .
  • the disclosure is not limited thereto.
  • the shapes and/or mutual arrangement relationship of the first and second electrodes ELT 1 and ELT 2 may be changed in various ways.
  • the first sub-pixel area SPA 1 may include an emission area EMA and a non-emission area NEMA.
  • the emission area EMA may include sub-emission areas separated from each other.
  • the first electrode ELT 1 may be disposed in each of the sub-emission areas.
  • the second electrode ELT 2 may be disposed in the entirety of the emission area EMA, for example, across the sub-emission areas.
  • the emission area EMA may be a unit area which expresses (or displays) single color light, be separated from an emission area configured to emit another color of light, and be defined by a pixel defining layer (or a bank or a light shielding pattern) or the like which blocks light emitted from a light emitting element LD from passing through other areas.
  • the first sub-pixel area SPA 1 may include an emission area EMA and a non-emission area NEMA.
  • the emission area EMA may include first and second sub-emission areas EMA_S 1 and EMA_S 2 separated from each other in the first direction DR 1 based on the reference line L_REF.
  • the first electrode ELT 1 may be disposed in each of the first and second sub-emission areas EMA_S 1 and EMA_S 2 based on the reference line L_REF.
  • the second electrode ELT 2 may be disposed in the entirety of the emission area EMA, for example, across the first and second sub-emission areas EMA_S 1 and EMA_S 2 .
  • the first electrode ELT 1 disposed in the second sub-emission area EMA_S 2 may be spaced, in the first direction DR 1 , apart from the first electrode ELT 1 disposed in the first sub-emission area EMA_S 1 , and electrically separated or insulated from the first electrode ELT 1 disposed in the first sub-emission area EMA_S 1 .
  • FIG. 7 illustrates that the emission area EMA include the first and second sub-emission areas EMA_S 1 and EMA_S 2 , this is for illustrative purposes.
  • the emission area EMA may include three or more sub-emission areas.
  • FIG. 7 illustrates that the first and second sub-emission areas EMA_S 1 and EMA_S 2 are successive (or adjacent) to each other, this is for illustrative purposes.
  • the first and second sub-emission areas EMA_S 1 and EMA_S 2 may be spaced apart from each other by a pixel defining layer (or a bank) or the like disposed therebetween.
  • the first electrode ELT 1 may be electrically connected to a first connection electrode CNL 1 (or a first connection line) extending in the second direction DR 2 .
  • the first electrodes ELT 1 included in each sub-emission area may be electrically connected to each other by the first connection electrode CNL 1 .
  • the second electrode ELT 2 may be electrically connected to a second connection electrode CNL 2 (or a second connection line) extending in the second direction DR 2 .
  • the second connection electrode CNL 2 may be electrically connected to the second power line (for example, a power line to which the second power supply VSS is applied) described with reference to FIGS. 6 A, 6 C, and 6 D .
  • FIG. 7 illustrates that the second connection electrode CNL 2 is disposed in only the corresponding sub-pixel SPX, this is for illustrative purposes, and the disclosure is not limited thereto.
  • the second connection electrode CNL 2 may extend to an adjacent sub-pixel SPX (e.g., the second and third sub-pixels SPX 2 and SPX 3 based on the first sub-pixel SPX 1 ).
  • each of the first and second electrodes ELT 1 and ELT 2 may have a single-layer or multi-layer structure.
  • the first electrode ELT 1 may have a multi-layer structure including a first reflective electrode and a first conductive capping layer.
  • the second electrode ELT 2 may have a multi-layer structure including a second reflective electrode and a second conductive capping layer.
  • the first electrode ELT 1 may be electrically connected to the first connection electrode CNL 1 .
  • the first electrode ELT 1 may be integrally and electrically connected to the first connection electrode CNL 1 .
  • the first electrode ELT 1 may be formed of at least one branch diverging from the first connection electrode CNL 1 .
  • the first connection electrode CNL 1 may be regarded as an area of the first electrode ELT 1 .
  • the disclosure is not limited thereto.
  • the first electrode ELT 1 and the first connection electrode CNL 1 may be individually formed and electrically connected to each other through at least one contact hole CH 1 , a via hole, or the like.
  • the second electrode ELT 2 may be electrically connected to the second connection electrode CNL 2 .
  • the second connection electrode CNL 2 may be independently formed from the second electrode ELT 2 and electrically connected to the second electrode ELT 2 through at least one second contact hole CH 2 , a via hole, or the like.
  • the disclosure is not limited thereto.
  • the second electrode ELT 2 may be integrally coupled to the second connection electrode CNL 2 .
  • the second electrode ELT 2 may be formed of at least one branch diverging from the second connection electrode CNL 2 .
  • the second connection electrode CNL 2 may be regarded as an area of the second electrode ELT 2 .
  • a first partition wall (or first bank) PW 1 may be disposed under the first electrode ELT 1 and overlap an area of the first electrode ELT 1 .
  • a second partition wall PW 2 may be disposed under the second electrode ELT 2 and overlap an area of the second electrode ELT 2 .
  • the first and second partition walls PW 1 and PW 2 may be disposed in the emission area EMA at positions spaced apart from each other, and make areas of the first and second electrodes ELT 1 and ELT 2 protrude upward.
  • the first electrode ELT 1 may be disposed on the first partition wall PW 1 and protrude in a height direction (or a thickness direction) of the base layer SUB 1 by the first partition wall PW 1 .
  • the second electrode ELT 2 may be disposed on the second partition wall PW 2 and protrude in the height direction of the base layer SUB 1 by the second partition wall PW 2 .
  • At least one light emitting element LD may be arranged between the first and second electrodes ELT 1 and ELT 2 .
  • Light emitting elements LD may be electrically connected in parallel to each other in the emission area EMA (or the first sub-emission area EMA_S 1 , refer to FIG. 7 ) in which the first electrode ELT 1 and the second electrode ELT 2 are disposed to face each other.
  • FIG. 8 illustrates that the light emitting elements LD are arranged between the first and second electrodes ELT 1 and ELT 2 in the second direction DR 2 , e.g., in a horizontal direction
  • the arrangement direction of the light emitting elements LD is not limited thereto.
  • at least one of the light emitting elements LD may be oriented in a diagonal direction.
  • Each of the light emitting elements LD may be electrically connected between the first electrode ELT 1 and the second electrode ELT 2 .
  • the respective first ends EP 1 of the light emitting elements LD may be electrically connected to the first electrode ELT 1 .
  • the respective second ends EP 2 of the light emitting elements LD may be electrically connected to the second electrode ELT 2 .
  • the first end of each of the light emitting elements LD may be electrically connected to the corresponding first electrode ELT 1 through at least one contact electrode, e.g., a first contact electrode CNE 1 , rather than being directly disposed on the first electrode ELT 1 .
  • the disclosure is not limited thereto.
  • the first ends of the light emitting elements LD may directly contact the first electrode ELT 1 to be electrically connected to the first electrode ELT 1 .
  • each of the light emitting elements LD may be a light emitting diode which is made of material having an inorganic crystal structure and has a subminiature size, e.g., a size corresponding to the nanometer or micrometer scale.
  • each of the light emitting elements LD may be a subminiature light emitting element (e.g., rod-type light emitting diode) having a size ranging from the nanometer scale to the micrometer scale, as illustrated in any one of FIGS. 1 A to 3 B .
  • a type of light emitting elements LD which may be applied to the disclosure is not limited thereto.
  • the light emitting element LD may be formed by a growth method and be a light emitting diode having a core-shell structure having a size corresponding to, e.g., the nanometer scale to the micrometer scale.
  • the light emitting elements LD may be prepared in diffused form in a predetermined solution and be supplied to the emission area EMA of each sub-pixel SPX by an inkjet printing method or a slit coating method. Furthermore, the light emitting elements LD may be simultaneously supplied to the first and second sub-emission areas EMA_S 1 and EMA_S 2 in the emission area EMA. For example, the light emitting elements LD may be mixed with a volatile solvent and be supplied to the emission area EMA.
  • the light emitting elements LD are self-aligned between the first and second electrodes ELT 1 and ELT 2 .
  • the solvent may be removed by a volatilization method or other methods. In this way, the light emitting elements LD may be reliably arranged between the first and second electrodes ELT 1 and ELT 2 .
  • the light emitting elements LD may be reliably and electrically connected between the first and second electrodes ELT 1 and ELT 2 .
  • the first contact electrode CNE 1 may be formed on the first ends EP 1 of the light emitting elements LD and at least one area of the first electrode ELT 1 corresponding to the first ends EP 1 , whereby the first ends EP 1 of the light emitting elements LD may be physically and/or electrically connected to the first electrode ELT 1 .
  • the second contact electrode CNE 2 may be formed on the second ends EP 2 of the light emitting elements LD and at least one area of the second electrode ELT 2 corresponding to the second ends EP 2 , whereby the second ends EP 2 of the light emitting elements LD may be physically and/or electrically connected to the second electrode ELT 2 .
  • the light emitting elements LD disposed in the emission area EMA may form a light source of the corresponding unit pixel (and the sub-pixel SPX).
  • the light emitting elements LD disposed in the first and second sub-emission areas EMA_S 1 and EMA_S 2 shown in FIG. 7 may form a light source.
  • the light emitting elements LD that are electrically connected in the forward direction between the first and second electrodes ELT 1 and ELT 2 of the sub-pixel SPX may emit light having a luminance corresponding to the driving current.
  • FIGS. 9 A to 9 D are cross-sectional views schematically illustrating examples of the unit pixel, taken along line I-I′ of FIG. 8 .
  • FIGS. 9 A to 9 D each illustrates a sub-pixel area SPA (e.g., the first sub-pixel area SPA 1 ) formed in the display panel PNL.
  • the cross-sectional structures of the first, second, and third sub-pixels SPX 1 , SPX 2 , and SPX 3 described above and the first and second unit pixels SSPX 1 and SSPX 2 included therein may be substantially identical or similar to each other. Therefore, for the sake of explanation, as illustrated in FIGS.
  • a pixel circuit layer PCL and a display element layer LDL may be successively disposed in each sub-pixel area SPA of the base layer SUB 1 .
  • the pixel circuit layer PCL and the display element layer LDL may be formed in the entirety of the display area DA of the display panel PNL.
  • the pixel circuit layer PCL may include circuit elements which constitute the pixel circuits PXC of the sub-pixels SPX.
  • the display element layer LDL may include light emitting elements LD of the sub-pixels SPX (or the unit pixels SSPX).
  • the pixel circuit layer PCL may include circuit elements which are formed in the first sub-pixel area SPA 1 and form the pixel circuit PXC of the first sub-pixel SPX 1 (or the first unit pixel SSPX 1 ).
  • the pixel circuit layer PCL may include transistors disposed in the first sub-pixel area SPA 1 , e.g., the first and second transistors T 1 and T 2 of FIG. 6 A .
  • the pixel circuit layer PCL may include a storage capacitor Cst disposed in the sub-pixel area SPA, various signal lines (e.g., the scan line Si and the data line Dj illustrated in FIG.
  • various power lines e.g., a first power line (not illustrated) and a second power line PL configured to respectively transmit the first power supply VDD and the second power supply VSS
  • various power lines e.g., a first power line (not illustrated) and a second power line PL configured to respectively transmit the first power supply VDD and the second power supply VSS
  • transistors e.g., first and second transistors T 1 and T 2 , provided in the pixel circuit PXC may have substantially an identical or similar cross-sectional structure.
  • the disclosure is not limited thereto.
  • at least some of the transistors may have different types and/or structures.
  • the pixel circuit layer PCL may include insulating layers.
  • the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV which are successively stacked on the surface of the base layer SUB 1 .
  • the buffer layer BFL may prevent impurities from diffusing into the circuit elements.
  • the buffer layer BFL may be formed of a single layer, or may be formed of multiple layers having double or more layers. In case that the buffer layer BFL has a multi-layer structure, the respective layers may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.
  • each of the first and second transistors T 1 and T 2 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET 1 , and a second transistor electrode ET 2 .
  • FIG. 9 A illustrates that each of the first and second transistors T 1 and T 2 includes the first transistor electrode ET 1 and the second transistor electrode ET 2 that are formed separately from the semiconductor layer SCL, the disclosure is not limited thereto.
  • the first and/or second electrode ET 1 and/or ET 2 provided in at least one transistor disposed in each sub-pixel area SPA may be integral with the corresponding semiconductor layer SCL.
  • the semiconductor layer SCL may be disposed on the buffer layer BFL.
  • the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer SUB 1 on which the buffer layer BFL is formed.
  • the semiconductor layer SCL may include a first area which contacts a first transistor electrode ET 1 , a second area which contacts a second transistor electrode ET 2 , and a channel area disposed between the first and second areas.
  • one of the first and second areas may be a source area, and the other may be a drain area.
  • the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc.
  • the channel area of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern.
  • Each of the first and second areas of the semiconductor layer SCL may be a semiconductor pattern doped with a predetermined impurity.
  • the gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween.
  • the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one area of the semiconductor layer SCL.
  • the first and second transistor electrodes ET 1 and ET 2 may be disposed over the semiconductor layer SCL and the gate electrode GE with at least one interlayer insulating layer ILD interposed therebetween.
  • the first and second transistor electrodes ET 1 and ET 2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV.
  • the first and second transistor electrodes ET 1 and ET 2 may be electrically connected to the semiconductor layer SCL.
  • the first and second transistor electrodes ET 1 and ET 2 may be respectively connected to the first area and the second area of the semiconductor layer SCL through contact holes which pass through the gate insulating layer GI and the interlayer insulating layer ILD.
  • one of the first and second transistor electrodes ET 1 and ET 2 of at least one transistor may be electrically connected, through a third contact hole CH 3 passing through the passivation layer PSV, to the first electrode ELT 1 of the light source unit LSU disposed over the passivation layer PSV.
  • At least one signal line and/or at least one power line that is electrically connected to the sub-pixel SPX may be disposed on a layer identical with that of an electrode of each of the circuit elements that form the pixel circuit PXC.
  • the second power line PL for supplying the second power supply VSS may be disposed on a layer identical with that of the gate electrode GE of each of the first and second transistors T 1 and T 2 and electrically connected to the second electrode ELT 2 of the light source unit LSU that is disposed over the passivation layer PSV, both through the second connection electrode CNL 2 (or the second connection line, or a bridge pattern) disposed on the same layer as that of the first and second transistor electrodes ET 1 and ET 2 and through at least one second contact hole CH 2 passing through the passivation layer PSV.
  • the structures and/or positions of the second power line PL, etc. may be changed in various ways.
  • the display element layer LDL may include first and second partition walls PW 1 and PW 2 , first and second electrodes ELT 1 and LET 2 , a first insulating layer INS 1 , light emitting elements LD, a second insulating layer INS 2 , first and second contact electrodes CNE 1 and CNE 2 , and a third insulating layer INS 3 , which are successively disposed and/or formed on the pixel circuit layer PCL.
  • the first and second partition walls PW 1 and PW 2 may be disposed on the pixel circuit layer PCL.
  • the first and second partition walls PW 1 and PW 2 may be disposed at positions spaced apart from each other in the emission area EMA.
  • the first and second partition walls PW 1 and PW 2 may protrudes in a height direction on the pixel circuit layer PCL.
  • the first and second partition walls PW 1 and PW 2 may have substantially the same height, but the disclosure is not limited thereto.
  • the first partition wall PW 1 may be disposed between the pixel circuit layer PCL and the first electrode ELT 1 .
  • the first partition wall PW 1 may be disposed adjacent to the first ends EP 1 of the light emitting elements LD.
  • a sidewall of the first partition wall PW 1 may be positioned adjacent to the first ends EP 1 of the light emitting elements LD and disposed to face the first ends EP 1 .
  • the second partition wall PW 2 may be disposed between the pixel circuit layer PCL and the second electrode ELT 2 .
  • the second partition wall PW 2 may be disposed adjacent to the second ends EP 2 of the light emitting elements LD.
  • a sidewall of the second partition wall PW 2 may be positioned adjacent to the second ends EP 2 of the light emitting elements LD and be disposed to face the second ends EP 2 .
  • each of the first and second partition walls PW 1 and PW 2 may have various shapes.
  • each of the first and second partition walls PW 1 and PW 2 may have a cross-sectional shape of a trapezoid, a width of which reduces from a bottom to a top thereof.
  • each of the first and second partition walls PW 1 and PW 2 may have an inclined surface on at least one side thereof.
  • each of the first and second partition walls PW 1 and PW 2 may have a semicircular or a semielliptical cross-section, a width of which reduces from a bottom to a top thereof.
  • each of the first and second partition walls PW 1 and PW 2 may have a curved surface on at least one side thereof.
  • the shape of each of the first and second partition walls PW 1 and PW 2 is not limited to a particular shape, and may be changed in various ways.
  • at least one of the first and second partition walls PW 1 and PW 2 may be omitted, or the position thereof may be changed.
  • Each of the first and second partition walls PW 1 and PW 2 may include insulating material having inorganic material and/or organic material.
  • the first and second partition walls PW 1 and PW 2 may include at least one inorganic layer including various inorganic insulating materials such as SiN x and SiO x .
  • the first and second partition walls PW 1 and PW 2 may include at least one organic layer and/or at least one photoresist layer containing various organic insulating materials, or may form a single- or multi-layer insulator containing organic/inorganic materials in combination. In other words, the materials of the first and second partition walls PW 1 and PW 2 may be variously changed.
  • each of the first and second partition walls PW 1 and PW 21 may function as a reflective member.
  • the first and second partition walls PW 1 and PW 2 along with the first and second electrodes ELT 1 and ELT 2 provided on the first and second partition walls PW 1 and PW 2 , may function as reflectors that guide light, emitted from each light emitting element LD, in a desired direction, thereby enhancing the light efficiency of the pixel PXL.
  • the first and second electrodes ELT 1 and ELT 2 may be respectively disposed over the first and second partition walls PW 1 and PW 2 .
  • the first and second electrodes ELT 1 and ELT 2 may be disposed at positions spaced apart from each other in the emission area EMA.
  • the first and second electrodes ELT 1 and ELT 2 that are respectively disposed over the first and second partition walls PW 1 and PW 2 may have shapes corresponding to the respective shapes of the first and second partition walls PW 1 and PW 2 .
  • the first and second electrodes ELT 1 and ELT 2 may have inclined surfaces or curved surfaces corresponding to those of the first and second partition walls PW 1 and PW 2 , respectively, and protrude in a height direction (or a thickness direction) of the display element layer LDL.
  • Each of the first and second electrodes ELT 1 and ELT 2 may include at least one conductive material.
  • each of the first and second electrodes ELT 1 and ELT 2 may include at least one of metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof, conductive oxide such as ITO, IZO, ZnO, or ITZO, and a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT).
  • metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof, conductive oxide such as ITO, IZO, ZnO, or ITZO, and a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT).
  • PEDOT poly(3,4-ethylenedioxythiophene)
  • Each of the first and second electrodes ELT 1 and ELT 2 may have a single-layer or multi-layer structure.
  • each of the first and second electrodes ELT 1 and ELT 2 may include at least one reflective electrode layer.
  • Each of the first and second electrodes ELT 1 and ELT 2 may selectively further include at least one of at least one transparent electrode layer disposed on an upper portion and/or a lower portion of the reflective electrode layer, and at least one conductive capping layer covering (or overlapping) an upper portion of the reflective electrode layer and/or the transparent electrode layer.
  • the reflective electrode layer of each of the first and second electrodes ELT 1 and ELT 2 may be formed of conductive material having a uniform reflectivity.
  • the reflective electrode layer may include at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and an alloy thereof.
  • metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and an alloy thereof.
  • the disclosure is not limited thereto.
  • reflective electrode layer may be formed of various reflective conductive materials.
  • Each of the first and second electrodes ELT 1 and ELT 2 that include the reflective electrode layers may enable light emitted from the opposite ends of each of the light emitting elements LD, for example, the first and second ends EP 1 and EP 2 , to travel in a direction (e.g., in a frontal direction) in which an image is displayed.
  • first and second electrodes ELT 1 and ELT 2 respectively have inclined or curved surfaces corresponding to the shapes of the first and second partition walls PW 1 and PW 2 and are respectively disposed to face the first and second ends EP 1 and EP 2 of the light emitting elements LD, light emitted from the first and second ends EP 1 and EP 2 of each of the light emitting elements LD may be reflected by the first and second electrodes ELT 1 and ELT 2 and thus more reliably travel in the frontal direction of the display panel PNL (e.g., in an upward direction of the base layer SUB 1 ). Therefore, the efficiency of light emitted from the light emitting elements LD may be enhanced.
  • each of the first and second electrodes ELT 1 and ELT 2 may be formed of various transparent electrode materials.
  • the transparent electrode layer may include ITO, IZO, or ITZO, but the disclosure is not limited thereto.
  • each of the first and second electrodes ELT 1 and ELT 2 may have a triple-layer structure having a stacked structure of ITO/Ag/ITO. As such, if the first and second electrodes ELT 1 and ELT 2 each are formed of a multi-layer structure of double or more layers, voltage drop due to signal delay (RC delay) may be minimized. Thus, a desired voltage can be effectively transmitted to the light emitting elements LD.
  • RC delay signal delay
  • each of the first and second electrodes ELT 1 and ELT 2 includes the conductive capping layer covering (or overlapping) the reflective electrode layer and/or the transparent electrode layer, it is possible to prevent the reflective electrode layer or the like of the first and second electrodes ELT 1 and ELT 2 from being damaged by defects caused during the manufacturing process of the pixel PXL.
  • the conductive capping layer may be selectively included in the first and second electrodes ELT 1 and ELT 2 and may be omitted according to an embodiment.
  • the conductive capping layer may be considered as a component of each of the first and second electrodes ELT 1 and ELT 2 , or considered as a separate component disposed on the first and second electrodes ELT 1 and ELT 2 .
  • the first insulating layer INS 1 may be disposed on an area of each of the first and second electrodes ELT 1 and ELT 2 .
  • the first insulating layer INS 1 may be formed to cover (or overlap) predetermined areas of the first and second electrodes ELT 1 and ELT 2 and may include an opening to expose other predetermined areas of the first and second electrodes ELT 1 and ELT 2 .
  • the first insulating layer INS 1 may be primarily formed to cover (or overlap) the overall surfaces of the first and second electrodes ELT 1 and ELT 2 . After the light emitting elements LD are supplied and aligned on the first insulating layer INS 1 , the first insulating layer INS 1 may be partially open to expose the first and second electrodes ELT 1 and ELT 2 in the first and second contactors CNT 1 and CNT 2 , as illustrated in FIG. 9 A . As another example, the first insulating layer INS 1 may be patterned in the form of an individual pattern which is sectionally disposed under the light emitting elements LD after the supply and alignment of the light emitting elements LD have been completed.
  • the first insulating layer INS 1 may be interposed between the first and second electrodes ELT 1 and ELT 2 and the light emitting elements LD and may expose at least one area of each of the first and second electrodes ELT 1 and ELT 2 .
  • the first insulating layer INS 1 may be formed to cover (or overlap) the first and second electrodes ELT 1 and ELT 2 , so that it is possible to prevent the first and second electrodes ELT 1 and ELT 2 from being damaged or to prevent metal from being precipitated, in a subsequent process.
  • the first insulating layer INS 1 may stably support each light emitting element LD. In an embodiment, the first insulating layer INS 1 may be omitted.
  • the light emitting elements LD may be supplied onto and aligned in the emission area EMA in which the first insulating layer INS 1 is formed.
  • light emitting elements LD may be supplied to the emission area EMA by an inkjet method or the like, and the light emitting elements LD may be aligned between the first and second electrodes ELT 1 and ELT 2 by predetermined alignment voltages (or alignment signals) applied to the first and second electrodes ELT 1 and ELT 2 .
  • a bank BNK may be disposed on the first insulating layer INS 1 .
  • the bank BNK may be formed between other sub-pixels to enclose the emission area EMA of the sub-pixel SPX, so that a pixel defining layer for defining the emission area EMA of the sub-pixel SPX may be formed.
  • the bank BNK may be formed to have a second height greater than a first height of the first and second partition walls PW 1 and PW 2 .
  • the bank BNK in the step of supplying the light emitting elements LD to each emission area EMA, may function as a dam structure configured to prevent a solution mixed with the light emitting elements LD from being introduced into the emission area EMA of an adjacent sub-pixel SPX or control the amount of solution such that a constant amount of solution is supplied to each emission area EMA.
  • the bank BNK may be formed to prevent light emitted from each emission area EMA from entering an adjacent emission area EMA and causing optical interference. To this end, the bank BNK may be formed to prevent light emitted from the light emitting elements LD of each sub-pixel SPX from passing through the bank BNK.
  • the bank BNK may not be disposed between the first and second sub-emission areas EMA_S 1 and EMA_S 2 (refer to FIG. 7 ), but the disclosure is not limited thereto.
  • the second insulating layer INS 2 may be disposed over the light emitting elements LD aligned between the first and second electrodes ELT 1 and ELT 2 and may expose the first and second ends EP 1 and EP 2 of the light emitting elements LD.
  • the second insulating layer INS 2 may be partially disposed only over predetermined areas of the light emitting elements LD without covering (or overlapping) the first and second ends EP 1 and EP 2 of the light emitting elements LD.
  • the second insulating layer INS 2 may be formed in an independent pattern in each emission area EMA, but the disclosure is not limited thereto. Furthermore, as illustrated in FIG.
  • the space may be filled with the second insulating layer INS 2 . Therefore, the light emitting elements LD may be more stably supported.
  • the first and second contact electrodes CNE 1 and CNE 2 may be disposed on the first and second electrodes ELT 1 and ELT 2 and the first and second ends EP 1 and EP 2 of the light emitting elements LD. In an embodiment, the first and second contact electrodes CNE 1 and CNE 2 may be disposed on a same layer, as illustrated in FIG. 9 A . In this case, although the first and second contact electrodes CNE 1 and CNE 2 are formed by a same process using a same conductive material, the disclosure is not limited thereto.
  • the first and second contact electrodes CNE 1 and CNE 2 may respectively and electrically connect the first and second ends EP 1 and EP 2 of the light emitting elements LD to the first and second electrodes ELT 1 and ELT 2 .
  • the first contact electrode CNE 1 may be disposed on the first electrode ELT 1 to contact the first electrode ELT 1 .
  • the first contact electrode CNE 1 may be disposed to contact the first electrode ELT 1 in a predetermined area of the first electrode ELT 1 that is not covered (or overlapped) by the first insulating layer INS 1 .
  • the first contact electrode CNE 1 may be disposed on the first end EP 1 of at least one light emitting element adjacent to the first electrode ELT 1 , e.g., on the respective first ends EP 1 of light emitting elements LD, so that the first contact electrode CNE 1 can contact the first ends EP 1 .
  • the first contact electrode CNE 1 may be disposed to cover (or overlap) the first ends EP 1 of the light emitting elements LD and at least one area of the corresponding first electrode ELT 1 .
  • the first ends EP 1 of the light emitting elements LD may be electrically connected to the first electrode ELT 1 .
  • the second contact electrode CNE 2 may be disposed on the second electrode ELT 2 to contact the second electrode ELT 2 .
  • the second contact electrode CNE 2 may be disposed to contact the second electrode ELT 2 in a predetermined area of the second electrode ELT 2 that is not covered (or overlapped) by the first insulating layer INS 1 .
  • the second contact electrode CNE 2 may be disposed on the second end EP 2 of at least one light emitting element LD adjacent to the second electrode ELT 2 , e.g., on the second ends EP 2 of light emitting elements LD, so that the second contact electrode CNE 2 can contact the second ends EP 2 .
  • the second contact electrode CNE 2 may be disposed to cover the second ends EP 2 of the light emitting elements LD and at least one area of the corresponding second electrode ELT 2 .
  • the second ends EP 2 of the light emitting elements LD may be electrically connected to the second electrode ELT 2 .
  • the third insulating layer INS 3 may be formed and/or disposed on a surface of the base layer SUB 1 on which the first and second partition walls PW 1 and PW 2 , the first and second electrodes ELT 1 and ELT 2 , the light emitting elements LD, the first and second contact electrodes CNE 1 and CNE 2 , and the bank BNK are formed, so that the third insulating layer INS 3 may cover (or overlap) the first and second partition walls PW 1 and PW 2 , the first and second electrodes ELT 1 and ELT 2 , the light emitting elements LD, the first and second contact electrodes CNE 1 and CNE 2 , and the bank BNK.
  • the third insulating layer INS 3 may include a thin-film encapsulation layer including at least one inorganic layer and/or organic layer, but the disclosure is not limited thereto. In some embodiments, at least one overcoat layer, which is not illustrated, may be further disposed over the third insulating layer INS 3 .
  • each of the first to third insulating layers INS 1 , INS 2 , and INS 3 may have a single-layer or multi-layer structure, and include at least one inorganic insulating material and/or organic insulating material.
  • each of the first to third insulating layers INS 1 , INS 2 , and INS 3 may include various kinds of organic/inorganic insulating materials as well as SiNx, and the material of each of the first to third insulating layers INS 1 , INS 2 , and INS 3 is not particularly limited.
  • the first to third insulating layers INS 1 , INS 2 , and INS 3 may include different insulating materials, or at least some of the first to third insulating layers INS 1 , INS 2 , and INS 3 may include the same insulating material.
  • first and second contact electrodes CNE 1 and CNE 2 may be disposed on different layers.
  • the first contact electrode CNE 1 may be disposed in the sub-pixel area SPA in which the second insulating layer INS 2 is disposed.
  • the first contact electrode CNE 1 may be disposed on the first electrode ELT 1 disposed in the corresponding sub-pixel area SPA such that the first contact electrode CNE 1 contacts an area of the first electrode ELT 1 .
  • the first contact electrode CNE 1 may be disposed on the first end EP 1 of at least one light emitting element LD disposed in the corresponding sub-pixel area SPA such that that the first contact electrode CNE 1 contacts the first end EP 1 . Because of the first contact electrode CNE 1 , the first end EP 1 of at least one light emitting element LD disposed in the sub-pixel area SPA may be electrically connected to the first electrode ELT 1 disposed in the corresponding sub-pixel area SPA.
  • a fourth insulating layer INS 4 may be disposed in the sub-pixel area SPA in which the first contact electrode CNE 1 is disposed.
  • the fourth insulating layer INS 4 may cover (or overlap) the second insulating layer INS 2 and the first contact electrode CNE 1 that are disposed in the corresponding sub-pixel area SPA.
  • the fourth insulating layer INS 4 may have a single-layer or multi-layer structure, and include at least one inorganic insulating material and/or organic insulating material, in a manner similar to that of the first to third insulating layers INS 1 , INS 2 , and INS 3 .
  • the fourth insulating layer INS 4 may include various kinds of organic/inorganic insulating materials as well as SiN x .
  • the fourth insulating layer INS 4 may include insulating material different from that of the first to third insulating layers INS 1 , INS 2 , and INS 3 , or the fourth insulating layer INS 4 and at least some of the first to third insulating layers INS 1 , INS 2 , and INS 3 may include the same insulating material.
  • the second contact electrode CNE 2 may be disposed in each sub-pixel area SPA in which the fourth insulating layer INS 4 is disposed.
  • the second contact electrode CNE 2 may be disposed on the second electrode ELT 2 disposed in the corresponding sub-pixel area SPA such that the second contact electrode CNE 2 contacts an area of the second electrode ELT 2 .
  • the second contact electrode CNE 2 may be disposed on the second end EP 2 of at least one light emitting element LD disposed in the corresponding sub-pixel area SPA such that that the second contact electrode CNE 2 contacts the second end EP 2 .
  • the second contact electrode CNE 2 may electrically connect the second end EP 2 of at least one light emitting element LD disposed in each sub-pixel area SPA to the second electrode ELT 2 disposed in the corresponding sub-pixel area SPA.
  • each of the first and second partition walls PW 1 and PW 2 may have various shapes.
  • each of the first and second partition walls PW 1 and PW 2 may have a cross-sectional shape of a trapezoid, a width of which reduces from a bottom to a top thereof.
  • each of the first and second partition walls PW 1 and PW 2 may have a semicircular or a semielliptical cross-section, a width of which reduces from a bottom to a top thereof.
  • FIGS. 10 A and 10 B are plan views schematically illustrating other examples of a sub-pixel included in the display device of FIG. 4 .
  • FIGS. 10 A and 10 B illustrate the structure of first to third sub-pixels SPX 1 to SPX 3 , focusing on a light source unit LSU (refer to FIGS. 6 A to 6 D ) (or a light emitting element layer) included in the first to third sub-pixels SPX 1 to SPX 3 . Since the first to third sub-pixels SPX 1 to SPX 3 are substantially equal to each other, the light source unit LSU will be described, focusing on the first sub-pixel SPX 1 .
  • LSU light source unit
  • the first sub-pixel SPX 1 of FIG. 10 A may be substantially the same as the first sub-pixel SPX 1 of FIG. 7 . Therefore, repetitive descriptions thereof will be omitted.
  • the emission area EMA may include a first sub-emission area EMA_S 1 and a second sub-emission area EMA_S 2 which are spaced apart from each other in the first direction DR 1 based on a reference line L_REF.
  • the bank BNK described with reference to FIG. 9 A may be disposed along the reference line L_REF between the first and second sub-emission areas EMA_S 1 and EMA_S 2 .
  • the bank BNK may also be disposed between the first electrodes ELT 1 , in a plan view.
  • the first sub-pixel SPX 1 of FIG. 10 B may be substantially the same as the first sub-pixel SPX 1 of FIG. 7 . Therefore, repetitive descriptions thereof will be omitted.
  • the emission area EMA may include first to third sub-emission areas EMA_S 1 , EMA_S 2 , and EMA_S 3 which are separated from each other in the second direction DR 2 based on the second electrodes ELT 2 , rather than being based on the reference line L_REF.
  • the first to third sub-emission areas EMA_S 1 , EMA_S 2 , and EMA_S 3 may be adjacent to each other, and a separate bank may not be disposed therebetween.
  • the first electrodes ELT 1 may have a length (for example, a length in the first direction DR 1 ) similar to that of the second electrodes ELT 2 and extend in the first direction DR 1 . Furthermore, the first electrodes ELT 1 may be electrically separated or insulated from each other. In this case, each of the first electrodes ELT 1 may be electrically connected, through the first contact hole CH 1 , to a corresponding pixel circuit (e.g., the pixel circuit PXC described with reference to FIG. 6 A as a pixel circuit PXC of the first to third unit pixels SSPX 1 , SSPX 2 , and SSPX 3 ).
  • a pixel circuit e.g., the pixel circuit PXC described with reference to FIG. 6 A as a pixel circuit PXC of the first to third unit pixels SSPX 1 , SSPX 2 , and SSPX 3 ).
  • the second connection electrode CNL 2 may extend in the second direction DR 2 and also be disposed in other adjacent sub-pixels (e.g., the second and third sub-pixels SPX 2 and SPX 3 ), but the disclosure is not limited thereto.
  • the first to third sub-emission areas EMA_S 1 , EMA_S 2 , and EMA_S 3 in the emission area EMA may be set or defined in various ways.
  • FIG. 11 is a circuit diagram schematically illustrating an example of a sub-pixel included in the pixel of FIG. 4 .
  • the first to third sub-pixels SPX 1 to SPX 3 shown in FIG. 4 may have a substantially identical or similar structure.
  • a sub-pixel SPX shown in FIG. 11 may be one of the first to third sub-pixels SPX 1 to SPX 3 provided in the display panel PNL of FIG. 4 . Therefore, as illustrated in FIG. 11 , the first to third sub-pixels SPX 1 to SPX 3 will be collectively referred to as a sub-pixel SPX.
  • the sub-pixel SPX may include first to k-th light emitting elements LD 1 to LDk configured to emit light having a luminance corresponding to a data signal. Furthermore, the sub-pixel SPX may include a common circuit PX_C and first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk configured to independently drive the respective first to k-th light emitting elements LD 1 to LDk.
  • the common circuit PX_C of the sub-pixel SPX may store or record a data signal provided from the data line Dj in response to a scan signal provided from the scan line Si and provide the data signal to the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk.
  • the common circuit PX_C may include second to fifth transistors T 2 to T 5 and a storage capacitor Cst. Since the second to fifth transistors T 2 to T 5 and the storage capacitor Cst are respectively substantially equal to the second to fifth transistors T 2 to T 5 and the storage capacitor Cst described with reference to FIG. 6 C , repetitive descriptions thereof will be omitted.
  • the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk may provide driving current, corresponding to the data signal stored in the common circuit PXC_C, to the first to k-th light emitting elements LD 1 to LDk, respectively.
  • the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk may include first transistors T 1 _ 1 to T 1 _k, sixth transistors T 6 _ 1 to T 6 _k and seventh transistors T 7 _ 1 to T 7 _k, which correspond to the first transistor T 1 , the sixth transistor T 6 , and the seventh transistor T 7 that are described with reference to FIG. 6 A .
  • the first sub-pixel circuit PXC_S 1 may include a first transistor T 1 _ 1 , a sixth transistor T 6 _ 1 , and a seventh transistor T 7 _ 1 , and provide first driving current corresponding to a data signal to the first light emitting element LD 1 .
  • the first transistor T 1 _ 1 , the sixth transistor T 6 _ 1 , and the seventh transistor T 7 _ 1 may be respectively substantially identical with the first transistor T 1 , the sixth transistor T 6 , and the seventh transistor T 7 that are described with reference to FIG. 6 A , so that repetitive descriptions thereof will be omitted.
  • the second sub-pixel circuit PXC_S 2 may include a first transistor T 1 _ 2 , a sixth transistor T 6 _ 2 , and a seventh transistor T 7 _ 2 and provide second driving current, corresponding to a data signal, to the second light emitting element LD 2 .
  • the k-th sub-pixel circuit PXC_Sk may include a first transistor T 1 _k, a sixth transistor T 6 _k, and a seventh transistor T 7 _k and provide k-th driving current, corresponding to a data signal, to the k-th light emitting element LDk.
  • the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk may have the same circuit structure and respectively and independently provide driving currents, corresponding to a data signal stored in the common circuit PXC_C, to the first to k-th light emitting elements LD 1 to LDk.
  • total driving current may be provided from the first power supply VDD to a first node N 1 through the fifth transistor T 5 .
  • the total driving current may be distributed to the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk, and the distributed driving currents may be respectively provided to the first to k-th light emitting elements LD 1 to LDk.
  • driving current that flows through each of the first to k-th light emitting elements LD 1 to LDk is controlled by the respective first transistors T 1 _ 1 to T 1 _k of each of the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk regardless of characteristics of each of the first to k-th light emitting elements LD 1 to LDk, uniform driving current may be provided to each of the first to k-th light emitting elements LD 1 to LDk.
  • the driving currents are independently provided to the first to k-th light emitting elements LD 1 to LDk. Therefore, even in case that the first to k-th light emitting elements LD 1 to LDk have a characteristic deviation (e.g., a forward voltage drop (Vf) deviation), identical or similar driving currents may be respectively provided to the first to k-th light emitting elements LD 1 to LDk. Therefore, the first to k-th light emitting elements LD 1 to LDk may uniformly emit light.
  • Vf forward voltage drop
  • FIG. 11 illustrates that the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk are respectively electrically connected to the first to k-th light emitting elements LD 1 to LDk, this is only an example for describing an embodiment where the first to k-th light emitting elements LD 1 to LDk can emit light independently from each other, and the sub-pixel SPX is not limited thereto.
  • each of the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk may be electrically connected to light emitting elements (e.g., the light source unit LSU described with reference to FIGS. 6 A to 6 D ) which are electrically connected in serial/parallel to each other.
  • light emitting elements e.g., the light source unit LSU described with reference to FIGS. 6 A to 6 D
  • FIG. 11 illustrates that the sub-pixel SPX include the common circuit PX_C and the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk
  • the sub-pixel SPX is not limited thereto.
  • the common circuit PX_C and the first sub-pixel circuit PXC_S 1 may form a pixel circuit (e.g., the pixel circuit PXC described with reference to FIG. 6 C ) and provide first driving current to the first light emitting element LD 1 .
  • Each of the second to k-th sub-pixel circuits PXC_S 2 to PXC_Sk may mirror the first driving current and provide the mirrored current to each of the second to k-th light emitting elements LD 2 to LDk.
  • FIG. 12 is a circuit diagram schematically illustrating an example of a sub-pixel included in the pixel of FIG. 4 .
  • a common circuit PX_C shown in FIG. 12 is different from the common circuit PXC_C shown in FIG. 11 at least in that the common circuit PXC_C of FIG. 12 includes only the second and fifth transistors T 2 and T 5 .
  • first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk shown in FIG. 12 are different from those of FIG. 11 at least in that each of the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk of FIG. 12 includes third and fourth transistors T 3 and T 4 and a storage capacitor Cst.
  • the first transistors T 1 for the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk may have a characteristic deviation (e.g., a threshold voltage deviation). Therefore, some of driving currents generated from the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk in response to a data signal VDATA (e.g., the data signal stored in the storage capacitor Cst shown in FIG. 11 ) may have a deviation.
  • VDATA e.g., the data signal stored in the storage capacitor Cst shown in FIG. 11
  • each of the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk illustrated in FIG. 12 may store, in the storage capacitor Cst, a data signal that reflects characteristics of the corresponding first transistor T 1 , and provide driving current corresponding to the associated data signal to the corresponding light emitting element (for example, the corresponding light emitting element of the first to k-th light emitting elements LD 1 to LDk). Therefore, the first to k-th light emitting elements LD 1 to LDk may more uniformly emit light.
  • FIG. 13 is a circuit diagram schematically illustrating an example of a sub-pixel included in the pixel of FIG. 4 .
  • the sub-pixel SPX may include first to k-th light emitting elements LD 1 to LDk configured to emit light having a luminance corresponding to a data signal. Furthermore, the sub-pixel SPX may include a common circuit PX_C and first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk configured to independently drive the respective first to k-th light emitting elements LD 1 to LDk.
  • the common circuit PX_C of the sub-pixel SPX may provide, to the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk, a data signal provided from the data line Dj in response to a scan signal provided from the first scan line S 1 .
  • the common circuit PX_C may include a second transistor T 2 .
  • the second transistor T 2 is substantially identical with the second transistor T 2 described with reference to FIG. 6 D , so that repetitive descriptions thereof will be omitted.
  • Each of the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk may store a data signal provided from the common circuit PX_C and provide driving current corresponding to the stored data signal to the corresponding light emitting element (for example, one of the first to k-th light emitting elements LD 1 to LDk).
  • the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk may include first transistors T 1 _ 1 to T 1 _k, third transistors T 3 _ 1 to T 3 _k and storage capacitors Cst_ 1 to Cst_k, which correspond to the first transistor T 1 , the third transistor T 3 , and the storage capacitor Cst that are described with reference to FIG. 6 D .
  • the first sub-pixel circuit PXC_S 1 may include a first transistor T 1 _ 1 , a third transistor T 3 _ 1 , and a first storage capacitor Cst 1 and provide first driving current, corresponding to a data signal, to the first light emitting element LD 1 .
  • the first transistor T 1 _ 1 , the third transistor T 3 _ 1 , and the first storage capacitor Cst 1 may be respectively substantially identical with the first transistor T 1 , the third transistor T 3 , and the storage capacitor Cst that are described with reference to FIG. 6 A , so that repetitive descriptions thereof will be omitted.
  • the second sub-pixel circuit PXC_S 2 may include a first transistor T 1 _ 2 , a third transistor T 3 _ 2 , and a second storage capacitor Cst 2 and provide second driving current, corresponding to a data signal, to the second light emitting element LD 2 .
  • the k-th sub-pixel circuit PXC_Sk may include a first transistor T 1 _k, a third transistor T 3 _k, and a k-th storage capacitor Cstk and provide k-th driving current, corresponding to a data signal, to the k-th light emitting element LDk.
  • each of the first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk illustrated in FIG. 13 may store a data signal in the first to k-th storage capacitors Cst 1 to Cstk and provide driving current corresponding to the associated data signal to the corresponding light emitting element (for example, the corresponding light emitting element of the first to k-th light emitting elements LD 1 to LDk). Therefore, the first to k-th light emitting elements LD 1 to LDk may more uniformly emit light.
  • FIG. 14 is a circuit diagram schematically illustrating an example of a sub-pixel included in the pixel of FIG. 4 .
  • FIG. 15 is a plan view schematically illustrating an example of a sub-pixel of FIG. 14 .
  • the sub-pixel SPX of FIG. 14 is different from the sub-pixel SPX of FIG. 13 at least in that first to k-th sub-pixel circuits PXC_S 1 to PXC_Sk are respectively connected to first to k-th light emitting element strings LDS 1 to LDSk (or light source units) including light emitting elements electrically connected in series to each other.
  • the sub-pixel SPX of FIG. 14 except the first to k-th light emitting element strings LDS 1 to LDSk, is substantially identical or similar to the sub-pixel SPX of FIG. 13 , so that repetitive descriptions thereof will be omitted.
  • the first sub-pixel circuit PXC_S 1 may provide, to the first light emitting element string LDS 1 (or a first sub-light source unit), first driving current corresponding to a data signal provided from the common circuit PXC_C.
  • the second sub-pixel circuit PXC_S 2 may provide, to a second light emitting element string LDS 2 , second driving current corresponding to a data signal provided from the common circuit PXC_C.
  • the k-th sub-pixel circuit PXC_Sk may provide, to a k-th light emitting element string LDSk, k-th driving current corresponding to a data signal provided from the common circuit PXC_C.
  • FIG. 15 there is illustrated in FIG. 15 structures of the first to third sub-pixels SPX 1 to SPX 3 , focusing on the first to k-th light emitting element strings LDS 1 to LDSk (or a light emitting element layer) included in the sub-pixel SPX of FIG. 14 .
  • FIG. 15 illustrates that the sub-pixel SPX includes three light emitting element strings (for example, first to k-th light emitting element strings, where k is equal to 3), and each of the light emitting element strings includes fourth light emitting elements LD electrically connected in series to each other.
  • the emission area EMA may be divided into first to third sub-emission areas EMA_S 1 , EMA_S 2 , and EMA_S 3 by first and second reference lines L_REF 1 and L_REF 2 .
  • the arrangement of the light emitting elements LD in the first to third sub-emission areas EMA_S 1 , EMA_S 2 , and EMA_S 3 are substantially identical or similar to each other, so that the arrangement of the light emitting elements LD will be described, focusing on the first sub-emission area EMA_S 1 .
  • the first sub-pixel SPX 1 (or the first unit pixel SSPX 1 corresponding to the first sub-emission area EMA_S 1 ) may include a first electrode ELT 1 and a second electrode ELT 2 disposed in the emission area EMA (or the sub-pixel area) at positions spaced apart from each other, and third electrodes ELT 3 arranged between the first electrode ELT 1 and the second electrode ELT 2 .
  • the first-sub pixel SPX 1 (or the first unit pixel SSPX 1 ) may include light emitting elements LD electrically connected in series between the first and second electrodes ELT 1 and ELT 2 through the third electrodes ELT 3 .
  • the first electrode ELT 1 and the second electrode ELT 2 may be disposed at positions spaced apart from each other in the emission area EMA (or the sub-pixel area) such that at least predetermined areas thereof face each other.
  • the first and second electrodes ELT 1 and ELT 2 each may extend in the first direction DR 1 and may be spaced apart from each other by a predetermined distance in the second direction DR 2 that is substantially perpendicular to or intersects the first direction DR 1 .
  • the disclosure is not limited thereto.
  • the shapes and/or mutual arrangement relationship of the first and second electrodes ELT 1 and ELT 2 may be changed in various ways.
  • the third electrodes ELT 3 may extend in the first direction DR 1 and be disposed at regular intervals in the second direction DR 2 between the first and second electrodes ELT 1 and ELT 2 .
  • the third electrodes ELT 3 may be disposed at regular intervals in the second direction DR 2 between the first and second electrodes ELT 1 and ELT 2 , but the disclosure is not limited thereto.
  • the number of third electrodes ELT 3 may be changed in various ways.
  • the first electrode ELT 1 may be disposed in each of the first to third sub-emission areas EMA_S 1 , EMA_S 2 , and EMA_S 3 .
  • the second electrode ELT 2 may be disposed in the entirety of the emission area EMA, for example, across the sub-emission areas.
  • the third electrode ELT 3 may be disposed between the first and second electrodes ELT 1 and ELT 2 in the corresponding sub-emission area (e.g., in the first sub-emission area EMA_S 1 ).
  • the first electrode ELT 1 may be integral with a third electrode ELT 3 .
  • Each of the first to third electrodes ELT 1 , ELT 2 , and ELT 3 may have a single layer structure or a multi-layer structure, as described with reference to FIG. 7 . Furthermore, each of the first to third electrodes ELT 1 , ELT 2 , and ELT 3 may protrude in an upward direction (or a height direction or a thickness direction of the base layer SUB 1 ) by a partition wall that is disposed to overlap the corresponding electrode.
  • the light emitting elements LD each may be disposed between two adjacent electrodes of the first to third electrodes ELT 1 to ELT 3 and be electrically connected to the two adjacent electrodes.
  • a light emitting element LD may be disposed between the first electrode ELT 1 and a first sub-electrode (for example, a third electrode ELT 3 closest to the first electrode ELT 1 among the third electrodes ELT 3 ).
  • the first end of the light emitting element LD may be electrically connected to the first electrode ELT 1
  • the second end of the light emitting element LD may be electrically connected to the first sub-electrode.
  • a light emitting element LD may be disposed between the second electrode ELT 2 and the second sub-electrode (for example, a third electrode ELT 3 closest to the second electrode ELT 2 among the third electrodes ELT 3 ).
  • the first end of the light emitting element LD may be electrically connected to the second sub-electrode, and the second end of the light emitting element LD may be electrically connected to the second electrode ELT 2 .
  • the light emitting elements LD in the first sub-emission area EMA_S 1 may be electrically connected in series between the first and second electrodes ELT 1 and ELT 2 .
  • FIG. 15 illustrates that the light emitting elements LD are electrically connected in series in a sub-emission area (e.g., the first sub-emission area EMA_S 1 ), the light emitting elements LD are not limited thereto.
  • the sub-emission area at least some of the light emitting elements LD may be electrically connected in parallel to other light emitting elements LD.
  • the light emitting elements LD in the sub-emission area may be arranged in a serial/parallel combined connection structure.
  • the light emitting elements LD shown in FIG. 15 have been described as being applied to the sub-pixel SPX of FIG. 14 , the disclosure is not limited thereto.
  • the light emitting elements LD (or the connection structure of the light emitting elements LD) shown in FIG. 15 may be applied to the sub-pixel SPX of FIG. 11 , the sub-pixel SPX of FIG. 12 , etc.

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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200105598A (ko) * 2019-02-28 2020-09-08 삼성디스플레이 주식회사 표시 장치
KR20210044938A (ko) 2019-10-15 2021-04-26 삼성디스플레이 주식회사 표시 장치
KR20210059075A (ko) 2019-11-13 2021-05-25 삼성디스플레이 주식회사 표시 장치
KR20210095266A (ko) * 2020-01-22 2021-08-02 삼성디스플레이 주식회사 발광 소자 및 이를 포함하는 표시 장치
KR20210106053A (ko) * 2020-02-19 2021-08-30 삼성디스플레이 주식회사 표시 장치
KR20220033662A (ko) * 2020-09-09 2022-03-17 삼성디스플레이 주식회사 표시 장치의 제조 방법 및 그에 의해 제조된 표시 장치
KR20220049685A (ko) * 2020-10-14 2022-04-22 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
KR20220063871A (ko) * 2020-11-10 2022-05-18 삼성디스플레이 주식회사 표시 장치
KR20220067647A (ko) * 2020-11-17 2022-05-25 삼성디스플레이 주식회사 표시 장치
KR20220078798A (ko) * 2020-12-03 2022-06-13 삼성디스플레이 주식회사 화소 및 이를 포함한 표시 장치
KR20220091703A (ko) 2020-12-23 2022-07-01 삼성디스플레이 주식회사 표시 장치
KR20220109538A (ko) * 2021-01-28 2022-08-05 삼성디스플레이 주식회사 표시 장치
KR20220121276A (ko) * 2021-02-24 2022-09-01 삼성디스플레이 주식회사 표시 장치
KR20220125862A (ko) * 2021-03-04 2022-09-15 삼성디스플레이 주식회사 표시 장치
KR20220127431A (ko) 2021-03-10 2022-09-20 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치

Citations (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010019963A (ja) 2008-07-09 2010-01-28 Sony Corp 表示装置
US7777701B2 (en) * 2004-08-30 2010-08-17 Samsung Mobile Display Co., Ltd. Signal driving method and apparatus for a light emitting display
US20110089850A1 (en) 2009-10-15 2011-04-21 Sharp Kabushiki Kaisha Light emitting device and manufacturing method therefor
US20110109612A1 (en) 2009-11-12 2011-05-12 Ignis Innovation Inc. Sharing switch tfts in pixel circuits
US8076674B2 (en) * 2004-05-24 2011-12-13 Samsung Mobile Display Co., Ltd. Display device
US8111224B2 (en) * 2004-08-26 2012-02-07 Samsung Mobile Display Co., Ltd. Organic light emitting diode display and display panel and driving method thereof
KR101244926B1 (ko) 2011-04-28 2013-03-18 피에스아이 주식회사 초소형 ｌｅｄ 소자 및 그 제조방법
CN103000131A (zh) 2012-12-05 2013-03-27 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板及显示装置
US8872214B2 (en) 2009-10-19 2014-10-28 Sharp Kabushiki Kaisha Rod-like light-emitting device, method of manufacturing rod-like light-emitting device, backlight, illuminating device, and display device
KR101490758B1 (ko) 2013-07-09 2015-02-06 피에스아이 주식회사 초소형 led 전극어셈블리 및 이의 제조방법
US20160012799A1 (en) 2014-07-09 2016-01-14 Samsung Display Co., Ltd. Pixel, pixel driving method, and display device comprising the pixel
US20160155379A1 (en) * 2014-12-02 2016-06-02 Samsung Display Co., Ltd. Organic light emitting display and driving method of the same
US20170076646A1 (en) 2015-09-16 2017-03-16 Samsung Display Co., Ltd. Pixel, organic light emitting display device including the pixel, and method of driving the pixel
KR20170050371A (ko) 2015-10-30 2017-05-11 엘지디스플레이 주식회사 표시 장치
US20170200412A1 (en) 2016-01-13 2017-07-13 Shanghai Jing Peng Invest Management Co., Ltd. Display device and pixel circuit thereof
US20180033830A1 (en) * 2016-07-29 2018-02-01 Samsung Display Co., Ltd. Display device
US20180175009A1 (en) * 2016-12-21 2018-06-21 Samsung Display Co., Ltd. Light emitting device and display device including the same
US20180198018A1 (en) * 2017-01-09 2018-07-12 Samsung Display Co., Ltd. Light emitting device and manufacturing method of the same
US20190073963A1 (en) * 2014-07-17 2019-03-07 Boe Technology Group Co., Ltd. Pixel circuit and display apparatus
US20190172761A1 (en) * 2017-12-04 2019-06-06 Au Optronics Corporation Pixel structure
US10424250B2 (en) * 2017-10-10 2019-09-24 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. AMOLED display device and driving method thereof
US20200013766A1 (en) * 2018-07-05 2020-01-09 Samsung Display Co., Ltd. Light emitting display device and method of fabricating the same
WO2020230989A1 (fr) * 2019-05-10 2020-11-19 삼성디스플레이 주식회사 Dispositif d'affichage et son procédé de fabrication
US10977990B2 (en) * 2018-06-20 2021-04-13 Samsung Electronics Co., Ltd. Pixel and organic light emitting display device comprising the same
US20210217739A1 (en) * 2018-09-03 2021-07-15 Samsung Display Co., Ltd. Light-emitting device and display device including same
US20210320231A1 (en) * 2018-07-30 2021-10-14 Samsung Display Co., Ltd. Light-emitting device and display device comprising same
US20210335230A1 (en) * 2018-01-10 2021-10-28 Chengdu Boe Optoelectronics Technology Co., Ltd. A pixel driving circuit with wide range input voltage
US20210335168A1 (en) * 2018-08-30 2021-10-28 Samsung Display Co., Ltd. Pixel and display device comprising same
US20210358408A1 (en) * 2018-06-26 2021-11-18 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit and method, display panel
US20210390902A1 (en) * 2018-10-08 2021-12-16 Samsung Display Co., Ltd. Pixel, display device having same and driving method thereof
US11217161B2 (en) * 2018-09-20 2022-01-04 Boe Technology Group Co., Ltd. Display-driving circuit, method, and display apparatus
US20220139319A1 (en) * 2019-02-28 2022-05-05 Samsung Display Co., Ltd. Display device
US11361710B2 (en) * 2018-09-20 2022-06-14 Boe Technology Group Co., Ltd. Pixel circuit with a time-shared signal line, a pixel compensation method, and a display apparatus
US11367394B2 (en) * 2018-07-30 2022-06-21 Sharp Kabushiki Kaisha Display device
US11403997B2 (en) * 2018-10-12 2022-08-02 Samsung Display Co., Ltd. Pixel and display apparatus including same
US20230005987A1 (en) * 2019-12-11 2023-01-05 Samsung Display Co., Ltd. Display device and method for manufacturing same
US20230013528A1 (en) * 2021-07-19 2023-01-19 Samsung Display Co., Ltd. Display device and method of driving the same

Patent Citations (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8076674B2 (en) * 2004-05-24 2011-12-13 Samsung Mobile Display Co., Ltd. Display device
US8111224B2 (en) * 2004-08-26 2012-02-07 Samsung Mobile Display Co., Ltd. Organic light emitting diode display and display panel and driving method thereof
US7777701B2 (en) * 2004-08-30 2010-08-17 Samsung Mobile Display Co., Ltd. Signal driving method and apparatus for a light emitting display
JP2010019963A (ja) 2008-07-09 2010-01-28 Sony Corp 表示装置
US20110089850A1 (en) 2009-10-15 2011-04-21 Sharp Kabushiki Kaisha Light emitting device and manufacturing method therefor
US8872214B2 (en) 2009-10-19 2014-10-28 Sharp Kabushiki Kaisha Rod-like light-emitting device, method of manufacturing rod-like light-emitting device, backlight, illuminating device, and display device
US20110109612A1 (en) 2009-11-12 2011-05-12 Ignis Innovation Inc. Sharing switch tfts in pixel circuits
US9112112B2 (en) 2011-04-28 2015-08-18 Psi Co., Ltd. Subminiature led element and manufacturing method thereof
KR101244926B1 (ko) 2011-04-28 2013-03-18 피에스아이 주식회사 초소형 ｌｅｄ 소자 및 그 제조방법
CN103000131A (zh) 2012-12-05 2013-03-27 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板及显示装置
US9773761B2 (en) 2013-07-09 2017-09-26 Psi Co., Ltd Ultra-small LED electrode assembly and method for manufacturing same
KR101490758B1 (ko) 2013-07-09 2015-02-06 피에스아이 주식회사 초소형 led 전극어셈블리 및 이의 제조방법
US20160012799A1 (en) 2014-07-09 2016-01-14 Samsung Display Co., Ltd. Pixel, pixel driving method, and display device comprising the pixel
KR20160007900A (ko) 2014-07-09 2016-01-21 삼성디스플레이 주식회사 화소, 화소 구동 방법, 및 화소를 포함하는 표시 장치
US9460691B2 (en) 2014-07-09 2016-10-04 Samsung Display Co., Ltd. Pixel, pixel driving method, and display device comprising the pixel
US20190073963A1 (en) * 2014-07-17 2019-03-07 Boe Technology Group Co., Ltd. Pixel circuit and display apparatus
KR20160066595A (ko) 2014-12-02 2016-06-13 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 구동 방법
US10388214B2 (en) 2014-12-02 2019-08-20 Samsung Display Co., Ltd. Organic light emitting display and driving method of the same
US20160155379A1 (en) * 2014-12-02 2016-06-02 Samsung Display Co., Ltd. Organic light emitting display and driving method of the same
US20170076646A1 (en) 2015-09-16 2017-03-16 Samsung Display Co., Ltd. Pixel, organic light emitting display device including the pixel, and method of driving the pixel
KR20170050371A (ko) 2015-10-30 2017-05-11 엘지디스플레이 주식회사 표시 장치
US20170200412A1 (en) 2016-01-13 2017-07-13 Shanghai Jing Peng Invest Management Co., Ltd. Display device and pixel circuit thereof
US20180033830A1 (en) * 2016-07-29 2018-02-01 Samsung Display Co., Ltd. Display device
KR20180072909A (ko) 2016-12-21 2018-07-02 삼성디스플레이 주식회사 발광 장치 및 이를 구비한 표시 장치
US20180175009A1 (en) * 2016-12-21 2018-06-21 Samsung Display Co., Ltd. Light emitting device and display device including the same
US10461123B2 (en) 2016-12-21 2019-10-29 Samsung Display Co., Ltd. Light emitting device and display device including the same
US20180198018A1 (en) * 2017-01-09 2018-07-12 Samsung Display Co., Ltd. Light emitting device and manufacturing method of the same
US10424250B2 (en) * 2017-10-10 2019-09-24 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. AMOLED display device and driving method thereof
US20190172761A1 (en) * 2017-12-04 2019-06-06 Au Optronics Corporation Pixel structure
US20210335230A1 (en) * 2018-01-10 2021-10-28 Chengdu Boe Optoelectronics Technology Co., Ltd. A pixel driving circuit with wide range input voltage
US10977990B2 (en) * 2018-06-20 2021-04-13 Samsung Electronics Co., Ltd. Pixel and organic light emitting display device comprising the same
US20210358408A1 (en) * 2018-06-26 2021-11-18 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit and method, display panel
US20200013766A1 (en) * 2018-07-05 2020-01-09 Samsung Display Co., Ltd. Light emitting display device and method of fabricating the same
US20210305225A1 (en) * 2018-07-05 2021-09-30 Samsung Display Co., Ltd. Light emitting display device and method of fabricating the same
US20210320231A1 (en) * 2018-07-30 2021-10-14 Samsung Display Co., Ltd. Light-emitting device and display device comprising same
US11367394B2 (en) * 2018-07-30 2022-06-21 Sharp Kabushiki Kaisha Display device
US20210335168A1 (en) * 2018-08-30 2021-10-28 Samsung Display Co., Ltd. Pixel and display device comprising same
US20210217739A1 (en) * 2018-09-03 2021-07-15 Samsung Display Co., Ltd. Light-emitting device and display device including same
US11217161B2 (en) * 2018-09-20 2022-01-04 Boe Technology Group Co., Ltd. Display-driving circuit, method, and display apparatus
US11361710B2 (en) * 2018-09-20 2022-06-14 Boe Technology Group Co., Ltd. Pixel circuit with a time-shared signal line, a pixel compensation method, and a display apparatus
US20210390902A1 (en) * 2018-10-08 2021-12-16 Samsung Display Co., Ltd. Pixel, display device having same and driving method thereof
US20230049527A1 (en) * 2018-10-08 2023-02-16 Samsung Display Co., Ltd. Pixel, display device having same and driving method thereof
US11403997B2 (en) * 2018-10-12 2022-08-02 Samsung Display Co., Ltd. Pixel and display apparatus including same
US20220139319A1 (en) * 2019-02-28 2022-05-05 Samsung Display Co., Ltd. Display device
WO2020230989A1 (fr) * 2019-05-10 2020-11-19 삼성디스플레이 주식회사 Dispositif d'affichage et son procédé de fabrication
US20230005987A1 (en) * 2019-12-11 2023-01-05 Samsung Display Co., Ltd. Display device and method for manufacturing same
US20230013528A1 (en) * 2021-07-19 2023-01-19 Samsung Display Co., Ltd. Display device and method of driving the same

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
"LED Design Forum: Avoiding thermal runaway when driving multiple LED strings (Magazine)", LEDs Magazine, Apr. 20, 2009, https://www.ledsmagazine.com/articles/print/volume-6/issue-2/features/led-design-forum-avoiding-thermal-runaway-when-driving-multiple-led-strings-magazine.html.
Extended European search report for European Patent Application or Patent No. 19916942.6, dated Sep. 30, 2022.
International Search Report, with English translation, corresponding to International Application No. PCT/KR2019/018712 dated Apr. 8, 2020.
Muhinthan Murugesu, "Current distribution in parallel LED strings", Articles: Vector, Oct. 14, 2015, EE publishers, http://www.ee.co.za/article/current-distribution-parallel-led-strings.html.
Written Opinion, with English translation, corresponding to International Application No. PCT/KR2019/018712, dated Apr. 8, 2020.

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