US11683010B2 - Oscillation circuit - Google Patents

Oscillation circuit Download PDF

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Publication number
US11683010B2
US11683010B2 US17/870,856 US202217870856A US11683010B2 US 11683010 B2 US11683010 B2 US 11683010B2 US 202217870856 A US202217870856 A US 202217870856A US 11683010 B2 US11683010 B2 US 11683010B2
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circuit
mos transistor
port
capacitor
constant current
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US20230031567A1 (en
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Manabu Fujimura
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Ablic Inc
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Ablic Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
    • H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits

Definitions

  • the present invention relates to an oscillation circuit.
  • An oscillation circuit is required to output a constant frequency without being affected by fluctuations in the power supply voltage and the temperature.
  • FIG. 4 is a circuit diagram illustrating a conventional oscillation circuit.
  • the oscillation circuit 400 of FIG. 4 includes a capacitor C 1 , inverters 41 , 42 , and 44 , a bandgap constant voltage circuit 43 (hereinafter referred to as a BGR circuit), a constant current source circuit 45 , a constant current bias generation circuit 46 , a PMOS transistor M 1 , and an NMOS transistor M 2 .
  • the BGR circuit 43 supplies a voltage VBGR which is not affected by fluctuations in the power supply voltage and the temperature.
  • the constant current source circuit 45 bias-controlled by the constant current bias generation circuit 46 generates a constant current which is not affected by fluctuations in the power supply voltage and the temperature. Since the voltage VBGR and the constant current control the voltage of the capacitor C 1 , the oscillation circuit of FIG. 4 can output a constant frequency from the inverter 42 without being affected by fluctuations in the power supply voltage and the temperature.
  • the above oscillation circuit includes the BGR circuit 43 and the constant current bias generation circuit 46 , the circuit scale of these circuits is large and the current consumption is large.
  • An oscillation circuit includes a capacitor, a first constant current circuit, a first switch circuit, a second constant current circuit, a first MOS transistor, a second MOS transistor, a second switch circuit, and an output port.
  • the first constant current circuit is connected between a first power supply terminal and one port of the capacitor.
  • the first switch circuit is connected between another port of the capacitor and a second power supply terminal.
  • the second constant current circuit has one port connected to the first power supply terminal.
  • the first MOS transistor has a gate and a drain connected to another port of the second constant current circuit and a source connected to the another port of the capacitor.
  • the second MOS transistor has a gate connected to the gate of the first MOS transistor and a drain connected to the one port of the capacitor.
  • the second switch circuit is connected between a source of the second MOS transistor and the second power supply terminal.
  • the output port outputs a signal based on a voltage of the one port of the capacitor. Turn-on and turn-off of the first switch circuit and the second switch circuit are controlled by the signal of the output port and an inverted signal of the signal.
  • the oscillation circuit of the present invention includes the NMOS transistors and the switch circuits which raise and lower the voltage of the capacitor by a constant voltage, and the constant current circuits which charge and discharge the capacitor by a constant current. Therefore, it is possible to provide an oscillation circuit which has a small circuit scale and a small current consumption but can output a constant frequency without being affected by fluctuations in the power supply voltage and the temperature.
  • FIG. 1 is a block diagram illustrating an oscillation circuit of the present embodiment.
  • FIG. 2 is a circuit diagram illustrating an example of the oscillation circuit of the present embodiment.
  • FIG. 3 is a timing chart illustrating the operation of the oscillation circuit of the present embodiment.
  • FIG. 4 is a block diagram illustrating a conventional oscillation circuit.
  • Embodiments of the present invention provide an oscillation circuit capable of outputting a constant frequency without being affected by fluctuations in the power supply voltage and the temperature, even if the circuit scale is small and the current consumption is small.
  • FIG. 1 is a block diagram illustrating an oscillation circuit 100 of the present embodiment.
  • the oscillation circuit 100 of FIG. 1 includes constant current circuits 10 , 11 , and 12 , NMOS transistors 13 , 14 , and 15 , switch circuits 16 and 17 , a capacitor 18 , and inverters 30 and 31 .
  • the constant current circuit 12 and the NMOS transistor 15 constitute a constant current inverter.
  • each of the constant current circuits 10 , 11 , and 12 is connected to a power supply terminal.
  • the drain and the gate of the NMOS transistor 13 are connected to another port of the constant current circuit 10 , and the source of the NMOS transistor 13 is connected to one port of the switch circuit 16 .
  • Another port of the switch circuit 16 is connected to a ground terminal, and a control port of the switch circuit 16 is connected to an output port of the inverter 31 .
  • the drain of the NMOS transistor 14 is connected to another port of the constant current circuit 11 , the gate of the NMOS transistor 14 is connected to the gate of the NMOS transistor 13 , and the source of the NMOS transistor 14 is connected to one port of the switch circuit 17 .
  • Another port of the switch circuit 17 is connected to a ground terminal, and a control port of the switch circuit 17 is connected to an output port of the inverter 30 .
  • One port of the capacitor 18 is connected to the source of the NMOS transistor 13 and another port of the capacitor 18 is connected to the drain of the NMOS transistor 14 .
  • the drain of the NMOS transistor 15 is connected to another port of the constant current circuit 12 , the gate of the NMOS transistor 15 is connected to the drain of the NMOS transistor 14 , and the source of the NMOS transistor 15 is connected to a ground terminal.
  • An input port of the inverter 30 is connected to the drain of the NMOS transistor 15 .
  • An input port of the inverter 31 is connected to the output port of the inverter 30 , and the output port of the inverter 31 is connected to an output port of the oscillation circuit 100 .
  • the oscillation circuit 100 of FIG. 1 controls turn-on and turn-off of the switch circuits 16 and 17 by signals CLK and CLKB, and charges and discharges the capacitor 18 by constant currents I 10 and I 11 of the constant current circuits 10 and 11 to output the signal CLK.
  • the oscillation circuit 100 of FIG. 1 is designed with the following conditions.
  • the oscillation circuit 100 configured as described above operates as follows.
  • FIG. 3 is a timing chart illustrating the operation of the oscillation circuit 100 .
  • the capacitor 18 In the initial state, the capacitor 18 is not charged.
  • the signal CLK becomes H level and the signal CLKB becomes L level, so that the switch circuit 16 is turned on and the switch circuit 17 is turned off. Therefore, the voltage V 1 of the node N 1 becomes the voltage of the ground terminal, i.e., L level.
  • the capacitor 18 is charged by the constant current I 11 flowing from a node N 2 to the node N 1 . Then, a voltage V 2 of the node N 2 , which is the voltage of the capacitor 18 , gradually rises. At the time t 1 , when the voltage V 2 reaches a threshold value Vth 15 of the NMOS transistor 15 , the NMOS transistor 15 is turned on. Therefore, the signal CLK becomes L level and the signal CLKB becomes H level.
  • the switch circuit 16 is turned off and the switch circuit 17 is turned on.
  • the NMOS transistor 13 With the constant current I 10 flowing, the NMOS transistor 13 generates a voltage Vgs 13 between the gate and the source.
  • the NMOS transistor 13 and the NMOS transistor 14 may be designed so that the voltage ⁇ Vgs at this time becomes a positive value.
  • the voltage V 1 becomes the voltage ⁇ Vgs
  • the voltage V 2 of the node N 2 is raised by the voltage ⁇ Vgs due to the capacitor 18 and becomes Vth 15 + ⁇ Vgs.
  • the switch circuit 17 turned on, the voltage charged in the capacitor 18 is discharged to the ground terminal via the NMOS transistor 14 .
  • the discharge current at this time is a current corresponding to the constant current I 10 of the constant current circuit 10 .
  • the voltage V 2 which is the voltage of the capacitor 18 being the voltage Vth 15 + ⁇ Vgs at the time t 1 , is discharged by the constant current I 10 and gradually drops. Then, at the time t 2 , when the voltage V 2 falls below the threshold value Vth 15 of the NMOS transistor 15 , the NMOS transistor 15 is turned off. Therefore, the signal CLK becomes H level and the signal CLKB becomes L level.
  • the switch circuit 16 is turned on and the switch circuit 17 is turned off.
  • the voltage V 1 of the node N 1 changes from ⁇ Vgs to the voltage of the ground terminal.
  • the voltage V 2 of the node N 2 is lowered by the voltage ⁇ Vgs due to the capacitor 18 and becomes Vth 15 ⁇ Vgs.
  • the oscillation circuit 100 outputs a signal CLK having a duty ratio of 50% to the output port.
  • FIG. 2 is a circuit diagram illustrating an example of the oscillation circuit 100 of the present embodiment.
  • the constant current circuits 10 , 11 , and 12 are composed of a bias circuit 20 and PMOS transistors 10 , 11 , and 12 .
  • the PMOS transistors 10 and 11 are designed to pass the same current and have the same size.
  • the switch circuits 16 and 17 are composed of NMOS transistors 16 and 17 .
  • the bias circuit 20 includes NMOS transistors 21 and 22 , a resistor 23 , and PMOS transistors 24 and 25 .
  • the source of the NMOS transistor 21 is connected to a ground terminal via the resistor 23 .
  • the source of the NMOS transistor 22 is connected to a ground terminal, and the drain and the gate of the NMOS transistor 22 are connected to the gate of the NMOS transistor 21 .
  • the source of the PMOS transistor 24 is connected to a power supply terminal, and the drain of the PMOS transistor 24 is connected to the drain of the NMOS transistor 22 .
  • the source of the PMOS transistor 25 is connected to a power supply terminal, and the drain and the gate of the PMOS transistor 25 are connected to the gate of the PMOS transistor 24 and the drain of the NMOS transistor 21 .
  • I 25 ⁇ Vgs_ B /R.
  • ⁇ Vgs_ B is the difference between the Vgs's of the NMOS transistors 21 and 22
  • R is the resistance value of the resistor 23 .
  • I is the current flowing through the constant current circuits 10 and 11
  • C is the capacitance value of the capacitor 18 .
  • the frequency f is determined by the capacitance value of the capacitor 18 and the resistance value of the resistor 23 .
  • the frequency f of the signal CLK of the oscillation circuit 100 may not be affected by variations in the characteristics of the MOS transistors and may not be affected by fluctuations in the power supply voltage and the temperature, and a constant frequency f may be outputted.
  • the frequency f can have improved characteristics by using a resistor having good temperature characteristics.
  • the oscillation circuit 100 of the present embodiment is composed of the NMOS transistors 13 and 14 and the switch circuits 16 and 17 which raise and lower the voltage of the capacitor 18 by a constant voltage ( ⁇ Vgs), and the constant current circuits 10 and 11 which charge and discharge the capacitor 18 by a constant current. Therefore, even if the circuit scale is small and the current consumption is small, a constant frequency can be outputted without being affected by fluctuations in the power supply voltage and the temperature.
  • the present invention is not limited to the above embodiment, and various modifications may be made without departing from the spirit of the present invention.
  • the circuit is configured so that the PMOS transistors and the NMOS transistors are exchanged.

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  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
US17/870,856 2021-07-29 2022-07-22 Oscillation circuit Active US11683010B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021123773A JP2023019228A (ja) 2021-07-29 2021-07-29 発振回路
JP2021-123773 2021-07-29
JPJP2021-123773 2021-07-29

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US20230031567A1 US20230031567A1 (en) 2023-02-02
US11683010B2 true US11683010B2 (en) 2023-06-20

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US17/870,856 Active US11683010B2 (en) 2021-07-29 2022-07-22 Oscillation circuit

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US (1) US11683010B2 (zh)
JP (1) JP2023019228A (zh)
KR (1) KR20230018323A (zh)
CN (1) CN115694433A (zh)
TW (1) TW202306314A (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005217762A (ja) 2004-01-29 2005-08-11 Fujitsu Ltd 発振回路および半導体装置
US20170117882A1 (en) * 2014-08-20 2017-04-27 Infineon Technologies Austria Ag Oscillator circuit
US20200343858A1 (en) * 2019-04-23 2020-10-29 Renesas Electronics Corporation Oscillator circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005217762A (ja) 2004-01-29 2005-08-11 Fujitsu Ltd 発振回路および半導体装置
US7068116B2 (en) 2004-01-29 2006-06-27 Fuiitsu Limited Oscillation circuit and semiconductor device free from the influence of source voltage, temperature and fluctuations in the inverter threshold voltage
US20170117882A1 (en) * 2014-08-20 2017-04-27 Infineon Technologies Austria Ag Oscillator circuit
US20200343858A1 (en) * 2019-04-23 2020-10-29 Renesas Electronics Corporation Oscillator circuit

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JP2023019228A (ja) 2023-02-09
CN115694433A (zh) 2023-02-03
US20230031567A1 (en) 2023-02-02
TW202306314A (zh) 2023-02-01
KR20230018323A (ko) 2023-02-07

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