US11600335B2 - Memory device and bit line precharging method during program verify operation in the memory device - Google Patents

Memory device and bit line precharging method during program verify operation in the memory device Download PDF

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US11600335B2
US11600335B2 US16/827,109 US202016827109A US11600335B2 US 11600335 B2 US11600335 B2 US 11600335B2 US 202016827109 A US202016827109 A US 202016827109A US 11600335 B2 US11600335 B2 US 11600335B2
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voltage
read
bit lines
verify
program
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US20210065812A1 (en
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Chi Wook An
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SK Hynix Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Definitions

  • Various embodiments relate generally to a memory device and an operating method thereof, and more particularly, to a memory device capable of performing program and read operations, and an operating method thereof.
  • a memory device may store data or output the stored data.
  • the memory device may include a volatile memory device which loses stored data when its power supply is interrupted, or a non-volatile memory device which retains the stored data even when its power supply is interrupted.
  • the memory device may include a memory cell array storing data, peripheral circuits performing various operations including program, read, and erase operations, and a control logic controlling the peripheral circuits.
  • the memory controller may control data communication between a host and the memory device.
  • the memory device may communicate with the memory controller through a channel and perform a program, read, or erase operation in response to a command received from the memory controller.
  • Memory devices may be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices may lose data when their power supply is stopped, whereas non-volatile memory devices can retain stored data even in the absence of a power supply. Non-volatile memory devices and volatile memory devices have advantages and disadvantages. Thus, an appropriate choice may be made for its purpose.
  • a program or read operation may be performed in units of pages each corresponding to a group of memory cells coupled to a single word line. Therefore, in order to simultaneously operate a plurality of memory cells included in a single page during a read operation, a large amount of voltage or current may be required instantaneously.
  • Various embodiments of the present disclosure are directed to a memory device capable of compensating for, in a program operation, noise which may occur during a read operation by selectively precharging bit lines during a program verify operation in consideration of an order for a read operation, and a method of operating the same.
  • a memory device may include bit lines coupled to a memory block, a page buffer group selecting the bit lines from among the bit lines in response to page buffer signals, applying a precharge voltage to selected bit lines, and applying a ground voltage to unselected bit lines during a program verify operation, and a page buffer controller outputting the page buffer signals for the page buffer group to selectively apply the precharge voltage to the selected bit lines according to an order of read operations on a logical page during the program verify operation.
  • a method of operating a memory device may include performing a read operation on memory cells of a logical page by applying a ground voltage to bit lines of selected columns with data determined based on a read voltage, and applying a precharge voltage to bit lines of remaining columns, applying the ground voltage to one or more of the bit lines and applying the precharge voltage to remaining bit lines according to a verify voltage corresponding to the read voltage, during a program verify operation on selected memory cells, and applying the verify voltage to a word line coupled to the selected memory cells and verifying the memory cells, when the ground voltage or the precharge voltage is selectively applied to the bit lines.
  • a method of operating a memory device may include applying a precharge voltage being a positive voltage to all bit lines during a first read operation of a selected logical page from among a plurality of logical pages included in a selected physical page, and applying a ground voltage to bit lines of a memory cell with data determined by a previous read operation and applying the precharge voltage to remaining bit lines during second and subsequent read operations of the selected logical page, and selectively applying the ground voltage and the precharge voltage to the bit lines in a same manner as the read operations according to verify voltages respectively corresponding to read voltages of the read operations during a program verify operation when the selected physical page is programmed with logical data corresponding to the plurality of logical pages.
  • a method of operating a memory device may include performing a read operation with two or more read bias groups on the page by applying a ground voltage to a bit line of a memory cell, a status of which is determined by a previous read bias group, and applying a precharge voltage to a bit line of a memory cell, a status of which is to be determined by one or more subsequent read bias groups, and performing, after a program voltage is applied to the page, a program verify operation with two or more verify bias groups on the page by applying the ground voltage to the bit line of the memory cell, the status of which is determined by a previous verify bias group, and applying the precharge voltage to the bit line of the memory cell, the status of which is to be determined by one or more subsequent verify bias groups, wherein the read bias groups respectively correspond to the verify bias groups.
  • FIG. 1 is a diagram illustrating a memory system
  • FIG. 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure
  • FIG. 3 is a diagram illustrating a memory block shown in FIG. 2 ;
  • FIG. 4 is a diagram illustrating a read operation
  • FIG. 5 is a diagram illustrating a program operation
  • FIG. 6 is a diagram illustrating a bit line precharging method in a program verify operation according to a first embodiment of the present disclosure
  • FIG. 7 is a diagram illustrating a bit line precharging method in a program verify operation according to a second embodiment of the present disclosure
  • FIG. 8 is a diagram illustrating a bit line precharging method in a program verify operation according to a third embodiment of the present disclosure
  • FIG. 9 is a diagram illustrating a bit line precharging method in a program verify operation according to a fourth embodiment of the present disclosure.
  • FIG. 10 is a diagram illustrating another embodiment of a memory system including a memory device shown in FIG. 2 ;
  • FIG. 11 is a diagram illustrating another embodiment of a memory system including a memory device shown in FIG. 2 ;
  • FIG. 12 is a diagram illustrating another embodiment of a memory system including a memory device shown in FIG. 2 .
  • FIG. 1 is a diagram illustrating a memory system 1000 .
  • the memory system 1000 may include a memory device 1100 storing data, a buffer memory 1300 temporarily storing data necessary for operations of a memory system 1000 , and a memory controller 1200 controlling the memory device 1100 and the buffer memory 1300 in response to control of a host 2000 .
  • the host 2000 may communicate with the memory system 1000 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnection (PCI), PCI express (PCIe), Non-volatile Memory express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multi-Media Card (MMC), embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM) communication methods.
  • USB Universal Serial Bus
  • SATA Serial AT Attachment
  • SAS Serial Attached SCSI
  • HSIC High Speed Interchip
  • SCSI Small Computer System Interface
  • PCI Peripheral Component Interconnection
  • PCIe PCI express
  • NVMe Non-volatile Memory express
  • UFS Universal Flash Storage
  • SD Secure Digital
  • MMC Multi-Media Card
  • the memory devices 1100 may include a volatile memory device which loses the stored data when a power supply is interrupted, or a non-volatile memory device which retains the stored data even when the power supply is interrupted.
  • the memory controller 1200 may control the memory device 1100 to perform a program, read, or erase operation. For example, during a program operation, the memory device 1100 may receive a command, an address, and data from the memory controller 1200 and perform the program operation.
  • the memory device 1100 may reflect noise occurring during a read operation when performing a program operation, so that read errors caused by the noise generated during the read operation may be prevented.
  • the memory device 1100 may reflect a noise value corresponding to noise that may occur during a read operation in an operation of precharging bit lines during a program verify operation.
  • the memory controller 1200 may control the general operations of the memory system 1000 and control data exchange between the host 2000 and the memory device 1100 .
  • the memory controller 1200 may control the memory device 1100 to program, read or erase data in response to a request from the host 2000 .
  • the memory controller 1200 may receive data and a logical address from the host 2000 and convert the logical address into a physical address indicating a region where the data is actually stored.
  • the memory controller 1200 may generate a logical-to-physical address mapping table configuring a mapping relationship between a logical address and a physical address, and may store the mapping table in the buffer memory 1300 .
  • the buffer memory 1300 may serve as an operation memory or a cache memory of the memory controller 1200 and store various types of system data used in the memory system 1000 in addition to the above mapping table.
  • FIG. 1 illustrates that the buffer memory 1300 is located outside the memory controller 1200 .
  • the buffer memory 1300 may be located in the memory controller 1200 .
  • the buffer memory 1300 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR4 SDRAM, Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), or Rambus Dynamic Random Access Memory (RDRAM).
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • DDR4 SDRAM DDR4 SDRAM
  • LPDDR4 SDRAM Low Power Double Data Rate 4 SDRAM
  • GDDR Graphics Double Data Rate SDRAM
  • LPDDR Low Power DDR
  • RDRAM Rambus Dynamic Random Access Memory
  • FIG. 2 is a diagram illustrating the memory device 1100 according to an embodiment of the present disclosure.
  • the memory device 1100 may include a memory cell array 100 storing data, peripheral circuits 200 performing program, read and erase operations, and a control logic 300 controlling the peripheral circuits 200 .
  • the memory cell array 100 may include a plurality of memory blocks MB 1 to MBk, where k is a positive integer. Each of the memory blocks MB 1 to MBk may include a plurality of memory cells and have the same configuration.
  • the memory blocks MB 1 to MBk may share a source line SL with bit lines BL 1 to BLi, where i is a positive integer, and may be coupled to local lines LL, respectively.
  • the memory blocks MB 1 to MBk may include a plurality of memory cells having a two-dimensional or three-dimensional structure.
  • the two-dimensional memory cells may be arranged in a horizontal direction to a substrate.
  • the three-dimensional memory cells may be stacked in a vertical direction to the substrate.
  • the peripheral circuits 200 may include a voltage generator 210 , a row decoder 220 , a page buffer group 230 , an I/O circuit 240 , and a control logic 300 .
  • the voltage generator 210 may generate operating voltages Vop in response to an operating signal OP_SIG and output the generated operating voltages Vop.
  • the operating voltages Vop may include a program voltage, a pass voltage, a read voltage, an erase voltage and a verify voltage.
  • the voltage generator 210 may generate and output a program voltage, a verify voltage and a pass voltage.
  • the voltage generator 210 may generate and output a read voltage and a pass voltage.
  • an erase operation the voltage generator 210 may generate and output an erase voltage, an erase verify voltage and a pass voltage.
  • the row decoder 220 may transfer the operating voltages Vop to a selected memory block according to a row address RADD. For example, the row decoder 220 may transfer the operating voltages Vop through the local lines LL coupled to the selected memory block in response to the row address RADD. For example, during a program operation, the row decoder 220 may transfer a program voltage or a verify voltage to a selected word line, among the local lines LL, and a pass voltage to unselected word lines. During the program operation, the pass voltage may be set to have a higher voltage level than the verify voltage. During a read operation, the row decoder 220 may transfer a read voltage to a selected word line, among the local lines LL, and a pass voltage to unselected word lines.
  • the pass voltage may be set to have a higher voltage level than the read voltage.
  • Each of the program voltage, the verify voltage, the read voltage, the pass voltage and the erase voltage may be set to a positive voltage.
  • a verify voltage used in the erase operation may be set to a negative voltage.
  • the page buffer group 230 may be coupled to the selected memory block through the bit lines BL 1 to BLi.
  • the page buffer group 230 may include a plurality of buffers coupled to the bit lines BL 1 to BLi, and each of the page buffers may temporarily store data during a program or read operation.
  • the page buffers included in the page buffer group 230 may simultaneously operate in response to page buffer signals PBSIG.
  • the page buffer group 230 may temporarily store the data received from the I/O circuit 240 , and may control the voltage or current in the bit lines BL 1 to BLi in response to the received data.
  • the page buffer group 230 may temporarily store the data sensed by the voltage or the current of the bit lines BL 1 to BLi. During a read operation, the page buffer group 230 may transfer the data read through the bit lines BL 1 to BLi to the I/O circuit 240 .
  • Each of the page buffers included in the page buffer group 230 may include a plurality of latches for temporarily storing data and generate a precharge voltage for precharging the bit lines BL 1 to BLi by combining data stored in the latches in response to the page buffer signals PBSIG.
  • page buffers PB 1 to PBi may selectively precharge the bit lines BL 1 to BLi by transferring data between the latches by various methods in response to the page buffer signals PBSIG.
  • the page buffer group 230 may selectively apply a ground voltage (0 V) or a precharge voltage to the bit lines BL 1 to BLi in response to the page buffer signals PBSIG.
  • the precharge voltage may be set to a positive voltage greater than the ground voltage (0 V).
  • the I/O circuit 240 may be coupled to the memory controller 1200 of FIG. 1 through input/output lines 10 , receive a command CMD, an address ADD and data from the memory controller 1200 , and may output the data received from the page buffer group 230 to the memory controller 1200 .
  • the I/O circuit 240 may transfer the received command CMD and address ADD to the control logic 300 and transfer the received data to a column decoder.
  • the control logic 300 may output operating signals OP_SIG, the row address RADD and the page control signals PBSIG in response to the command CMD and the address ADD.
  • the control logic 300 may include a page buffer controller 310 for controlling the page buffer group 230 .
  • the page buffer controller 310 may output the page buffer signals PBSIG for controlling the page buffer group 230 during a program operation, a read operation, or an erase operation. For example, during a program verify operation, the page buffer controller 310 may output the page buffer signals PBSIG so that the precharge voltage may be applied to only selected bit lines according to an algorithm that is set based on the order of the read operation.
  • FIG. 3 is a diagram illustrating one of the memory blocks MB 1 to MBk shown in FIG. 2 .
  • the first memory block MB 1 will be described as an example.
  • the first memory block MB 1 may include a plurality of word lines WL 1 to WL 16 arranged in parallel with each other between a first select line and a second select line.
  • the first select line may be a source select line SSL and the second select line may be a drain select line DSL.
  • the first memory block MB 1 may include a plurality of strings ST coupled between the bit lines BL 1 to BLi and a source line SL.
  • the bit lines BL 1 to BLi may be coupled to the strings ST, respectively, and the source line SL may be coupled in common to the strings ST. Since the strings ST may have the same configuration, the string ST coupled to the first bit line BL 1 will be described in detail by way of example.
  • the string ST may include a source select transistor SST, a plurality of memory cells F 1 to F 16 , and a drain select transistor DST coupled in series between the source line SL and the first bit line BL 1 .
  • Each string ST may include at least one source select transistor SST, at least one drain select transistor DST, and more memory cells than the memory cells F 1 to F 16 as shown in FIG. 3 .
  • a source of the source select transistor SST may be coupled to the source line SL and a drain of the drain select transistor DST may be coupled to the first bit line BL 1 .
  • the memory cells F 1 to F 16 may be coupled in series between the source select transistor SST and the drain select transistor DST. Gates of the source select transistors SST included in different strings ST may be coupled in common to the source select line SSL, gates of the drain select transistors DST may be coupled in common to the drain select line DSL, and gates of the memory cells F 1 to F 16 may be coupled to the plurality of word lines WL 1 to WL 16 , respectively.
  • a group of memory cells coupled to the same word line, among memory cells included in different strings ST, may be referred to as a physical page PPG. Therefore, the first memory block MB 1 may include as many physical pages PPG as the number of word lines WL 1 to WL 16 .
  • a method of storing one bit of data in a single memory cell is referred to as a single level cell (SLC) method.
  • One physical page PPG may store logical data corresponding to one logical page LPG.
  • a method of storing two bits of data in a single memory cell is referred to as a multi-level cell (MLC) method.
  • MLC multi-level cell
  • One physical page PPG stores logical data corresponding to two logical pages LPG.
  • a method of storing three bits of data in a single memory cell may be referred to as a triple level cell (TLC) method.
  • a method of storing four bits of data in a single memory cell is referred to as a quadruple level cell (QLC) method.
  • QLC quadruple level cell
  • more than four bits of data may be stored in a single memory cell.
  • the present embodiment is applicable to the MLC method, the TLC method, the QLC method and other methods which store more bits of data.
  • a plurality of memory cells included in one physical page PPG may be programmed or read at the same time.
  • the memory device 1100 may perform a program operation and a read operation in units of the physical pages PPG.
  • a plurality of memory cells included in a single memory block may be simultaneously erased.
  • the memory device 1100 may perform an erase operation in units of memory blocks.
  • the bit lines BL 1 to BLi coupled to the strings ST, respectively, may be coupled to the page buffers PB included in the page buffer group 230 .
  • the page buffers PB may selectively apply a ground voltage (0 V) or a precharge voltage Vpr to the bit lines BL 1 to BLi in response to the page buffer signals PBSIG.
  • FIG. 4 is a diagram illustrating a read operation.
  • memory cells may have any one of an erase state (ER) and three program states (PV 1 to PV 3 ).
  • ER erase state
  • PV 1 to PV 3 program states
  • a first program state PV 1 may have a greater threshold voltage than an erase state ER
  • a second program state PV 2 may have a greater threshold voltage than the first program state PV 1
  • a third program state PV 3 may have a greater threshold voltage than the second program state PV 2 .
  • three read voltages may be used in a read operation of the memory cells programmed using the MLC method.
  • a first read voltage R 1 for discriminating the erase state ER from the first to third program states PV 1 to PV 3 a second read voltage R 2 for discriminating the erase state ER and the first program state PV 1 from the second and third program states PV 2 and PV 3
  • a third read voltage R 3 for discriminating the erase state ER and the first and second program states PV 1 and PV 2 from the third program state PV 3 may be used.
  • a memory cell may store logical data including least significant bit (LSB) data and most significant bit (MSB) data. Therefore, the first to third read voltages R 1 to R 3 may be set to discriminate the LSB data from the MSB data.
  • the second read voltage R 2 may be used to identify the LSB data
  • the first and third read voltages R 1 and R 3 may be used to identify the MSB data.
  • the read operation may be performed with the precharge voltage Vpr applied to all bit lines.
  • memory cells having threshold voltages less than the second read voltage R 2 may become ON cells, whereas memory cells having threshold voltages greater than the second read voltage R 2 may become OFF cells.
  • An ON cell may refer to a cell in which a channel is formed and a current flows.
  • An OFF cell may refer to a cell in which a channel is blocked and a current does not flow.
  • read data DATA_R of an ON cell may be defined as 1 (one) and read data DATA_R of an OFF cell may be defined as 0 (zero).
  • the read data DATA_R of the memory cells having the erase state ER and the first program state PV 1 may be 1, and the read data DATA_R of the memory cells having the second and third program states PV 2 and PV 3 may be 0.
  • the operation of identifying the LSB data may be terminated by only the read operation using the second read voltage R 2 .
  • read operations using the first and third read voltages R 1 and R 3 may be performed.
  • the order in which the read operation using the first read voltage R 1 and the read operation using the third read voltage R 3 are performed may vary depending on a type of a memory device. According to this embodiment, the read operation using the first read voltage R 1 may be performed prior to the read operation using the third read voltage R 3 .
  • the read operation using the first read voltage R 1 is the first read operation for identifying MSB data, this read operation may be performed without determined data DDT. Therefore, the read operation using the first read voltage R 1 may be performed with the precharge voltage Vpr applied to all bit lines.
  • the read data DATA_R may be 1.
  • the read data DATA_R may be 0.
  • the first read voltage R 1 may have the lowest voltage level among the read voltages for identifying the MSB data.
  • the MSB data of the memory cells having the erase state ER may be determined as 1.
  • the MSB data of the first to third program states PV 1 to PV 3 may not be determined data. Therefore, only ‘1’ data of the memory cells corresponding to the erase state ER may be the determined data DDT in the read operation using the first read voltage R 1 .
  • the memory cells corresponding to the determined data DDT may not have to be read again during a read operation using the next read voltage in read operations of the same logical page (e.g., MSB page). Thus, these memory cells may be excluded from a read target in the read operation using the next read voltage.
  • the same logical page e.g., MSB page
  • a ground voltage of 0 V may be applied to bit lines of the memory cells corresponding to the determined data DDT during the previous read operation, i.e., the read operation using the first read voltage R 1 , and the precharge voltage Vpr may be applied to bit lines coupled to memory cells with no determined data DDT.
  • the read data DATA_R of the memory cells having the first and second program states PV 1 and PV 2 may be 1, and the read data DATA_R of the memory cells having the third program state PV 3 may be 0.
  • the read data DATA_R of the read operation using the third read voltage R 3 may be inverted and stored.
  • the read data DATA_R of the memory cells corresponding to the first and second program states PV 1 and PV 2 may change from 1 to 0, and the read data DATA_R of the memory cells corresponding to the third program state PV 3 may change 0 to 1. Since the read data DATA_R of the memory cells in the erase state ER is previously determined during the read operation using the first read voltage R 1 , the read data DATA_R may be maintained at 1. Accordingly, when the read operation using the third read voltage R 3 finishes, the LSB and MSB data of the first program state PV 1 , the second program state PV 2 and the third program state PV 3 may be 11, 10, 00 and 01, respectively.
  • bit lines may be selectively precharged in the same manner as a read operation, so that noise caused by the differences between the read operation and a program operation may be compensated. This will be described below in more detail.
  • FIG. 5 is a diagram illustrating a program operation.
  • a program operation of a selected page may include a process of applying a program voltage and a process of performing a program verify operation. These processes may be repeated by gradually increasing a program voltage Vpgm until threshold voltages of all memory cells are increased to a target voltage.
  • This method is referred to as an Incremental Step Pulse Program (ISPP) scheme.
  • ISPP Incremental Step Pulse Program
  • the program voltage applying process and the program verify operation performing process may constitute a single program loop PL.
  • a plurality of program loops PL may be performed by gradually increasing a program voltage.
  • a plurality of verify voltages may be used. Therefore, in a program operation using an ISPP method, the program loops PL using a plurality of verify voltages may be performed. For example, in the program loop PL using a first verify voltage Vf 1 , a verify operation may be performed by increasing threshold voltages of memory cells by applying the program voltage Vpgm to a selected word line Sel.WL, and determining whether the threshold voltages of the memory cells are higher than the first verify voltage Vf 1 by applying the first verify voltage Vf 1 to selected memory cells.
  • a verify operation using a second verify voltage Vf 2 higher than the first verify voltage Vf 1 may be performed. In this manner, when a verify operation using a third verify voltage Vf 3 passes, the program operation of the selected page may be terminated.
  • one verify voltage may be used in one program loop PL.
  • a plurality of verify voltages may be used in one program loop PL depending on a program method.
  • a program verify operation may be performed in a similar method to a read operation.
  • a program verify operation may be performed in such a manner that precharges bit lines and senses a voltage or current in the bit lines that varies depending on threshold voltages of memory cells.
  • bit lines may be selectively precharged according to a verify voltage corresponding to a read voltage.
  • FIG. 6 is a diagram illustrating a bit line precharging method in a program verify operation according to a first embodiment of the present disclosure.
  • bit lines may be selectively precharged according to a verify voltage corresponding to a read voltage.
  • reference numeral 61 denotes a method of precharging bit lines during a read operation
  • reference numeral 62 denotes a method of selectively precharging bit lines during a program verify operation.
  • the first to third verify voltages Vf 1 to Vf 3 used in the program verify operation may correspond to the first to third read voltages R 1 to R 3 , respectively.
  • the method of precharging the bit lines in the read operations using the first to third read voltages R 1 to R 3 may be applied to the program verify operation.
  • the first verify voltage Vf 1 may correspond to the first read voltage R 1 .
  • the precharge voltage Vpr may be applied to all bit lines. Therefore, in a program verify operation using the first verify voltage Vf 1 , the precharge voltage Vpr may be applied to all bit lines.
  • the second verify voltage Vf 2 may correspond to the second read voltage R 2 .
  • the precharge voltage Vpr may be applied to all bit lines. Therefore, in a program verify operation using the second verify voltage Vf 2 , the precharge voltage Vpr may be applied to all bit lines.
  • the third verify voltage Vf 3 may correspond to the third read voltage R 3 .
  • a ground voltage of 0 V may be applied to bit lines coupled to memory cells with determined data, and the precharge voltage Vpr may be applied to bit lines coupled to memory cells with no determined data. Accordingly, during the program verify operation, the ground voltage of 0 V may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER, and the precharge voltage Vpr may be applied to the remaining bit lines.
  • noise which may occur during the read operations using the first to third read voltages R 1 to R 3 may be compensated.
  • noise which may occur in the bit lines caused by erased cells or programmed cells during the read operation may be offset and prevent potential errors caused by noise in the bit lines.
  • FIG. 7 is a diagram illustrating a bit line precharging method in a program verify operation according to a second embodiment of the present disclosure.
  • a bit line precharging method in a program verify operation is shown.
  • three bits of data may be stored in a single memory cell.
  • Memory cells may be programmed into one of the erase state ER and the first to seventh program states PV 1 to PV 7 .
  • the three bits of data may be defined as logical data corresponding to different logical pages.
  • the three bits of data may consist of LSB data, CSB data and MSB data.
  • LSB, CSB and MSB data of the memory cells in the erase state ER are defined as 1, 1, and 1, respectively
  • a gray code of the erase state ER may be 111.
  • a gray code of the first program state PV 1 may be 110.
  • gray codes of the erase state ER, the first program state PV 1 , the second program state PV 2 , the third program state PV 3 , the fourth program state PV 4 , the fifth program state PV 5 , the sixth program state PV 6 , and the seventh program state PV 7 may be sequentially set to 111, 110, 100, 101, 001, 000, 010 and 011.
  • the gray codes shown in FIG. 7 are shown as an exemplary embodiment, however, various other combinations may be set.
  • the order of read voltages shown on the right side of the threshold voltages may refer to the order of read operations, and the drawing of Vf 1 to Vf 7 as shown below the threshold voltages illustrates a method of selectively precharging bit lines during a program verify operation.
  • a program verify operation when read operations of reading logical data are performed in order from a low level to a high level is described as an example.
  • LSB read operation only the read operation using a fourth read voltage R 4 may be performed.
  • CSB read operation read operations using second and sixth read voltages R 2 and R 6 may be performed.
  • MSB read operation read operations using first, third, fifth and seventh R 1 , R 3 , R 5 , and R 7 may be performed.
  • the LSB data of the erase state ER and the first to seventh program states PV 1 to PV 7 may be determined as 1 or 0.
  • memory cells having threshold voltages less than the fourth read voltage R 4 and corresponding to the erase state ER and the first to third program states PV 1 to PV 3 may be read as a value of 1, and memory cells having threshold voltages greater than the fourth read voltage R 4 and corresponding to the fourth to seventh program states PV 4 to PV 7 may be read as 0.
  • the LSB read operation only the read operation using the fourth read voltage R 4 may be performed. Therefore, data read during the read operation using the fourth read voltage R 4 may be determined data, and the LSB read operation may be terminated.
  • a CSB read operation may be performed.
  • the read operation using the second read voltage R 2 and the read operation using the sixth read voltage R 6 may be sequentially performed.
  • the second read voltage R 2 may be the lowest read voltage among the read voltages for identifying the CSB data. Therefore, when the read operation using the second read voltage R 2 is performed, ‘1’ data read from memory cells having threshold voltages less than the second read voltage R 2 may be determined data. For example, data read from the memory cells corresponding to the erase state ER and the first program state PV 1 and having threshold voltages lower than the second read voltage R 2 may be determined data.
  • ‘0’ data read from memory cells having threshold voltages greater than the second read voltage R 2 may not be determined data.
  • a ground voltage (0 V) may be applied to bit lines of columns determined during the read operation using the second read voltage R 2 , and the precharge voltage Vpr may be applied to only bit lines of columns with no determined data.
  • the ground voltage may be applied to the bit lines of the columns corresponding to the memory cells in the erase state ER and the first program state PV 1 with the determined data, and the precharge voltage Vpr may be applied to the remaining bit lines.
  • ‘1’ data may be read from the memory cells having the second to fifth program states PV 2 to PV 5
  • ‘0’ data may be read from the memory cells having the sixth and seventh program states PV 6 and PV 7
  • the data read using the sixth read voltage R 6 may be inverted and stored in the page buffers.
  • data of the memory cells corresponding to the second to fifth program states PV 2 to PV 5 may be determined as 0, and data of the memory cells corresponding to the sixth and seventh program states PV 6 and PV 7 may be determined as 1. Since the data of the memory cells corresponding to the erase state ER and the first program state PV 1 is determined as 1 during the read operation using the second read voltage R 2 , the CSB read operation may be terminated when the read operation using the sixth read voltage R 6 finishes.
  • an MSB read operation may be performed.
  • read operations using the first, third, fifth and seventh read voltages R 1 , R 3 , R 5 , and R 7 may be sequentially performed.
  • the first read voltage R 1 may be the lowest read voltage among the read voltages for identifying the MSB data. Therefore, when the read operation using the first read voltage R 1 is performed, ‘1’ data read from memory cells having threshold voltages less than the first read voltage R 1 may be determined data. For example, data read from the memory cells corresponding to the erase state ER and having threshold voltages lower than the first read voltage R 1 may be determined data.
  • the data read from memory cells having the threshold voltages greater than the first read voltage R 1 may not be determined data.
  • a ground voltage (0 V) may be applied to bit lines of columns determined during the read operation using the first read voltage R 1 , and the precharge voltage Vpr may be applied to only bit lines of columns with no determined data.
  • the ground voltage may be applied to the bit lines of the columns corresponding to the memory cells in the erase state ER with the determined data, and the precharge voltage Vpr may be applied to the remaining bit lines.
  • ‘1’ data may be read from the memory cells having the first and second program states PV 1 and PV 2
  • ‘0’ data may be read from the memory cells having the third to seventh program states PV 3 to PV 7 .
  • the data read using the third read voltage R 3 may be inverted and stored in the page buffers. Therefore, data of the memory cells corresponding to the first and second program states PV 1 and PV 2 may be determined as 0.
  • the ground voltage (0 V) may be applied to the bit lines of the columns determined during the read operation using the third read voltage R 3 , and the precharge voltage Vpr may be applied to only the bit lines of the columns with no determined data.
  • the ground voltage (0 V) may be applied to the bit lines of the columns corresponding to the memory cells in the erase state ER and the first and second program states PV 1 and PV 2 with determined data in the read operations using the first and third read voltages R 1 and R 3 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • ‘1’ data read from the memory cells corresponding to the third and fourth program states PV 3 and PV 4 and having threshold voltages less than the fifth read voltage R 5 may be determined data.
  • a ground voltage (0 V) may be applied to bit lines of the columns determined during the read operation using the fifth read voltage R 5 , and the precharge voltage Vpr may be applied to only bit lines of the columns with no determined data.
  • the ground voltage (0 V) may be applied to the bit lines of the columns corresponding to the memory cells having the erase state ER and the first to fourth program states PV 1 to PV 4 with the determined data in the read operations using the first, third and fifth read voltages R 1 , R 3 and R 5 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • ‘1’ data may be read from the memory cells corresponding to the fifth and sixth program states PV 5 and PV 6 and having threshold voltages less than the seventh read voltage R 7
  • ‘0’ data may be read from the memory cells having threshold voltages greater than the seventh read voltage R 7
  • the data read using the seventh read voltage R 7 may be inverted and stored in the page buffers.
  • data of the memory cells corresponding to the fifth and sixth program states PV 5 and PV 6 may be determined as 0, and data of the memory cells corresponding to the seventh program state PV 7 may be determined as 1.
  • a read operation may be performed on a page including memory cells programmed into one of the erase state ER and the first to seventh program states PV 1 to PV 7 . Therefore, noise may vary depending on the read operations using the first to seventh read voltages R 1 to R 7 . Therefore, in this embodiment, to compensate for noise which may occur in a read operation, a method of selectively precharging bit lines in the read operation may be reflected in a program verify operation.
  • a program operation may be performed to gradually increase threshold voltages of memory cells in an erase state. Therefore, verify voltages may be used in a sequential manner from a low level during a program verify operation. For example, the first verify voltage Vf 1 which is the lowest voltage among the first to seventh verify voltages Vf 1 to Vf 7 may be used first, the second verify voltage Vf 2 may then be used, and subsequently, the third to seventh verify voltages Vf 3 to Vf 7 may be sequentially used to perform the program verify operation.
  • the first verify voltage Vf 1 may correspond to the first read voltage R 1 and the first read voltage R 1 may be used first in the MSB read operation. Therefore, during the program verify operation using the first verify voltage Vf 1 , the precharge voltage Vpr may be applied to all bit lines similar to the read operation using the first read voltage R 1 . For example, when the program verify operation using the first verify voltage Vf 1 starts, the precharge voltage Vpr may be applied to all bit lines, and the first verify voltage Vf 1 may be applied to a selected word line, thereby performing the program verify operation.
  • the second verify voltage Vf 2 may correspond to the second read voltage R 2 and the second read voltage R 2 may be used first in the CSB read operation. Therefore, during the program verify operation using the second verify voltage Vf 2 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the second read voltage R 2 . For example, when the program verify operation using the second verify voltage Vf 2 starts, the precharge voltage Vpr may be applied to all bit lines, and the second verify voltage Vf 2 may be applied to the selected word line, thereby performing the program verify operation.
  • the third verify voltage Vf 3 may correspond to the third read voltage R 3 , and the third read voltage R 3 may be used after the first read voltage R 1 in the MSB read operation. Therefore, during a program verify operation using the third verify voltage Vf 3 , a ground voltage (0 V) may be applied to bit lines coupled to memory cells corresponding to the erase state ER, and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the third read voltage R 3 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the third verify voltage Vf 3 may be applied to the selected word line, thereby performing the program verify operation.
  • a fourth verify voltage Vf 4 may correspond to the fourth read voltage R 4 and the fourth read voltage R 4 may be used first in the LSB read operation. Therefore, during a program verify operation using the fourth verify voltage Vf 4 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the fourth read voltage R 4 . For example, when the program verify operation using the fourth verify voltage Vf 4 starts, the precharge voltage Vpr may be applied to all bit lines, and the fourth verify voltage Vf 4 may be applied to the selected word line, thereby performing the program verify operation.
  • a fifth verify voltage Vf 5 may correspond to the fifth read voltage R 5 and the fifth read voltage R 5 may be used after the third read voltage R 3 in the MSB read operation. Therefore, during a program verify operation using the fifth verify voltage Vf 5 , the ground voltage (0 V) may be applied to bit lines coupled to memory cells corresponding to the erase state ER and the first and second program states PV 1 and PV 2 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the fifth read voltage R 5 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first and second program states PV 1 and PV 2
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the fifth verify voltage Vf 5 may be applied to the selected word line, thereby performing the program verify operation.
  • a sixth verify voltage Vf 6 may correspond to the sixth read voltage R 6 , and the sixth read voltage R 6 may be used after the second read voltage R 2 in the CSB read operation. Therefore, during a program verify operation using the sixth verify voltage Vf 6 , the ground voltage (0 V) may be applied to bit lines coupled to memory cells corresponding to the erase state ER and the first program state PV 1 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the sixth read voltage R 6 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first program state PV 1 , the precharge voltage Vpr may be applied to the remaining bit lines, and the sixth verify voltage Vf 6 may be applied to the selected word line, thereby performing the program verify operation.
  • the seventh verify voltage Vf 7 may correspond to the seventh read voltage R 7 , and the seventh read voltage R 7 may be used after the fifth read voltage R 5 in the MSB read operation. Therefore, during a program verify operation using the seventh verify voltage Vf 7 , the ground voltage (0 V) may be applied to bit lines coupled to memory cells corresponding to the erase state ER and the first to fourth program states PV 1 to PV 4 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the seventh read voltage R 7 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to fourth program states PV 1 to PV 4
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the seventh verify voltage Vf 7 may be applied to the selected word line, thereby performing the program verify operation.
  • FIG. 8 is a diagram illustrating a bit line precharging method in a program verify operation according to a third embodiment of the present disclosure.
  • FIG. 8 in a memory device according to a TLC method where read operations are performed in a second order (read order), a bit line precharging method in a program verify operation is shown.
  • a bit line precharging method in a program verify operation is shown in FIG. 8 .
  • overlapping contents with FIG. 7 will be omitted.
  • the order of the read voltages shown on the right side of threshold voltages may refer to the order of read operations, and the drawing of Vf 1 to Vf 7 as shown below the threshold voltages illustrates a method of selectively precharging bit lines during a program verify operation.
  • a program verify operation when read operations of reading logical data are performed in order from a high level to a low level is described as an example.
  • LSB read operation only the read operation using the fourth read voltage R 4 may be performed.
  • CSB read operation read operations using the sixth and second read voltages R 6 and R 2 may be performed.
  • MSB read operation read operations using the seventh, fifth, third and first read voltages R 7 , R 5 , R 3 , and R 1 may be performed.
  • the LSB data of the erase state ER and the first to seventh program states PV 1 to PV 7 may be determined as 1 or 0.
  • memory cells having threshold voltages less than the fourth read voltage R 4 and corresponding to the erase state ER and the first to third program states PV 1 to PV 3 may be read as a value of 1
  • memory cells having threshold voltages greater than the fourth read voltage R 4 and corresponding to the fourth to seventh program states PV 4 to PV 7 may be read as a value of 0.
  • only the read operation using the fourth read voltage R 4 may be performed. Therefore, data read during the read operation using the fourth read voltage R 4 may be determined data, and the LSB read operation may be terminated.
  • a CSB read operation may be performed.
  • the read operation using the sixth read voltage R 6 and the read operation using the second read voltage R 2 may be sequentially performed.
  • ‘1’ data may be read from the memory cells corresponding to the erase state ER and the first to fifth program states PV 1 to PV 5 and having threshold voltages less than the sixth read voltage R 6
  • ‘0’ data may be read from the memory cells having threshold voltages greater than the sixth read voltage R 6 and corresponding to the sixth and seventh program states PV 6 and PV 7
  • the data read using the sixth read voltage R 6 may be inverted and stored in the page buffers. Therefore, ‘1’ data corresponding to the read data of the memory cells corresponding to the sixth and seventh program states PV 6 and PV 7 may be determined data.
  • the ground voltage (0 V) may be applied to bit lines of the columns determined during the read operation using the sixth read voltage R 6 , and the precharge voltage Vpr may be applied to only bit lines of the columns with no determined data.
  • the ground voltage of 0 V may be applied to the bit lines of the columns corresponding to memory cells having the sixth and seventh program states PV 6 and PV 7 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • ‘1’ data may be read from the memory cells having the erase state ER and the first program state PV 1
  • ‘0’ data may be read from the memory cells having the second to fifth program states PV 2 to PV 5
  • the data read during the read operation using the second read voltage R 2 may be determined data.
  • the CSB data of the memory cells corresponding to the erase state ER and the first program state PV 1 may be 1
  • the CSB read operation may be terminated.
  • an MSB read operation may be performed.
  • the read operations using the seventh, fifth, third and first read voltages R 7 , R 5 , R 3 , and R 1 may be sequentially performed.
  • ‘1’ data may be read from the memory cells corresponding to the erase state ER and the first to sixth program states PV 1 to PV 6 , and having threshold voltages less than the seventh read voltage R 7
  • ‘0’ data may be read from the memory cells having threshold voltages greater than the seventh read voltage R 7 and corresponding to the seventh program state PV 7
  • the data read using the seventh read voltage R 7 may be inverted and stored in the page buffers. As a result, the data of the memory cells in the seventh program state PV 7 may be determined as 1.
  • the ground voltage (0 V) may be applied to bit lines of the columns determined during the read operation using the seventh read voltage R 7 , and the precharge voltage Vpr may be applied to only bit lines of the columns with no determined data.
  • the ground voltage may be applied to the bit lines of the columns corresponding to the memory cells in the seventh program state PV 7 with the determined data during the previous read operation, and the precharge voltage Vpr may be applied to the remaining bit lines.
  • ‘1’ data may be read from the memory cells corresponding to the erase state ER and the first to fourth program states PV 1 to PV 4 and having threshold voltages less than the fifth read voltage R 5
  • ‘0’ data may be read from the memory cells having threshold voltages greater than the fifth read voltage R 5 and corresponding to the fifth and sixth program states PV 5 and PV 6 . Therefore, data of the memory cells corresponding to the fifth and sixth program states PV 5 and PV 6 may be determined as 0.
  • the ground voltage (0 V) may be applied to bit lines of the columns determined during the read operation using the fifth read voltage R 5 , and the precharge voltage Vpr may be applied to only bit lines of columns with no determined data.
  • the ground voltage (0 V) may be applied to the bit lines of the columns corresponding to the memory cells in the fifth to seventh program states PV 5 to PV 7 with the determined data in the read operations using the seventh and fifth read voltages R 7 and R 5 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • ‘1’ data may be read from the memory cells corresponding to the erase state ER and the first and second program states PV 1 and PV 2 , and having threshold voltages less than the third read voltage R 3
  • ‘0’ data may be read from the memory cells having threshold voltages greater than the third read voltage R 3 and corresponding to the third and fourth program states PV 3 and PV 4
  • the data read using the third read voltage R 3 may be inverted and stored in the page buffers. Therefore, the data of the memory cells corresponding to the third and fourth program states PV 3 and PV 4 may be determined as 1.
  • the ground voltage (0 V) may be applied to bit lines of the columns determined during the read operation using the seventh, fifth and third read voltage R 7 , R 5 , and R 3 , and the precharge voltage Vpr may be applied to only bit lines of the columns with no determined data.
  • the ground voltage (0 V) may be applied to the bit lines of the columns corresponding to the memory cells in the third to seventh program states PV 3 to PV 7 with the determined data in the read operations using the seventh, fifth and third read voltages R 7 , R 5 and R 3 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • ‘1’ data may be read from the memory cells corresponding to the erase state ER and having threshold voltages less than the first read voltage R 1
  • ‘0’ data may be read from the memory cells having threshold voltages greater than the first read voltage R 1 and corresponding to the first and second program states PV 1 and PV 2 . Since the read operation using the first read voltage R 1 is performed last in the MSB read operation, the data read during the read operation using the first read voltage R 1 may be determined data. In other words, both the ‘1’ data read from the memory cells in the erase state ER and the ‘0’ data read from the memory cells in the first and second program states PV 1 and PV 2 may be determined data.
  • a program operation may be performed to gradually increase threshold voltages of memory cells in an erase state. Therefore, verify voltages may be used in a sequential manner from a low level during a program verify operation. For example, the first verify voltage Vf 1 which is the lowest voltage among the first to seventh verify voltages Vf 1 to Vf 7 may be used first, the second verify voltage Vf 2 may then be used, and subsequently, the third to seventh verify voltages Vf 3 to Vf 7 may be sequentially used to perform the program verify operation.
  • the first verify voltage Vf 1 may correspond to the first read voltage R 1 and the first read voltage R 1 may be used last in the MSB read operation. Therefore, during a program verify operation using the first verify voltage Vf 1 , the precharge voltage Vpr may be applied to bit lines coupled to memory cells corresponding to the erase state ER and the first and second program states PV 1 and PV 2 , and the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the third to seventh program states PV 3 to PV 7 in the same manner as the read operation using the first read voltage R 1 .
  • the precharge voltage Vpr may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first and second program states PV 1 and PV 2
  • the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the third to seventh program states PV 3 to PV 7
  • the first verify voltage Vf 1 may be applied to a selected word line, thereby performing the program verify operation.
  • the second verify voltage Vf 2 may correspond to the second read voltage R 2 and the second read voltage R 2 may be used last in the CSB read operation. Therefore, during a program verify operation using the second verify voltage Vf 2 , the ground voltage (0 V) may be applied to bit lines coupled to memory cells corresponding to the sixth to seventh program states PV 6 to PV 7 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the second read voltage R 2 .
  • the precharge voltage Vpr may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first to fifth program states PV 1 to PV 5
  • the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the sixth and seventh program states PV 6 and PV 7
  • the second verify voltage Vf 2 may be applied to the selected word line, thereby performing the program verify operation.
  • the third verify voltage Vf 3 may correspond to the third read voltage R 3 and the third read voltage R 3 may be used after the fifth read voltage R 5 in the MSB read operation. Therefore, during a program verify operation using the third verify voltage Vf 3 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the fifth to seventh program states PV 5 to PV 7 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the third read voltage R 3 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the fifth to seventh program states PV 5 to PV 7
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the third verify voltage Vf 3 may be applied to the selected word line, thereby performing the program verify operation.
  • the fourth verify voltage Vf 4 may correspond to the fourth read voltage R 4 and the fourth read voltage R 4 may be used first in the LSB read operation. Therefore, during a program verify operation using the fourth verify voltage Vf 4 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the fourth read voltage R 4 . For example, when the program verify operation using the fourth verify voltage Vf 4 starts, the precharge voltage Vpr may be applied to all bit lines, and the fourth verify voltage Vf 4 may be applied to the selected word line, thereby performing the program verify operation.
  • a fifth verify voltage Vf 5 may correspond to the fifth read voltage R 5 and the fifth read voltage R 5 may be used after the seventh read voltage R 7 in the MSB read operation. Therefore, during a program verify operation using the fifth verify voltage Vf 5 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the seventh program state PV 7 and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the fifth read voltage R 5 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the seventh program state PV 7
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the fifth verify voltage Vf 5 may be applied to the selected word line, thereby performing the program verify operation.
  • the sixth verify voltage Vf 6 may correspond to the sixth read voltage R 6 and the sixth read voltage R 6 may be used first in the CSB read operation. Therefore, during a program verify operation using the sixth verify voltage Vf 6 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the sixth read voltage R 6 . For example, when the program verify operation using the sixth verify voltage Vf 6 starts, the precharge voltage Vpr may be applied to all bit lines, and the sixth verify voltage Vf 6 may be applied to the selected word line, thereby performing the program verify operation.
  • the seventh verify voltage Vf 7 may correspond to the seventh read voltage R 7 and the seventh read voltage R 7 may be used first in the MSB read operation. Therefore, during a program verify operation using the seventh verify voltage Vf 7 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the seventh read voltage R 7 . For example, when the program verify operation using the seventh verify voltage Vf 7 starts, the precharge voltage Vpr may be applied to all bit lines, and the seventh verify voltage Vf 7 may be applied to the selected word line, thereby performing the program verify operation.
  • FIG. 9 is a diagram illustrating a bit line precharging method in a program verify operation according to a fourth embodiment of the present disclosure.
  • bit line precharging method in a program verify operation in a memory device using a QLC method is described.
  • four bits of data may be stored in a single memory cell.
  • Memory cells may be programmed into one of the erase state ER and the first to 15 th program states PV 1 to PV 15 .
  • Four bits of data may be defined as logical data corresponding to first to fourth logical pages 1 LP to 4 LP, respectively.
  • the four bits of data may include first to fourth logical data.
  • the first to fourth logical data may be defined as a gray code consisting of various combinations.
  • the order of read voltages shown above threshold voltages may refer to the order of read operations, and the drawing of Vf 1 to Vf 15 as shown below the threshold voltages illustrates a method of selectively precharging bit lines during a program verify operation.
  • bit lines may be selectively precharged during a program verify operation according to order of read operations.
  • read operations of the first to fourth logical pages 1 LP to 4 LP may be sequentially performed using different read voltages as shown below.
  • Read operations of the first logical page 1 LP may be performed using the first, sixth, eighth and eleventh read voltages R 1 , R 6 , R 8 , and R 11 in a sequential manner.
  • the first read voltage R 1 may be used first in the read operations of the first logical page 1 LP. Therefore, during the read operation using the first read voltage R 1 , the precharge voltage Vpr may be applied to all bit lines.
  • the read operation may be performed by applying the precharge voltage Vpr to all bit lines and applying the first read voltage R 1 to the selected word line.
  • the read operation using the sixth read voltage R 6 may be performed.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to read data determined in the read operation using the first read voltage R 1 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operations using the first and sixth read voltages R 1 and R 6 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operations using the first, sixth and eighth read voltages R 1 , R 6 and R 8 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • Read operations of the second logical page 2 LP may be performed using the second, seventh and thirteenth read voltages R 2 , R 7 , and R 13 in a sequential manner.
  • the second read voltage R 2 may be used first in the read operations of the second logical page 2 LP. Therefore, during the read operation using the second read voltage R 2 , the precharge voltage Vpr may be applied to all bit lines.
  • the read operation may be performed by applying the precharge voltage Vpr to all bit lines and applying the second read voltage R 2 to the selected word line.
  • the read operation using the seventh read voltage R 7 may be performed.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operation using the second read voltage R 2 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operations using the second and seventh read voltages R 2 and R 7 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operations using the second and seventh read voltages R 2 and R 7 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • Read operations of the third logical page 3 LP may be performed using the third, fifth, ninth and fifteenth read voltages R 3 , R 5 , R 9 , and R 15 in a sequential manner.
  • the third read voltage R 3 may be used first in the read operations of the third logical page 3 LP. Therefore, during the read operation using the third read voltage R 3 , the precharge voltage Vpr may be applied to all bit lines.
  • the read operation may be performed by applying the precharge voltage Vpr to all bit lines and applying the third read voltage R 3 to a selected word line.
  • the read operation using the third read voltage R 3 ends, the read operation using the fifth read voltage R 5 may be performed.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operation using the third read voltage R 3 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operations using the third read voltage R 3 and the fifth read voltage R 5 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operations using the third, fifth and ninth read voltages R 3 , R 5 and R 9 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • Read operations of the fourth logical page 4 LP may be performed using the fourth, tenth, twelfth and fourteenth 14 th read voltages R 4 , R 10 , R 12 , and R 14 in a sequential manner.
  • the fourth read voltage R 4 may be used first in the read operations of the fourth logical page 4 LP. Therefore, during the read operation using the fourth read voltage R 4 , the precharge voltage Vpr may be applied to all bit lines.
  • the read operation may be performed by applying the precharge voltage Vpr to all bit lines and applying the fourth read voltage R 4 to the selected word line.
  • the read operation using the fourth read voltage R 4 ends, the read operation using the tenth read voltage R 10 may be performed.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operation using the fourth read voltage R 4 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to the read data determined in the read operations using the fourth and tenth read voltages R 4 and R 10 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • the ground voltage (0 V) may be applied to bit lines of the columns corresponding to read data determined in the read operations using the fourth, tenth and twelfth read voltages R 4 , R 10 and R 12 , and the precharge voltage Vpr may be applied to the remaining bit lines.
  • a program operation may be performed to gradually increase threshold voltages of memory cells in an erase state. Therefore, verify voltages may be used in a sequential manner from a low level during a program verify operation. For example, the first verify voltage Vf 1 which is the lowest voltage among the first to fifteenth verify voltages Vf 1 to Vf 15 may be used first, the second verify voltage Vf 2 may then be used, and subsequently, the third to fifteenth verify voltages Vf 3 to Vf 15 may be sequentially used to perform the program verify operation.
  • the first verify voltage Vf 1 may correspond to the first read voltage R 1 and the first read voltage R 1 may be used first in the read operations of the first logical page 1 LP. Therefore, during the program verify operation using the first verify voltage Vf 1 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the first read voltage R 1 . For example, when the program verify operation using the first verify voltage Vf 1 starts, the precharge voltage Vpr may be applied to all bit lines, and the first verify voltage Vf 1 may be applied to the selected word line, thereby performing the program verify operation.
  • the second verify voltage Vf 2 may correspond to the second read voltage R 2 and the second read voltage R 2 may be used first in the read operations of the second logical page 2 LP. Therefore, during the program verify operation using the second verify voltage Vf 2 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the second read voltage R 2 . For example, when the program verify operation using the second verify voltage Vf 2 starts, the precharge voltage Vpr may be applied to all bit lines, and the second verify voltage Vf 2 may be applied to the selected word line, thereby performing the program verify operation.
  • the third verify voltage Vf 3 may correspond to the third read voltage R 3 and the third read voltage R 3 may be used first in the read operations of the third logical page 3 LP. Therefore, during the program verify operation using the third verify voltage Vf 3 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the third read voltage R 3 . For example, when the program verify operation using the third verify voltage Vf 3 starts, the precharge voltage Vpr may be applied to all bit lines, and the third verify voltage Vf 3 may be applied to the selected word line, thereby performing the program verify operation.
  • the fourth verify voltage Vf 4 may correspond to the fourth read voltage R 4 and the fourth read voltage R 4 may be used first in the read operations of the fourth logical page 4 LP. Therefore, during a program verify operation using the fourth verify voltage Vf 4 , the precharge voltage Vpr may be applied to all bit lines as in the read operation using the fourth read voltage R 4 . For example, when the program verify operation using the fourth verify voltage Vf 4 starts, the precharge voltage Vpr may be applied to all bit lines, and the fourth verify voltage Vf 4 may be applied to the selected word line, thereby performing the program verify operation.
  • the fifth verify voltage Vf 5 may correspond to the fifth read voltage R 5 and the fifth read voltage R 5 may be used after the third read voltage R 3 in the read operations of the third logical page 3 LP. Therefore, during a program verify operation using the fifth verify voltage Vf 5 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first and second program states PV 1 and PV 2 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the fifth read voltage R 5 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first and second program states PV 1 and PV 2
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the fifth verify voltage Vf 5 may be applied to the selected word line, thereby performing the program verify operation.
  • the sixth verify voltage Vf 6 may correspond to the sixth read voltage R 6 and the sixth read voltage R 6 may be used after the first read voltage R 1 in the read operations of the first logical page 1 LP. Therefore, during a program verify operation using the sixth verify voltage Vf 6 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER, and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the sixth read voltage R 6 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the sixth verify voltage Vf 6 may be applied to the selected word line, thereby performing the program verify operation.
  • the seventh verify voltage Vf 7 may correspond to the seventh read voltage R 7 and the seventh read voltage R 7 may be used after the second read voltage R 2 in the read operations of the second logical page 2 LP. Therefore, during a program verify operation using the seventh verify voltage Vf 7 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first program state PV 1 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the seventh read voltage R 7 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first program state PV 1 , the remaining bit lines may be applied to the remaining bit lines, and the seventh verify voltage Vf 7 may be applied to the selected word line, thereby performing the program verify operation.
  • the eighth verify voltage Vf 8 may correspond to the eighth read voltage R 8 and the eighth read voltage R 8 may be used after the sixth read voltage R 6 in the read operations of the first logical page 1 LP. Therefore, during a program verify operation using the eighth verify voltage Vf 8 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first to fifth program states PV 1 to PV 5 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the eighth read voltage R 8 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to fifth program states PV 1 to PV 5
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the eighth verify voltage Vf 8 may be applied to the selected word line, thereby performing the program verify operation.
  • the ninth verify voltage Vf 9 may correspond to the ninth read voltage R 9 and the ninth read voltage R 9 may be used after the fifth read voltage R 5 in the read operations of the third logical page 3 LP. Therefore, during a program verify operation using the ninth verify voltage Vf 9 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first to fourth program states PV 1 to PV 4 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the ninth read voltage R 9 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to fourth program states PV 1 to PV 4
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the ninth verify voltage Vf 9 may be applied to the selected word line, thereby performing the program verify operation.
  • the tenth verify voltage Vf 10 may correspond to the tenth read voltage R 10 and the tenth read voltage R 10 may be used after the fourth read voltage R 4 in the read operations of the fourth logical page 4 LP. Therefore, during a program verify operation using the tenth verify voltage Vf 10 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first to third program states PV 1 to PV 3 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the tenth read voltage R 10 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to third program states PV 1 to PV 3
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the tenth verify voltage Vf 10 may be applied to the selected word line, thereby performing the program verify operation.
  • the eleventh verify voltage Vf 11 may correspond to the eleventh read voltage R 11 and the eleventh read voltage R 11 may be used after the eighth read voltage R 8 in the read operations of the first logical page 1 LP. Therefore, during a program verify operation using the eleventh verify voltage Vf 11 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first to seventh program states PV 1 to PV 7 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the eleventh read voltage R 11 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to seventh program states PV 1 to PV 7 , the precharge voltage Vpr may be applied to the remaining bit lines, and the eleventh verify voltage Vf 11 may be applied to the selected word line, thereby performing the program verify operation.
  • the twelfth verify voltage Vf 12 may correspond to the twelfth read voltage R 12 and the twelfth read voltage R 12 may be used after the tenth read voltage R 10 in the read operations of the fourth logical page 4 LP. Therefore, during a program verify operation using the twelfth verify voltage Vf 12 , the ground voltage (0 V) may be applied to bit lines coupled to memory cells corresponding to the erase state ER and the first to ninth program states PV 1 to PV 9 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the twelfth read voltage R 12 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to ninth program states PV 1 to PV 9
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the twelfth verify voltage Vf 12 may be applied to the selected word line, thereby performing the program verify operation.
  • the thirteenth verify voltage Vf 13 may correspond to the thirteenth read voltage R 13 and the thirteenth read voltage R 13 may be used after the seventh read voltage R 7 in the read operations of the second logical page 2 LP. Therefore, during a program verify operation using the thirteenth verify voltage Vf 13 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first to sixth program states PV 1 to PV 6 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the thirteenth read voltage R 13 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to sixth program states PV 1 to PV 6
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the thirteenth verify voltage Vf 13 may be applied to the selected word line, thereby performing the program verify operation.
  • a fourteenth verify voltage Vf 14 may correspond to the fourteenth read voltage R 14 and the fourteenth read voltage R 14 may be used after the twelfth read voltage R 12 in the read operations of the fourth logical page 4 LP. Therefore, during a program verify operation using the fourteenth verify voltage Vf 14 , the ground voltage (0 V) may be applied to bit lines coupled to the memory cells corresponding to the erase state ER and the first to eleventh program states PV 1 to PV 11 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the fourteenth read voltage R 14 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to eleventh program states PV 1 to PV 11
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the fourteenth verify voltage Vf 14 may be applied to the selected word line, thereby performing the program verify operation.
  • the fifteenth verify voltage Vf 15 may correspond to the fifteenth read voltage R 15 and the fifteenth read voltage R 15 may be used after the ninth read voltage R 9 in the read operations of the third logical page 3 LP. Therefore, during a program verify operation using the fifteenth verify voltage Vf 15 , the ground voltage (0 V) may be applied to bit lines coupled to memory cells corresponding to the erase state ER and the first to eighth program states PV 1 to PV 8 , and the precharge voltage Vpr may be applied to the remaining bit lines in the same manner as the read operation using the fifteenth read voltage R 15 .
  • the ground voltage (0 V) may be applied to the bit lines coupled to the memory cells corresponding to the erase state ER and the first to eighth program states PV 1 to PV 8
  • the precharge voltage Vpr may be applied to the remaining bit lines
  • the fifteenth verify voltage Vf 15 may be applied to the selected word line, thereby performing the program verify operation.
  • the precharge voltage when a precharge voltage is selectively applied to bit lines during a read operation using a next read voltage, the precharge voltage may be selectively applied to bit lines in a program verify operation according to a verify voltage as in the read operation. Therefore, noise that may occur in the read operation may be reduced by reflecting the noise occurring in the read operation in the program verify operation in advance.
  • FIG. 10 is a diagram illustrating another embodiment of the memory system 1000 including the memory device 1100 shown in FIG. 2 .
  • a memory system 30000 may be embodied in a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device.
  • PDA personal digital assistant
  • the memory system 30000 may include the memory device 1100 and the memory controller 1200 for controlling the operations of the memory device 1100 .
  • the memory controller 1200 may control a data access operation of the memory device 1100 , for example, a program operation, an erase operation or a read operation of the memory device 1100 in response to control of the host 2000 .
  • the memory device 1100 may reduce errors that may occur in a read operation by previously reflecting noise that may occur in the read operation in a program verify operation during a program operation.
  • the memory controller 1200 may control data programmed into the memory device 1100 to be output through a display 3200 in response to control of the memory controller 1200 .
  • a radio transceiver 3300 may exchange a radio signal through an antenna ANT.
  • the radio transceiver 3300 may change the radio signal received through the antenna ANT into a signal which can be processed by the host 2000 . Therefore, the host 2000 may process the signal output from the radio transceiver 3300 and transfer the processed signal to the memory controller 1200 or the display 3200 .
  • the memory controller 1200 may transfer the signal processed by the host 2000 into the semiconductor memory device 1100 .
  • the radio transceiver 3300 may change a signal output from the host 2000 into a radio signal and output the radio signal to an external device through the antenna ANT.
  • a control signal for controlling the operations of the host or data to be processed by the host 2000 may be input by an input device 3400 , and the input device 3400 may include a pointing device, such as a touch pad, a computer mouse, a keypad, or a keyboard.
  • the host 2000 may control the operations of the display 3200 so that data output from the memory controller 1200 , data output from the radio transceiver 3300 , or data output from an input device 3400 may be output through the display 3200 .
  • FIG. 11 is a diagram illustrating another embodiment of the memory system 1000 including the memory device 1100 shown in FIG. 2 .
  • a memory system 40000 may be embodied in a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.
  • PC personal computer
  • PDA personal digital assistant
  • PMP portable multimedia player
  • MP3 player MP3 player
  • MP4 player MP4 player
  • the memory system 40000 may include the memory device 1100 and the memory controller 1200 for controlling a data processing operation of the memory device 1100 .
  • the memory device 1100 may reduce errors that may occur in a read operation by previously reflecting noise that may occur in the read operation in a program verify operation during a program operation.
  • the host 2000 may output data stored in the memory device 1100 through a display 4300 according to data input through an input device 4200 .
  • Examples of the input device 4200 may include a pointing device such as a touch pad, a computer mouse, a keypad, or a keyboard.
  • the host 2000 may control various operations of the memory system 40000 and control operations of the memory controller 1200 .
  • FIG. 12 is a diagram illustrating another embodiment of the memory system 1000 including the memory device 1100 shown in FIG. 2 .
  • a memory system may include the host 2000 and a memory card 70000 .
  • the memory card 70000 may be embodied in a smart card.
  • the memory card 70000 may include the memory device 1100 , the memory controller 1200 and a card interface 7100 .
  • the memory device 1100 may reduce errors that may occur in a read operation by previously reflecting noise that may occur in the read operation in a program verify operation during a program operation.
  • the memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100 .
  • the card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multi-media card (MMC) interface.
  • the card interface 7100 may interface data exchange between the host 2000 and the memory controller 1200 according to a protocol of the host 2000 .
  • the card interface 7100 may support a Universal Serial Bus (USB) protocol and an InterChip (IC)-USB protocol.
  • USB Universal Serial Bus
  • IC InterChip
  • the card interface 7100 may refer to hardware that supports a protocol used by the host 2000 , software mounted on the hardware, or a signal transmission method.
  • a read error caused by noise occurring during a read operation may be prevented by compensating for the noise in a program verify operation.
  • the reliability of a read operation of a memory device may be improved.
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