US11362078B2 - Display device - Google Patents

Display device Download PDF

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Publication number
US11362078B2
US11362078B2 US17/244,477 US202117244477A US11362078B2 US 11362078 B2 US11362078 B2 US 11362078B2 US 202117244477 A US202117244477 A US 202117244477A US 11362078 B2 US11362078 B2 US 11362078B2
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Prior art keywords
light emitting
emitting element
gradation value
pixel
green light
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US20210249394A1 (en
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Masanobu Ikeda
Yuji Maede
Yasuhiro Kanaya
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Japan Display Inc
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Japan Display Inc
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Assigned to JAPAN DISPLAY INC. reassignment JAPAN DISPLAY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANAYA, YASUHIRO, MAEDE, YUJI, IKEDA, MASANOBU
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
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    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
    • H—ELECTRICITY
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin

Definitions

  • What is disclosed herein relates to a display device.
  • the red LED described in U.S. Patent Application Publication No. 2018-0097033 includes a light emitting layer having a multi-quantum well structure made of gallium nitride (GaN).
  • the red LED described in WO 2010/128643 includes a light emitting layer made of material obtained by adding europium (Eu) to GaN.
  • the red LED described in US-A-2018-0097033 has lower luminous efficacy than those of a blue LED and a green LED. As a result, the red LED requires a higher drive current, which may possibly increase power consumption.
  • the red LED described in WO 2010/128643 has a half width of a light spectrum less than that of a blue LED and a green LED. As a result, only red color is vividly displayed, which may possibly make it difficult to satisfactorily display an image.
  • a display device includes: a substrate; and a plurality of pixels provided on the substrate.
  • Each of the pixels includes a red light emitting element and a first green light emitting element.
  • an emission intensity of the first green light emitting element is lower than an emission intensity of the red light emitting element, and a half width of a spectrum of light output from the first green light emitting element is greater than a half width of a spectrum of light output from the red light emitting element.
  • FIG. 1 is a plan view schematically illustrating a display device according to an embodiment
  • FIG. 2 is a plan view of a plurality of pixels
  • FIG. 3 is a circuit diagram of a pixel circuit
  • FIG. 4 is an enlarged plan view of two pixels of the display device according to the embodiment.
  • FIG. 5 is a sectional view along line V-V′ of FIG. 4 ;
  • FIG. 6 is a sectional view along line VI-VI′ of FIG. 4 ;
  • FIG. 7 is a sectional view of a red light emitting element according to the embodiment.
  • FIG. 8 is a graph schematically illustrating the relation between the emission intensity and the wavelength of each of the red light emitting element and a first green light emitting element;
  • FIG. 9 is a block diagram schematically illustrating the configuration of a signal processing circuit
  • FIG. 10 is a diagram for explaining the relation between the input gradation value and the light emitting element to be driven
  • FIG. 11 is a flowchart for explaining a method for setting output gradation values of the light emitting elements according to a first modification
  • FIG. 12 is a block diagram schematically illustrating the configuration of the signal processing circuit according to a second modification
  • FIG. 13 is a flowchart for explaining the method for setting the output gradation values of the light emitting elements according to the second modification
  • FIG. 14 is a flowchart for explaining the method for setting the output gradation values of the light emitting elements according to a third modification
  • FIG. 15A is a plan view of a first arrangement pattern of the light emitting elements in one pixel group according to a fourth modification
  • FIG. 15B is a plan view of a second arrangement pattern of the light emitting elements in one pixel group
  • FIG. 15C is a plan view of a third arrangement pattern of the light emitting elements in one pixel group
  • FIG. 16A is a plan view of a fourth arrangement pattern of the light emitting elements in two pixel groups according to a fifth modification
  • FIG. 16B is a plan view of a fifth arrangement pattern of the light emitting elements in two pixel groups
  • FIG. 16C is a plan view of a sixth arrangement pattern of the light emitting elements in two pixel groups
  • FIG. 17 is a sectional view of a red light emitting element according to a sixth modification.
  • FIG. 18 is a sectional view of a red light emitting element according to a seventh modification.
  • FIG. 19 is a sectional view of a red light emitting element according to an eighth modification.
  • FIG. 20 is a sectional view of a red light emitting element according to a ninth modification.
  • FIG. 21 is a sectional view of a red light emitting element according to a tenth modification.
  • the element when an element is described as being “on” another element, the element can be directly on the other element, or there can be one or more elements between the element and the other element.
  • FIG. 1 is a plan view schematically illustrating a display device according to an embodiment.
  • a display device 1 includes an array substrate 2 , pixels Pix (pixel group), drive circuits 12 , a drive integrated circuit (IC) 210 , and cathode wiring 60 .
  • the array substrate 2 is a drive circuit board for driving the pixels Pix and is also called a backplane or an active matrix substrate.
  • the array substrate 2 includes a substrate 21 , a plurality of transistors, a plurality of capacitances, and various kinds of wiring, for example.
  • the display device 1 has a display region AA and a peripheral region GA.
  • the display region AA is disposed overlapping the pixels Pix and displays an image.
  • the peripheral region GA does not overlap the pixels Pix and is disposed outside the display region AA.
  • the pixels Pix are arrayed in a first direction Dx and a second direction Dy in the display region AA.
  • the first direction Dx and the second direction Dy are parallel to the surface of the substrate 21 .
  • the first direction Dx is orthogonal to the second direction Dy.
  • the first direction Dx may intersect the second direction Dy without being orthogonal thereto.
  • a third direction Dz is orthogonal to the first direction Dx and the second direction Dy.
  • the third direction Dz corresponds to the normal direction of the substrate 21 , for example.
  • planar view indicates the positional relation when viewed in the third direction Dz.
  • the drive circuits 12 drive a plurality of gate lines (e.g., a reset control signal line L 5 , an output control signal line L 6 , a pixel control signal line L 7 , and an initialization control signal line L 8 (refer to FIG. 3 )) based on various control signals received from the drive IC 210 .
  • the drive circuits 12 sequentially or simultaneously select a plurality of gate lines and supply gate drive signals (e.g., pixel control signals SG) to the selected gate lines. As a result, the drive circuits 12 select a plurality of pixels Pix coupled to the gate lines.
  • the drive IC 210 is a circuit that controls display on the display device 1 .
  • the drive IC 210 is mounted on the peripheral region GA of the substrate 21 as a chip on glass (COG) driver.
  • the mounting form is not limited thereto, and the drive IC 210 may be mounted on a wiring substrate coupled to the peripheral region GA of the substrate 21 as a chip on film (COF) driver.
  • the wiring substrate is a flexible printed circuit board or a rigid substrate, for example.
  • the cathode wiring 60 is provided in the peripheral region GA of the substrate 21 .
  • the cathode wiring 60 is provided surrounding the pixels Pix in the display region AA and the drive circuits 12 in the peripheral region GA.
  • the cathode wiring 60 is disposed between a peripheral circuit provided on a substrate 10 and the outer periphery of the substrate 21 .
  • Cathodes (cathode terminals 22 t (refer to FIG. 5 )) of a plurality of light emitting elements 3 are coupled to the cathode wiring 60 that is common among the cathodes and are supplied with a fixed potential (e.g., a ground potential). More specifically, the cathode terminal 22 t (refer to FIG.
  • the cathode wiring 60 is not limited to a single wiring line continuously extending along three sides of the substrate 10 .
  • the cathode wiring 60 may be composed of two partial wiring lines having a slit at any one side on the substrate 21 and simply needs to be disposed along at least one side of the substrate 21 .
  • FIG. 2 is a plan view of a plurality of pixels.
  • one pixel Pix includes a plurality of pixels 49 .
  • the pixel Pix includes a first pixel 49 R, a second pixel 49 Ga, a third pixel 49 Gb, and a fourth pixel 49 B, for example.
  • the first pixel 49 R displays a primary color of red as the first color.
  • the second pixel 49 Ga displays a primary color of first green as the second color.
  • the third pixel 49 Gb displays a primary color of second green as the second color.
  • the fourth pixel 49 B displays a primary color of blue as the third color. While both the first green and the second green are green light, they are different in at least one of the emission intensity and the maximum emission intensity of a light spectrum.
  • the first pixel 49 R and the second pixel 49 Ga are disposed in the second direction Dy in one pixel Pix.
  • the first pixel 49 R and the fourth pixel 49 B are disposed in the first direction Dx.
  • the second pixel 49 Ga and the third pixel 49 Gb are disposed in the first direction Dx.
  • the third pixel 49 Gb and the fourth pixel 49 B are disposed in the second direction Dy.
  • the first color, the second color, and the third color are not limited to red, green, and blue, respectively, and may be any desired colors, such as complementary colors.
  • the first pixel 49 R, the second pixel 49 Ga, the third pixel 49 Gb, and the fourth pixel 49 B are referred to as pixels 49 when they need not be distinguished from one another.
  • the pixels 49 each include the light emitting element 3 and an anode electrode 23 .
  • the first pixel 49 R, the second pixel 49 Ga, the third pixel 49 Gb, and the fourth pixel 49 B include a red light emitting element 3 R, a first green light emitting element 3 Ga, a second green light emitting element 3 Gb, and a blue light emitting element 3 B, respectively.
  • the red light emitting element 3 R and the first green light emitting element 3 Ga are disposed in the second direction Dy.
  • the red light emitting element 3 R and the blue light emitting element 3 B are disposed in the first direction Dx.
  • the first green light emitting element 3 Ga and the second green light emitting element 3 Gb are disposed in the first direction Dx.
  • the second green light emitting element 3 Gb and the blue light emitting element 3 B are disposed in the second direction Dy.
  • the red light emitting element 3 R outputs red light.
  • the first green light emitting element 3 Ga outputs first green light.
  • the second green light emitting element 3 Gb outputs second green light.
  • the blue light emitting element 3 B outputs blue light.
  • the red light emitting element 3 R, the first green light emitting element 3 Ga, the second green light emitting element 3 Gb, and the blue light emitting element 3 B are referred to as the light emitting elements 3 when they need not be distinguished from one another.
  • the light emitting element 3 is an inorganic light emitting diode (LED) chip having a size of approximately 3 ⁇ m to 300 ⁇ m in planar view and is called a micro LED or a mini LED.
  • the display device 1 including the micro LEDs in the respective pixels is also called a micro LED display device.
  • the term “micro” of the micro LED is not intended to limit the size of the light emitting element 3 .
  • the light emitting elements 3 may output different light in four or more colors.
  • the first color, the second color, and the third color are not limited to red, green, and blue, respectively, and may be desired colors, such as complementary colors.
  • the number of pixels 49 disposed in one pixel Pix is not limited to four. Five or more pixels 49 may be disposed in one pixel Pix and correspond to different colors.
  • the array of the pixels 49 is not limited to that illustrated in FIG. 2 .
  • the first pixel 49 R, the second pixel 49 Ga, the third pixel 49 Gb, and the fourth pixel 49 B may be disposed in one of the first direction Dx and the second direction Dy.
  • FIG. 3 is a circuit diagram of a pixel circuit.
  • FIG. 3 illustrates a pixel circuit PICA provided in one pixel 49 .
  • the pixel circuit PICA is provided in each of the pixels 49 .
  • the pixel circuit PICA includes the light emitting element 3 , five transistors, and two capacitances.
  • the pixel circuit PICA includes a drive transistor DRT, an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST.
  • the drive transistor DRT, the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST are n-type thin-film transistors (TFTs).
  • the pixel circuit PICA includes a first capacitance Cs 1 and a second capacitance Cs 2 .
  • the cathode (cathode terminal 22 t ) of the light emitting element 3 is coupled to a cathode power supply line L 10 .
  • the anode (anode terminal 23 t ) of the light emitting element 3 is coupled to an anode power supply line L 1 via the drive transistor DRT and the output transistor BCT.
  • the anode power supply line L 1 is supplied with an anode power supply potential PVDD.
  • the cathode power supply line L 10 is supplied with a cathode power supply potential PVSS corresponding to the cathode wiring 60 and the cathode electrode 22 .
  • the anode power supply potential PVDD is higher than the cathode power supply potential PVSS.
  • the anode power supply line L 1 supplies, to the pixel 49 , the anode power supply potential PVDD serving as a drive potential.
  • the light emitting element 3 ideally emits light by being supplied with a forward current (drive current) by a potential difference (PVDD-PVSS) between the anode power supply potential PVDD and the cathode power supply potential PVSS.
  • the anode power supply potential PVDD has a potential difference to cause the light emitting element 3 to emit light with respect to the cathode power supply potential PVSS.
  • the anode terminal 23 t of the light emitting element 3 is coupled to the anode electrode 23 .
  • the second capacitance Cs 2 is coupled between the anode electrode 23 and the anode power supply line L 1 .
  • the source electrode of the drive transistor DRT is coupled to the anode terminal 23 t of the light emitting element 3 via the anode electrode 23 , and the drain electrode thereof is coupled to the source electrode of the output transistor BCT.
  • the gate electrode of the drive transistor DRT is coupled to the first capacitance Cs 1 , the drain electrode of the pixel selection transistor SST, and the drain electrode of the initialization transistor IST.
  • the gate electrode of the output transistor BCT is coupled to the output control signal line L 6 .
  • the output control signal line L 6 is supplied with an output control signal BG.
  • the drain electrode of the output transistor BCT is coupled to the anode power supply line L 1 .
  • the source electrode of the initialization transistor IST is coupled to an initialization power supply line L 4 .
  • the initialization power supply line L 4 is supplied with an initialization potential Vini.
  • the gate electrode of the initialization transistor IST is coupled to the initialization control signal line L 8 .
  • the initialization control signal line L 8 is supplied with an initialization control signal IG.
  • the gate electrode of the drive transistor DRT is coupled to the initialization power supply line L 4 via the initialization transistor IST.
  • the source electrode of the pixel selection transistor SST is coupled to a video signal line L 2 .
  • the video signal line L 2 is supplied with a video signal Vsig.
  • the gate electrode of the pixel selection transistor SST is coupled to the pixel control signal line L 7 .
  • the pixel control signal line L 7 is supplied with a pixel control signal SG.
  • the source electrode of the reset transistor RST is coupled to a reset power supply line L 3 .
  • the reset power supply line L 3 is supplied with a reset power supply potential Vrst.
  • the gate electrode of the reset transistor RST is coupled to the reset control signal line L 5 .
  • the reset control signal line L 5 is supplied with a reset control signal RG.
  • the drain electrode of the reset transistor RST is coupled to the anode electrode 23 (anode terminal 23 t of the light emitting element 3 ) and the source electrode of the drive transistor DRT. A reset operation performed by the reset transistor RST resets the voltage held in the first capacitance Cs 1 and the second capacitance Cs 2 .
  • the first capacitance Cs 1 is provided between the drain electrode of the reset transistor RST and the gate electrode of the drive transistor DRT.
  • the first capacitance Cs 1 and the second capacitance Cs 2 of the pixel circuit PICA can reduce fluctuations in the gate voltage that would be caused by parasitic capacitance and current leakage in the drive transistor DRT.
  • the anode power supply line L 1 and the cathode power supply line L 10 may be simply referred to as power supply lines.
  • the video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 may be referred to as signal lines.
  • the reset control signal line L 5 , the output control signal line L 6 , the pixel control signal line L 7 , and the initialization control signal line L 8 may be referred to as gate lines.
  • the gate electrode of the drive transistor DRT is supplied with an electric potential corresponding to the video signal Vsig (or gradation signal).
  • the drive transistor DRT supplies an electric current corresponding to the video signal Vsig to the light emitting element 3 in accordance with the anode power supply potential PVDD supplied via the output transistor BCT.
  • the anode power supply potential PVDD supplied to the anode power supply line L 1 is lowered by the drive transistor DRT and the output transistor BCT.
  • an electric potential lower than the anode power supply potential PVDD is supplied to the anode terminal 23 t of the light emitting element 3 .
  • a first electrode of the second capacitance Cs 2 is supplied with the anode power supply potential PVDD via the anode power supply line L 1 , and a second electrode of the second capacitance Cs 2 is supplied with an electric potential lower than the anode power supply potential PVDD.
  • the first electrode of the second capacitance Cs 2 is supplied with an electric potential higher than that supplied to the second electrode of the second capacitance Cs 2 .
  • the first electrode of the second capacitance Cs 2 is the anode power supply line L 1 , for example.
  • the second electrode of the second capacitance Cs 2 is the anode electrode 23 coupled to the source of the drive transistor DRT and an anode coupling electrode 24 coupled to the anode electrode 23 , for example.
  • the drive circuits 12 select a plurality of pixel rows in order from the first row (e.g., the uppermost pixel row in the display region AA in FIG. 1 ).
  • the drive IC 210 writes the video signals Vsig (video writing potential) to the pixels 49 of the selected pixel row, thereby causing the light emitting elements 3 to emit light.
  • the drive IC 210 supplies the video signals Vsig to the video signal line L 2 , supplies the reset power supply potential Vrst to the reset power supply line L 3 , and supplies the initialization potential Vini to the initialization power supply line L 4 in each horizontal scanning period.
  • the display device 1 repeats these operations for each image of one frame.
  • FIG. 4 is an enlarged plan view of two pixels of the display device according to the embodiment.
  • FIG. 4 illustrates two pixels 49 (e.g., the second pixel 49 Ga and the third pixel 49 Gb) that are adjacent in the first direction Dx.
  • the anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 extend in the second direction Dy.
  • the reset control signal line L 5 , the output control signal line L 6 , the pixel control signal line L 7 , and the initialization control signal line L 8 extend in the first direction Dx and intersect the anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 in planar view.
  • Coupling wiring L 9 is provided between the two anode power supply lines L 1 that are adjacent in the first direction Dx.
  • the coupling wiring L 9 couples the drive transistor DRT, the pixel selection transistor SST, and the initialization transistor IST.
  • the anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 are hatched.
  • the reset control signal line L 5 , the output control signal line L 6 , the pixel control signal line L 7 , and the initialization control signal line L 8 are represented by dotted lines.
  • Semiconductor layers 61 , 65 , 71 , 75 , and 79 are also hatched.
  • the anode coupling electrode 24 is represented by a long dashed double-short dashed line.
  • Each of the anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , the initialization power supply line L 4 , and the coupling wiring L 9 is made of a metal layer provided in a layer different from that of the gate lines (the reset control signal line L 5 , the output control signal line L 6 , the pixel control signal line L 7 , and the initialization control signal line L 8 ).
  • Examples of the material of the various wires include, but are not limited to, titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), niobium (Nb), indium tin oxide (ITO), aluminum (Al), silver (Ag), Ag alloy, copper (Cu), carbon nanotube, graphite, graphene, carbon nanobud, etc.
  • the sheet resistance of the anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , the initialization power supply line L 4 , and the coupling wiring L 9 is equal to or lower than those of the gate lines.
  • the sheet resistance of the anode power supply line L 1 is equal to or lower than those of the signal lines (the video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 ) and the coupling wiring L 9 .
  • the sheet resistance of the anode power supply line L 1 is 30 m ⁇ /square to 120 m ⁇ /square, for example.
  • the sheet resistance of each of the signal lines and the coupling wiring L 9 is 120 m ⁇ /square to 300 m ⁇ /square.
  • the sheet resistance of each gate line is 300 m ⁇ /square to 3000 m ⁇ /square.
  • Each of the various kinds of wiring lines is not limited to a single layer and may be a multilayered film.
  • the power supply lines and the signal lines may have a multilayered structure made of Ti/Al/Ti or Mo/Al/Mo or be a single-layered film made of Al.
  • Ti, Al, and Mo may be alloys.
  • the semiconductor layers 61 , 65 , 71 , 75 , and 79 are made of amorphous silicon, microcrystalline oxide semiconductor, amorphous oxide semiconductor, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), or gallium nitride (GaN), for example.
  • oxide semiconductor include, but are not limited to, IGZO, zinc oxide (ZnO), ITZO, etc.
  • IGZO is indium gallium zinc oxide
  • ITZO is indium tin zinc oxide.
  • the semiconductor layers 61 , 65 , 71 , 75 , and 79 may be made of the same material, such as polycrystalline silicon.
  • the reset power supply line L 3 and the initialization power supply line L 4 are shared by the two pixels 49 that are adjacent in the first direction Dx.
  • the second pixel 49 Ga illustrated on the left in FIG. 4 is provided not with the initialization power supply line L 4 but with the reset power supply line L 3 extending along the video signal line L 2 .
  • the third pixel 49 Gb illustrated on the right in FIG. 4 is provided not with the reset power supply line L 3 but with the initialization power supply line L 4 extending along the video signal line L 2 .
  • This configuration requires a smaller number of wiring lines and enables efficiently disposing the wiring lines as compared with the configuration in which the reset power supply line L 3 and the initialization power supply line L 4 are provided for each of the pixels 49 .
  • the drive transistor DRT includes the semiconductor layer 61 , a source electrode 62 , and a gate electrode 64 .
  • the semiconductor layer 61 , the source electrode 62 , and the gate electrode 64 partially overlap in planar view and are provided in a region surrounded by the two anode power supply lines L 1 adjacent in the first direction Dx, the output control signal line L 6 , and the pixel control signal line L 7 .
  • a channel region is formed in part of a region in the semiconductor layer 61 overlapping the gate electrode 64 .
  • the drive transistor DRT has a single-gate structure in which one gate electrode 64 is provided overlapping the semiconductor layer 61 .
  • the semiconductor layer 61 includes a first partial semiconductor layer 61 a .
  • the first partial semiconductor layer 61 a is provided in the same layer as that of the semiconductor layer 61 and made of the same semiconductor material as that of the semiconductor layer 61 .
  • the first partial semiconductor layer 61 a is a part protruding from the semiconductor layer 61 in the first direction Dx.
  • the width of the first partial semiconductor layer 61 a in the first direction Dx is greater than the width in the first direction Dx of the part of the semiconductor layer 61 coupled to the semiconductor layer 65 of the output transistor BCT.
  • the semiconductor layer 61 is coupled to the source electrode 62 via the first partial semiconductor layer 61 a .
  • the semiconductor layer 61 and the first partial semiconductor layer 61 a overlap a first insulating film 91 (refer to FIG. 5 ) and the gate electrode 64 .
  • the first capacitance Cs 1 is formed between the first partial semiconductor layer 61 a and the gate electrode 64 .
  • the semiconductor layer 61 and the first partial semiconductor layer 61 a may each have a rectangular shape and be electrically coupled to each other via a coupler.
  • the output transistor BCT includes the semiconductor layer 65 .
  • the semiconductor layer 65 is coupled to the semiconductor layer 61 of the drive transistor DRT and intersects the output control signal line L 6 in planar view. A channel region is formed in a region in the semiconductor layer 65 overlapping the output control signal line L 6 .
  • the part of the output control signal line L 6 overlapping the semiconductor layer 65 functions as a gate electrode 66 of the output transistor BCT.
  • One end of the semiconductor layer 65 is electrically coupled to an anode power supply line coupling part L 1 a .
  • the anode power supply line coupling part L 1 a is a part branched off in the first direction Dx from the anode power supply line L 1 .
  • the initialization transistor IST includes the semiconductor layer 71 .
  • the initialization transistor IST includes a semiconductor layer 71 A.
  • the semiconductor layers 71 and 71 A intersect the initialization control signal line L 8 and a branch signal line L 8 a in planar view.
  • a channel region is formed in a region in the semiconductor layers 71 and 71 A overlapping the initialization control signal line L 8 and the branch signal line L 8 a .
  • the branch signal line L 8 a is branched off from the initialization control signal line L 8 and extends in the first direction Dx.
  • the parts of the initialization control signal line L 8 and the branch signal line L 8 a overlapping the semiconductor layers 71 and 71 A each function as a gate electrode 74 of the initialization transistor IST.
  • the initialization transistor IST has a double-gate structure in which two gate electrodes 74 are provided overlapping the respective semiconductor layers 71 and 71 A.
  • the semiconductor layer 71 extends in the second direction Dy.
  • One end of the semiconductor layer 71 is electrically coupled to the coupling wiring L 9 , and the other end is coupled to an initialization power supply line coupling part L 4 a .
  • the initialization power supply line coupling part L 4 a is a part branched off from the initialization power supply line L 4 in the first direction Dx.
  • the semiconductor layer 71 A includes a part extending in the second direction Dy and a part extending in the first direction Dx.
  • One end of the part of the semiconductor layer 71 A extending in the second direction Dy is electrically coupled to the coupling wiring L 9 .
  • the part of the semiconductor layer 71 A extending in the first direction Dx intersects the anode power supply line L 1 and the video signal line L 2 in planar view, extends to the third pixel 49 Gb, and is electrically coupled to the initialization power supply line coupling part L 4 a .
  • one initialization power supply line L 4 is electrically coupled to the two initialization transistors IST and shared by the two pixels 49 disposed adjacent in the first direction Dx.
  • the pixel selection transistor SST includes the semiconductor layer 75 .
  • the semiconductor layer 75 extends in the first direction Dx and intersects two branch signal lines L 7 a in planar view. A channel region is formed in a region in the semiconductor layer 75 overlapping the two branch signal lines L 7 a .
  • the two branch signal lines L 7 a are parts branched off from the pixel control signal line L 7 in the second direction Dy.
  • the parts of the two branch signal lines L 7 a overlapping the semiconductor layer 75 each function as a gate electrode 78 of the pixel selection transistor SST.
  • the pixel selection transistor SST has a double-gate structure in which two gate electrodes 78 are provided overlapping the semiconductor layer 75 .
  • the video signal line coupling part L 2 a is a part branched off from the video signal line L 2 in the first direction Dx.
  • the reset transistor RST includes the semiconductor layer 79 .
  • the semiconductor layer 79 extends in the second direction Dy and intersects the reset control signal line L 5 and a branch signal line L 5 a in planar view.
  • a channel region is formed in a region in the semiconductor layer 79 overlapping the reset control signal line L 5 and the branch signal line L 5 a .
  • the branch signal line L 5 a is branched off from the reset control signal line L 5 and extends in the first direction Dx.
  • the parts of the reset control signal line L 5 and the branch signal line L 5 a overlapping the semiconductor layer 79 each function as a gate electrode of the reset transistor RST.
  • the reset transistor RST has a double-gate structure.
  • the reset power supply line L 3 is coupled to reset power supply line coupling parts L 3 a and L 3 b and a bridge L 3 c extending in the first direction Dx.
  • the reset power supply line coupling parts L 3 a and L 3 b are made of the same metal layer as that of the reset power supply line L 3 .
  • the bridge L 3 c is made of a layer different from that of the reset power supply line coupling parts L 3 a and L 3 b , such as the same metal layer as that of the various gate lines.
  • the reset power supply line coupling part L 3 a is provided in the second pixel 49 Ga
  • the reset power supply line coupling part L 3 b is provided in the third pixel 49 Gb.
  • the anode power supply line L 1 , the video signal line L 2 , and the initialization power supply line L 4 are provided between the reset power supply line coupling parts L 3 a and L 3 b .
  • the bridge L 3 c intersects the anode power supply line L 1 , the video signal line L 2 , and the initialization power supply line L 4 in planar view and couples the reset power supply line coupling parts L 3 a and L 3 b.
  • one end of the semiconductor layer 79 is coupled to the reset power supply line coupling part L 3 a .
  • one end of the semiconductor layer 79 is coupled to the reset power supply line coupling part L 3 b .
  • the other ends of the semiconductor layers 79 are each electrically coupled to the semiconductor layer 61 of the drive transistor DRT.
  • the other end of the semiconductor layer 79 of the reset transistor RST is electrically coupled to the anode terminal 23 t of the light emitting element 3 via the semiconductor layer 61 and the source electrode 62 .
  • one reset power supply line L 3 is electrically coupled to two reset transistors RST and shared by two pixels 49 disposed adjacent in the first direction Dx.
  • the first capacitance Cs 1 (refer to FIG. 3 ) is formed between the semiconductor layer 61 (first partial semiconductor layer 61 a ) and the gate electrode 64 .
  • the anode coupling electrode 24 is electrically coupled to the drive transistor DRT and disposed overlapping at least the anode power supply line L 1 .
  • the second capacitance Cs 2 (refer to FIG. 3 ) is formed between the anode coupling electrode 24 and the group of the anode power supply line L 1 and the various wires coupled to the anode power supply line L 1 .
  • the second capacitance Cs 2 formed in the second pixel 49 Ga is smaller than the second capacitance Cs 2 formed in the third pixel 49 Gb.
  • the area of the anode coupling electrode 24 provided in the second pixel 49 Ga is smaller than that of the anode coupling electrode 24 provided in the third pixel 49 Gb.
  • the second capacitance Cs 2 is approximately 150 fF, for example.
  • the second capacitance Cs 2 is approximately 250 fF, for example.
  • the drive transistor DRT and the output transistor BCT that supply the drive current to the light emitting element 3 according to the present embodiment has a single-gate structure.
  • the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST have a double-gate structure. This configuration can reduce current leakage in the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST.
  • FIG. 5 is a sectional view along line V-V′ of FIG. 4 .
  • FIG. 6 is a sectional view along line VI-VI′ of FIG. 4 .
  • FIG. 6 schematically illustrates the cathode wiring 60 and a transistor Tr provided in the peripheral region GA.
  • the array substrate 2 includes the substrate 21 , various transistors, various kinds of wiring, and various insulating films.
  • the substrate 21 is an insulating substrate, such as a glass substrate, a resin substrate, or a resin film.
  • a direction from the substrate 21 to a flattening film 27 in a direction perpendicular to the surface of the substrate 21 is referred to as an “upper side”.
  • a direction from the flattening film 27 to the substrate 21 is referred to as a “lower side”.
  • the drive transistor DRT, the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST are provided on a first surface of the substrate 21 .
  • Various layers are stacked on the first surface of the substrate 21 in order of an undercoat film 90 , the gate lines, the first insulating film 91 , the semiconductor layers 61 , 65 , 71 , and 75 , a second insulating film 92 , the signal lines and the power supply lines, a third insulating film 93 , the anode coupling electrode 24 and a shield electrode 26 , and a fourth insulating film 94 .
  • the anode electrode 23 and the light emitting element 3 are provided on the anode coupling electrode 24 and the shield electrode 26 with a fourth insulating film 94 interposed therebetween.
  • the array substrate 2 includes the layers from the substrate 21 to the anode electrode 23 .
  • the array substrate 2 does not include the flattening film 27 , the cathode electrode 22 , or the light emitting element 3 .
  • the undercoat film 90 , the first insulating film 91 , the second insulating film 92 , and the fourth insulating film 94 are made of inorganic insulating material, such as a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxynitride film (SiON).
  • inorganic insulating material such as a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxynitride film (SiON).
  • SiO silicon oxide film
  • SiN silicon nitride film
  • SiON silicon oxynitride film
  • the third insulating film 93 and the flattening film 27 are organic insulating films or inorganic-organic hybrid insulating films (made of material in which an organic group (a methyl group or a phenyl group) is bonded to a main chain of Si—O, for example).
  • the gate electrodes 64 , 66 , 74 , and 78 are provided on the substrate 21 with the undercoat film 90 interposed therebetween.
  • the first insulating film 91 is provided on the undercoat film 90 to cover the gate electrodes 64 , 66 , 74 , and 78 .
  • the semiconductor layers 61 , 65 , 71 , and 75 are provided on the first insulating film 91 .
  • the second insulating film 92 is provided on the first insulating film 91 to cover the semiconductor layers 61 , 65 , 71 , and 75 .
  • the transistors have what is called a bottom-gate structure.
  • the transistors may have a top-gate structure in which the gate electrode is provided on the semiconductor layer.
  • the transistors may have a dual-gate structure in which the gate electrodes are provided both on and under the semiconductor layer.
  • the coupling wiring L 9 , the source electrodes 62 and 72 , and a drain electrode 67 are provided on the second insulating film 92 .
  • the source electrode 62 is electrically coupled to the first partial semiconductor layer 61 a (semiconductor layer 61 ) through a contact hole formed in the second insulating film 92 .
  • the drain electrode 67 is electrically coupled to the semiconductor layer 65 through a contact hole formed in the second insulating film 92 .
  • the source electrode 72 of the initialization transistor IST is electrically coupled to the semiconductor layer 71 through a contact hole formed in the second insulating film 92 .
  • One end of the coupling wiring L 9 is electrically coupled to the semiconductor layer 75 of the pixel selection transistor SST through a contact hole formed in the second insulating film 92 .
  • the part of the coupling wiring L 9 overlapping the semiconductor layer 75 functions as a drain electrode 77 .
  • the other end of the coupling wiring L 9 is electrically coupled to the semiconductor layer 71 of the initialization transistor IST through a contact hole formed in the second insulating film 92 .
  • the part of the coupling wiring L 9 overlapping the semiconductor layer 71 functions as a drain electrode 73 .
  • the third insulating film 93 is provided on the second insulating film 92 to cover the source electrodes 62 and 72 and the drain electrodes 67 , 73 , and 77 .
  • the anode coupling electrode 24 and the shield electrode 26 are provided on the third insulating film 93 .
  • the anode coupling electrode 24 is coupled to the source electrode 62 through a contact hole formed in the third insulating film 93 .
  • the shield electrode 26 is provided under the anode electrode 23 and the light emitting element 3 .
  • the fourth insulating film 94 is provided on the third insulating film 93 to cover the anode coupling electrode 24 and the shield electrode 26 .
  • the anode electrode 23 is provided on the fourth insulating film 94 .
  • the anode electrode 23 is electrically coupled to the anode coupling electrode 24 through a contact hole formed in the fourth insulating film 94 .
  • the light emitting element 3 is provided on the anode electrode 23 , and the anode terminal 23 t of the light emitting element 3 is coupled to the anode electrode 23 .
  • the anode terminal 23 t of the light emitting element 3 is electrically coupled to the source electrode 62 of the drive transistor DRT.
  • the flattening film 27 is provided on the fourth insulating film 94 to cover at least side surfaces 3 a of the light emitting element 3 .
  • the cathode electrode 22 is provided on the flattening film 27 and coupled to the cathode terminal 22 t of the light emitting element 3 .
  • the cathode electrode 22 is provided from the display region AA to the peripheral region GA and electrically coupled to the light emitting elements 3 of a plurality of pixels 49 .
  • the peripheral region GA of the substrate 21 is provided with the transistors serving as a plurality of transistors Tr included in the drive circuits 12 (refer to FIG. 1 ) and the cathode wiring 60 .
  • the cathode wiring 60 is provided in the same layer as that of the anode power supply line L 1 and provided on the second insulating film 92 in the peripheral region GA.
  • the cathode electrode 22 illustrated in FIG. 5 is electrically coupled to the cathode wiring 60 through a contact hole formed in the third insulating film 93 , the fourth insulating film 94 , and the flattening film 27 .
  • the cathode power supply line L 10 illustrated in FIG. 3 includes the cathode wiring 60 and the cathode electrode 22 .
  • the transistor Tr includes a semiconductor layer 81 , a source electrode 82 , a drain electrode 83 , and a gate electrode 84 .
  • the semiconductor layer 81 is provided on the first insulating film 91 , that is, in the same layer as that of the semiconductor layers 61 , 65 , 71 , 75 , and 79 .
  • the transistor Tr may be provided in a layer different from that of the transistors of the pixel 49 .
  • the anode power supply line L 1 , the video signal line L 2 , and the reset power supply line L 3 are provided on the second insulating film 92 .
  • the width of the anode power supply line L 1 is greater than those of the video signal line L 2 and the reset power supply line L 3 .
  • the thickness t 2 of the anode power supply line L 1 is greater than the thickness t 1 (refer to FIG. 5 ) of the gate electrode 64 .
  • the thickness t 2 of the anode power supply line L 1 is equal to the thickness of the video signal line L 2 and the reset power supply line L 3 . This configuration can reduce the resistance of the anode power supply line L 1 .
  • the thickness t 2 of the anode power supply line L 1 may be different from the thickness of the video signal line L 2 and the reset power supply line L 3 .
  • the layer configuration of the wiring can be appropriately modified.
  • the anode power supply line L 1 may be provided in a layer different from that of the signal lines, such as the video signal line L 2 , and the reset power supply line L 3 .
  • the capacitance formed between the anode power supply line L 1 and the various gate lines is used as a decoupling capacitor.
  • the decoupling capacitor can accommodate fluctuations in the anode power supply potential PVDD and enable the drive IC 210 to stably operate.
  • the decoupling capacitor can hamper electromagnetic noise generated in the display device 1 from leaking outside.
  • the configuration of the pixel circuit PICA illustrated in FIG. 3 can be appropriately modified.
  • the number of wiring lines and the number of transistors in one pixel 49 may be different from those illustrated in FIG. 3 , for example.
  • FIG. 7 is a sectional view of the red light emitting element according to the embodiment.
  • the red light emitting element 3 R has what is called a face-up structure in which the anode terminal 23 t is provided at the lower part and the cathode terminal 22 t is provided at the upper part.
  • the red light emitting element 3 R includes a plurality of partial light emitting elements 3 s , a protective layer 39 , a p-type electrode 37 , and an n-type electrode 38 .
  • the protective layer 39 covers the partial light emitting elements 3 s .
  • the partial light emitting elements 3 s have a columnar shape and are provided between the p-type electrode 37 and the n-type electrode 38 .
  • the partial light emitting elements 3 s each include an n-type cladding layer 33 , a light emitting layer 34 , and a p-type cladding layer 35 .
  • the n-type electrode 38 is electrically coupled to the n-type cladding layer 33 .
  • the p-type electrode 37 is electrically coupled to the p-type cladding layer 35 .
  • the p-type cladding layer 35 , the light emitting layer 34 , and the n-type cladding layer 33 are stacked on the p-type electrode 37 in the order as listed.
  • the n-type cladding layer 33 includes a first n-type cladding layer 33 a and a second n-type cladding layer 33 b .
  • the second n-type cladding layer 33 b and the first n-type cladding layer 33 a are stacked on the light emitting layer 34 in the order as listed.
  • the first n-type cladding layer 33 a is made of n-type gallium nitride (n-GaN), for example.
  • the second n-type cladding layer 33 b is made of n-type aluminum gallium nitride (n-AlGaN), for example.
  • the p-type cladding layer 35 includes a first p-type cladding layer 35 a and a second p-type cladding layer 35 b .
  • the first p-type cladding layer 35 a and the second p-type cladding layer 35 b are stacked on the p-type electrode 37 in the order as listed.
  • the light emitting layer 34 is provided between the second p-type cladding layer 35 b and the second n-type cladding layer 33 b .
  • the first p-type cladding layer 35 a is made of p-type gallium nitride (p-GaN), for example.
  • the second p-type cladding layer 35 b is made of p-type aluminum gallium nitride (p-AlGaN), for example.
  • the light emitting layer 34 of the red light emitting element 3 R is made of GaN to which europium (Eu) is added. As a result, the red light emitting element 3 R has higher luminous efficacy of red light.
  • the n-type electrode 38 is made of translucent conductive material, such as ITO.
  • the n-type electrode 38 serves as the cathode terminal 22 t of the red light emitting element 3 R and is coupled to the cathode electrode 22 .
  • the p-type electrode 37 serves as the anode terminal 23 t of the red light emitting element 3 R and includes a Pt layer 37 a and a thick Au layer 37 b produced by plating.
  • the thick Au layer 37 b is coupled to a placement surface 23 a of the anode electrode 23 .
  • the protective layer 39 is a spin on glass (SOG) layer, for example.
  • the side surfaces of the protective layer 39 correspond to the side surfaces 3 a of the red light emitting element 3 R.
  • the flattening film 27 is provided surrounding the side surfaces of the protective layer 39 .
  • a plurality of partial light emitting elements 3 s each include the light emitting layer 34 .
  • the state of Eu added to GaN can differ between the partial light emitting elements 3 s .
  • the amount of added Eu differs between the partial light emitting elements 3 s .
  • the red light emitting element 3 R has a greater half width of a spectrum SPR of light (refer to FIG. 8 ).
  • the first green light emitting element 3 Ga, the second green light emitting element 3 Gb, and the blue light emitting element 3 B have the same sectional structure.
  • the n-type cladding layer 33 and the p-type cladding layer 35 are made of indium gallium nitride (InGaN), for example.
  • the light emitting layer 34 includes a multi-quantum well structure (MQW structure) in which indium gallium nitride (In x Ga (1-x) N) layers and GaN layers are repeatedly stacked.
  • MQW structure multi-quantum well structure
  • FIG. 8 is a graph schematically illustrating the relation between the emission intensity and the wavelength of each of the red light emitting element and the first green light emitting element.
  • FIG. 8 illustrates the spectrum SPR of light output from the red light emitting element 3 R and spectra SPG- 1 , SPG- 2 , and SPG- 3 of light output from the first green light emitting element 3 Ga.
  • the spectra SPG- 1 , SPG- 2 , and SPG- 3 indicate spectra of light obtained when the drive currents having different magnitude are supplied to the first green light emitting element 3 Ga.
  • the magnitude of the drive current decreases in order of the spectra SPG- 1 , SPG- 2 , and SPG- 3 .
  • the maximum emission wavelength of the spectrum SPR is approximately 620 nm, and the maximum emission wavelength of the spectrum SPG- 1 is approximately 520 nm.
  • the red light emitting element 3 R according to the present embodiment has higher luminous efficacy (emission intensity) because the light emitting layer 34 of the red light emitting element 3 R is made of GaN to which Eu is added.
  • the half width of the spectrum SPR is less than those of the spectra SPG- 1 , SPG- 2 , and SPG- 3 .
  • the emission intensity of the spectra SPG- 2 and SPG- 3 of the first green light emitting element 3 Ga is lower than that of the red light emitting element 3 R.
  • the maximum emission wavelengths of the spectra SPG are closer to that of the spectrum SPR in order of the spectra SPG- 1 , SPG- 2 , and SPG- 3 .
  • FIG. 8 illustrates the spectra SPG- 1 , SPG- 2 , and SPG- 3 of first green light output from the first green light emitting element 3 Ga.
  • the second green light emitting element 3 Gb may have the same configuration as that of the first green light emitting element 3 Ga.
  • the spectra of the second green light output from the second green light emitting element 3 Gb have the same characteristics as those of the spectra SPG- 1 , SPG- 2 , and SPG- 3 .
  • the pixel Pix displays red light by simultaneously turning on the red light emitting element 3 R and the first green light emitting element 3 Ga and combining light output from the red light emitting element 3 R and light output from the first green light emitting element 3 Ga.
  • the first green light emitting element 3 Ga is supplied with a drive current lower than those supplied to the second green light emitting element 3 Gb and the red light emitting element 3 R.
  • the first green light emitting element 3 Ga outputs light having an intensity distribution indicated by the spectrum SPG- 2 or SPG- 3 .
  • the second green light emitting element 3 Gb is driven independently of the first green light emitting element 3 Ga and outputs light having an intensity distribution indicated by the spectrum SPG- 1 .
  • the emission intensity of the first green light emitting element 3 Ga is lower than that of the red light emitting element 3 R, and the half width of the spectrum (e.g., the spectrum SPG- 2 or SPG- 3 ) of light output from the first green light emitting element 3 Ga is greater than that of the spectrum SPR of light output from the red light emitting element 3 R.
  • the emission intensity of the second green light emitting element 3 Gb is higher than that of the first green light emitting element 3 Ga.
  • the maximum emission wavelength of the spectrum (e.g., the spectrum SPG- 2 or SPG- 3 ) of light output from the first green light emitting element 3 Ga is longer than that of the spectrum (e.g., the spectrum SPG- 1 ) of light output from the second green light emitting element 3 Gb and shorter than that of the spectrum SPR of light output from the red light emitting element 3 R.
  • the distribution of the wavelength of red light is substantially widened as compared with the case where red is displayed by only the red light emitting element 3 R.
  • This mechanism reduces the difference between the half width of red light obtained by combining light output from the red light emitting element 3 R and light output from the first green light emitting element 3 Ga and both the half width of green light output from the second green light emitting element 3 Gb and the half width of blue light output from the blue light emitting element 3 B. Consequently, the display device 1 can hamper only red from being vividly displayed in a certain image, thereby satisfactorily displaying images.
  • FIG. 9 is a block diagram schematically illustrating the configuration of a signal processing circuit.
  • FIG. 10 is a diagram for explaining the relation between the input gradation value and the light emitting element to be driven.
  • a signal processing circuit 100 includes a first processing circuit 110 , a memory 115 , and a buffer 125 .
  • the signal processing circuit 100 calculates output gradation values SoR, SoGa, SoGb, and SoB of the respective four pixels 49 based on the video signals Vsig.
  • the video signals Vsig include input gradation values SiR, SiG, and SiB of each pixel Pix.
  • the input gradation values SiR, SiG, and SiB are gradation values of red, green, and blue, respectively.
  • the output gradation value SoR is a gradation value corresponding to the first pixel 49 R.
  • the output gradation value SoGa is a gradation value corresponding to the second pixel 49 Ga.
  • the output gradation value SoGb is a gradation value corresponding to the third pixel 49 Gb.
  • the output gradation value SoB is a gradation value corresponding to the fourth pixel 49 B.
  • the signal processing circuit 100 may be included in the drive IC 210 illustrated in FIG. 1 or provided on the substrate 21 as another circuit chip different from the drive IC 210 , for example.
  • the output gradation values SoR, SoGa, SoGb, and SoB are referred to as output gradation values So when they need not be distinguished from one another.
  • the input gradation values SiR, SiG, and SiB are referred to as input gradation values Si when they need not be distinguished from one another.
  • the buffer 125 is a circuit that stores therein the input gradation values Si.
  • the buffer 125 may store therein the input gradation values Si included in the video signals Vsig of one frame or acquire the input gradation values Si included in part of the video signals Vsig of one frame.
  • the memory 115 includes data LUT indicating information on the relation between the input gradation values SiR, SiG, and SiB and the output gradation values SoR, SoGa, SoGb, and SoB of the respective four pixels 49 .
  • the data LUT is table data, such as a look-up table.
  • a range where the input gradation value SiR is 0 to a first threshold Lth (refer to FIG. 10 ) is associated with the output gradation value SoR for turning on only the red light emitting element 3 R.
  • the output gradation value SoGa is 0 (gradation value of 0).
  • a range where the input gradation value SiR is larger than the first threshold Lth and smaller than a second threshold Hth (refer to FIG. 10 ) is associated with the output gradation values SoR and SoGa for turning on both the red light emitting element 3 R and the first green light emitting element 3 Ga.
  • the second threshold Hth is a gradation value larger than the first threshold Lth.
  • a range where the input gradation value SiR is equal to or larger the second threshold Hth is associated with the output gradation values SoR and SoGa for turning on only the red light emitting element 3 R.
  • the output gradation value SoGa is 0 (gradation value of 0).
  • the first processing circuit 110 refers to the data LUT read from the memory 115 and identifies the output gradation values SoR, SoGa, SoGb, and SoB corresponding to the input gradation values SiR, SiG, and SiB.
  • the first processing circuit 110 outputs the output gradation values SoR, SoGa, SoGb, and SoB to the pixel Pix.
  • the pixels 49 are each turned on based on the output gradation values SoR, SoGa, SoGb, and SoB.
  • the red light emitting element 3 R is turned on, and the first green light emitting element 3 Ga is not turned on based on the output gradation values SoR and SoGa.
  • both the red light emitting element 3 R and the first green light emitting element 3 Ga are turned on based on the output gradation values SoR and SoGa.
  • the first green light emitting element 3 Ga is turned on in intermediate-gradation of red.
  • the input gradation value SiR is equal to or larger than the second threshold Hth, only the red light emitting element 3 R is turned on, and the first green light emitting element 3 Ga is not turned on.
  • both the red light emitting element 3 R and the first green light emitting element 3 Ga are turned on, whereby an image is satisfactorily displayed. This mechanism can hamper an increase in the drive current supplied to the first green light emitting element 3 Ga. Consequently, the capacitance Cs 2 formed in the second pixel 49 Ga can be made smaller than that formed in the other pixels 49 .
  • FIG. 11 is a flowchart for explaining the method for setting the output gradation values of the light emitting elements.
  • the signal processing circuit 100 calculates the output gradation values SoR, SoGa, SoGb, and SoB based on the predetermined data LUT; however, the present embodiment is not limited thereto.
  • the signal processing circuit 100 acquires an image of one frame (Step ST 1 ).
  • the buffer 125 acquires the video signals Vsig of one frame and stores therein the input gradation values SiR, SiG, and SiB corresponding to red, green, and blue, respectively.
  • the first processing circuit 110 determines whether the input gradation value SiR is larger than 0 for each pixel Pix (Step ST 2 ). In other words, the first processing circuit 110 determines whether to display red for each pixel Pix. If the input gradation value SiR is 0 (No at Step ST 2 ), the first processing circuit 110 sets a gradation value of 0 as the output gradation values SoR and SoGa (Step ST 3 ). A gradation value of 0 is a gradation value for bringing the pixel Pix into an OFF state. The set output gradation values SoR and SoGa are output to the pixel Pix, thereby bringing the red light emitting element 3 R and the first green light emitting element 3 Ga into the OFF state.
  • the first processing circuit 110 compares the input gradation value SiR with the first threshold Lth and the second threshold Hth (Step ST 4 ).
  • the first processing circuit 110 sets the output gradation values SoR and SoGa for turning on only the red light emitting element 3 R (Step ST 5 ). More specifically, the first processing circuit 110 sets a value larger than 0 (gradation value SioR) based on the input gradation value SiR as the output gradation value SoR and sets a gradation value of 0 as the output gradation value SoGa.
  • the set output gradation values SoR and SoGa are output to the pixel Pix, thereby turning on the red light emitting element 3 R and bringing the first green light emitting element 3 Ga into the OFF state.
  • the first processing circuit 110 sets the output gradation values SoR and SoGa for turning on the red light emitting element 3 R and the first green light emitting element 3 Ga (Step ST 6 ). More specifically, the first processing circuit 110 sets a value larger than 0 (gradation value SioRa) based on the input gradation value SiR as the output gradation value SoR and sets a gradation value SioGa based on the input gradation value SiR as the output gradation value SoGa. The gradation value SioGa is larger than 0.
  • the set output gradation values SoR and SoGa are output to the pixel Pix, thereby turning on the red light emitting element 3 R and the first green light emitting element 3 Ga.
  • the first processing circuit 110 determines whether the input gradation value SiG is larger than 0 (Step ST 7 ). In other words, the first processing circuit 110 determines whether to display green. If the input gradation value SiG is 0 (No at Step ST 7 ), the first processing circuit 110 sets a gradation value of 0 as the output gradation value SoGb (Step ST 8 ). The set output gradation value SoGb is output to the pixel Pix, thereby bringing the second green light emitting element 3 Gb into the OFF state.
  • the first processing circuit 110 sets a gradation value (gradation value SioGb) based on the input gradation value SiG as the output gradation value SoG (Step ST 9 ).
  • the set output gradation value SoGb is output to the pixel Pix, thereby turning on the second green light emitting element 3 Gb.
  • the first processing circuit 110 determines whether the input gradation value SiB is larger than 0 (Step ST 10 ). In other words, the first processing circuit 110 determines whether to display blue. If the input gradation value SiB is 0 (No at Step ST 10 ), the first processing circuit 110 sets a gradation value of 0 as the output gradation value SoB (Step ST 11 ). The set output gradation value SoB is output to the pixel Pix, thereby bringing the blue light emitting element 3 B into the OFF state.
  • the first processing circuit 110 sets a gradation value (gradation value SioB) based on the input gradation value SiB as the output gradation value SoB.
  • the set output gradation value SoB is output to the pixel Pix, thereby turning on the blue light emitting element 3 B (Step ST 12 ).
  • the first processing circuit 110 determines whether the output gradation values SoR, SoGa, SoGb, and SoB of all the pixels Pix of one frame are set (Step ST 13 ). If the output gradation values So of all the pixels Pix are not set (No at Step ST 13 ), the first processing circuit 110 performs the process starting from Step ST 2 on the next pixel Pix. If the output gradation values So of all the pixels Pix are set (Yes at Step ST 13 ), the first processing circuit 110 ends the setting of the output gradation values So.
  • the output gradation values SoR, SoGa, SoGb, and SoB are output to the pixels Pix, and the light emitting elements 3 disposed in the pixels Pix are controlled to be turned on based on the set output gradation values SoR, SoGa, SoGb, and SoB.
  • the set output gradation values So may be output to the pixels Pix after setting the output gradation values So of all the pixels of one frame is completed or after setting the output gradation values So of a pixel group of one line coupled to the common gate line is completed.
  • the output gradation values So may be sequentially output to each pixel Pix in the order in which its output gradation values So are set.
  • FIG. 12 is a block diagram schematically illustrating the configuration of the signal processing circuit according to a second modification.
  • FIG. 13 is a flowchart for explaining the method for setting the output gradation values of the light emitting elements according to the second modification.
  • a signal processing circuit 100 A further includes a second processing circuit 120 .
  • two pixels Pix adjacent to each other are referred to as a first pixel group Pix 1 (first pixel) and a second pixel group Pix 2 (second pixel).
  • the signal processing circuit 100 A turns on the pixels 49 of the first pixel group Pix 1 and one or some of the pixels 49 of the second pixel group Pix 2 based on the input gradation values SiR, SiG, and SiB of the first pixel group Pix 1 .
  • the first processing circuit 110 performs the same process as that illustrated in FIG. 11 and outputs the output gradation values SoR, SoGa 1 , SoGb, and SoB to the second processing circuit 120 .
  • the second processing circuit 120 compares the drive current corresponding to the output gradation value SoGa 1 received from the first processing circuit 110 with a predetermined threshold current and sets an output gradation value SoGa 2 based on the comparison result.
  • the signal processing circuit 100 A outputs the set output gradation value SoGa 2 to the pixel Pix.
  • the second processing circuit 120 calculates the drive current to be supplied to the first green light emitting element 3 Ga of the first pixel group Pix 1 based on the output gradation value SoGa 1 .
  • the second processing circuit 120 sets the output gradation value SoGa 2 such that the drive current of the first green light emitting element 3 Ga does not exceed the predetermined threshold current. More specifically, if the drive current exceeds the predetermined threshold current, the second processing circuit 120 divides the output gradation value SoGa 1 into a reference gradation value SotGa and a retention gradation value SorGa and sets the reference gradation value SotGa as the output gradation value SoGa 2 .
  • the reference gradation value SotGa is a gradation value corresponding to the threshold current or the drive current equal to or lower than the threshold current.
  • the reference gradation value SotGa is set as the output gradation value SoGa 2 and output to a first green light emitting element 3 Ga 1 of the first pixel group Pix 1 .
  • the retention gradation value SorGa is input to the memory 115 .
  • the second processing circuit 120 sets the output gradation value SoGa 2 based on the retention gradation value SorGa and the gradation value SioGa based on the input gradation value SiR of the second pixel group Pix 2 .
  • the output gradation value SoGa 2 is set such that the luminance obtained when the first green light emitting element 3 Ga 1 is caused to emit light with the output gradation value SioGa is substantially equal to the luminance obtained when the first green light emitting element 3 Ga 1 and the first green light emitting element 3 Ga 2 of the second pixel group Pix 2 are caused to emit light with the reference gradation value SotGa and the retention gradation value SorGa.
  • the output gradation value SoGa 2 for the first green light emitting element 3 Ga 2 of the second pixel group Pix 2 is set based on the gradation value SioGa based on the input gradation value SiR of the second pixel group Pix 2 and on the retention gradation value SorGa obtained by dividing the gradation value SioGa based on the input gradation value SiR of the first pixel group Pix 1 .
  • the second processing circuit 120 receives the output gradation value SoGa 1 from the first processing circuit 110 and determines whether the retention gradation value SorGa is retained in the memory 115 (Step ST 31 ). If the retention gradation value SorGa is retained in the memory 115 (Yes at Step ST 31 ), the second processing circuit 120 sets the retention gradation value SorGa as the output gradation value SoGa 2 (Step ST 32 ).
  • the set output gradation value SoGa 2 is output to the pixel Pix, thereby turning on the first green light emitting element 3 Ga included in the pixel Pix. If the retention gradation value SorGa is not retained in the memory 115 (No at Step ST 31 ), the second processing circuit 120 sets the output gradation value SoGa 1 (gradation value of 0) as the output gradation value SoGa 2 (Step ST 33 ). The set output gradation value SoGa 2 is output to the pixel Pix, thereby bringing the first green light emitting element 3 Ga included in the pixel Pix into the OFF state.
  • the second processing circuit 120 receives the output gradation value SoGa 1 from the first processing circuit 110 and determines whether the retention gradation value SorGa is retained in the memory 115 (Step ST 34 ). If the retention gradation value SorGa is retained in the memory 115 (Yes at Step ST 34 ), the second processing circuit 120 adds the retention gradation value SorGa to the output gradation value SoGa 1 (gradation value SioGa based on the input gradation value SiR) (Step ST 35 ).
  • the second processing circuit 120 determines whether the drive current corresponding to the output gradation value SoGa 1 (gradation value SioGa) is equal to or lower than the threshold current (Step ST 36 ).
  • the second processing circuit 120 sets the output gradation value SoGa 1 as the output gradation value SoGa 2 (Step ST 37 ).
  • the set output gradation value SoGa 2 is output to the pixel Pix, thereby turning on the first green light emitting element 3 Ga included in the pixel Pix.
  • the second processing circuit 120 determines whether the drive current corresponding to the output gradation value SoGa 1 to which the retention gradation value SorGa is added (gradation value SioGa+retention gradation value SorGa) is equal to or lower than the threshold current (Step ST 36 ). If the drive current corresponding to the output gradation value SoGa 1 is equal to or lower than the threshold current (Yes at Step ST 36 ), the second processing circuit 120 sets the output gradation value SoGa 1 to which the retention gradation value SorGa is added, as the output gradation value SoGa 2 (Step ST 37 ).
  • the set output gradation value SoGa 2 is output to the pixel Pix, thereby turning on the first green light emitting element 3 Ga included in the pixel Pix at the gradation corresponding to the output gradation value SoGa 1 to which the retention gradation value SorGa is added.
  • the second processing circuit 120 sets the reference gradation value SotGa smaller than the output gradation value SoGa 1 (gradation value SioGa) as the output gradation value SoGa 2 (Step ST 38 ). More specifically, the second processing circuit 120 calculates the reference gradation value SotGa and the retention gradation value SorGa based on the output gradation value SoGa 1 and sets the reference gradation value SotGa as the output gradation value SoGa 2 .
  • the second processing circuit 120 records the retention gradation value SorGa in the memory 115 (Step ST 39 ).
  • the set output gradation value SoGa 2 is output to the pixel Pix, thereby turning on the first green light emitting element 3 Ga included in the pixel Pix.
  • Step ST 35 After the processing at Step ST 35 is completed, if the drive current corresponding to the output gradation value SoGa 1 to which the retention gradation value SorGa is added (gradation value SioGa+retention gradation value SorGa) is higher than the threshold current (No at Step ST 36 ), the second processing circuit 120 sets the reference gradation value SotGa smaller than the output gradation value SoGa 1 to which the retention gradation value SorGa is added, as the output gradation value SoGa 2 (Step ST 38 ).
  • the second processing circuit 120 calculates the reference gradation value SotGa and the retention gradation value SorGa based on the output gradation value SoGa 1 to which the retention gradation value SorGa is added and sets the reference gradation value SotGa as the output gradation value SoGa 2 (Step ST 38 ).
  • the second processing circuit 120 records the retention gradation value SorGa in the memory 115 (Step ST 39 ).
  • the set output gradation value SoGa 2 is output to the pixel Pix, thereby turning on the first green light emitting element 3 Ga included in the pixel Pix.
  • the signal processing circuit 100 A After the processing at Step ST 32 , ST 33 , ST 37 , or ST 39 is completed, the signal processing circuit 100 A performs the processing from Step ST 7 to Step ST 13 in the same manner as the procedure illustrated in FIG. 11 .
  • the execution order of Steps ST can be appropriately modified, and the signal processing circuit 100 A may simultaneously perform the processing at Step ST 38 and Step ST 39 or perform the processing at Step ST 39 before the processing at Step ST 38 , for example. While the signal processing circuit 100 A compares the drive current corresponding to the output gradation value SoGa 1 with the threshold current at Step ST 36 , the present modification is not limited thereto.
  • the signal processing circuit 100 A may record the reference gradation value SotGa corresponding to the threshold current and determine whether the output gradation value SoGa 1 is equal to or smaller than the reference gradation value SotGa.
  • the reference gradation value SotGa may be a value common to all the pixels Pix or be a different value for each pixel Pix.
  • the first green light emitting element 3 Ga of the first pixel group Pix 1 is turned on with the output gradation value (reference gradation value SotGa) smaller than a gradation value SioGa 1 corresponding to the input gradation value SiR, and the retention gradation value SorGa is retained.
  • the second modification adds the retention gradation value SorGa, thereby turning on the first green light emitting element 3 Ga with the output gradation value (gradation value SioGa 2 +retention gradation value SorGa) larger than the gradation value SioGa 2 corresponding to the input gradation value SiR. Consequently, the two first green light emitting elements 3 Ga of the first pixel group Pix 1 and the second pixel group Pix 2 disposed adjacent to each other maintain the total emission intensity, and the drive current flowing through the first green light emitting element 3 Ga of the first pixel group Pix 1 can be reduced. As a result, the present modification can hamper the maximum emission wavelength of the spectrum SPG- 3 of light output from the first green light emitting element 3 Ga illustrated in FIG. 8 , for example, from shifting away from the wavelength region of the red light emitting element 3 R.
  • FIG. 14 is a flowchart for explaining the method for setting the output gradation values of the light emitting elements according to a third modification. While the first processing circuit 110 performs the processing from Step ST 22 to Step ST 26 , and the second processing circuit 120 performs the processing from Step ST 31 to Step ST 39 in the second modification, the present embodiment is not limited thereto. The processing performed by the first processing circuit 110 and that performed by the second processing circuit 120 may be switched. In the third modification, the first processing circuit 110 determines whether the retention gradation value SorGa is retained in the memory 115 . Descriptions common to the second modification are omitted at Steps ST.
  • the first processing circuit 110 acquires the input gradation values Si of one frame (Step ST 121 ) and determines whether the retention gradation value SorGa is retained in the memory 115 (Step ST 122 ). If the retention gradation value SorGa is not retained in the memory 115 (No at Step ST 122 ), the first processing circuit 110 performs the same processing as that from Step ST 2 to Step ST 6 in FIG. 11 .
  • the first processing circuit 110 sets a gradation value of 0 as the output gradation value SoGa 2 without the second processing circuit 120 (Steps ST 124 and ST 126 ).
  • the first processing circuit 110 outputs, to the second processing circuit 120 , the gradation value SioGa based on the input gradation value SiR as the output gradation value SoGa 1 (Step ST 127 ).
  • the first processing circuit 110 adds the retention gradation value SorGa and performs the same processing as that from Step ST 123 to Step ST 127 . Specifically, if the input gradation value SiR is 0 (No at Step ST 128 ) or if the input gradation value SiR is equal to or smaller than the first threshold Lth or equal to or larger than the second threshold Hth (Yes at Step ST 130 ), the first processing circuit 110 sets the retention gradation value SorGa as the output gradation value SoGa 2 without the second processing circuit 120 (Steps ST 129 and ST 131 ).
  • the first processing circuit 110 outputs, to the second processing circuit 120 , a value obtained by adding the retention gradation value SorGa to the gradation value SioGa based on the input gradation value SiR as the output gradation value SoGa 1 (Step ST 132 ).
  • the second processing circuit 120 After receiving the output gradation value SoGa 1 from the first processing circuit 110 (Steps ST 132 and ST 127 ), the second processing circuit 120 performs the same processing as that from Step ST 36 to Step ST 39 in FIG. 13 . Specifically, the second processing circuit 120 determines whether the drive current corresponding to the output gradation value SoGa 1 is equal to or lower than the threshold current (Step ST 133 ). If the drive current corresponding to the output gradation value SoGa 1 is equal to or lower than the threshold current (Yes at Step ST 133 ), the second processing circuit 120 sets the output gradation value SoGa 1 as the output gradation value SoGa 2 (Step ST 134 ).
  • the second processing circuit 120 divides the output gradation value SoGa 1 into the reference gradation value SotGa and the retention gradation value SorGa and sets the reference gradation value SotGa as the output gradation value SoGa 2 (Step ST 135 ).
  • the second processing circuit 120 records the retention gradation value SorGa in the memory 115 (Step ST 136 ).
  • Step ST 124 After the processing at Step ST 124 , ST 126 , ST 129 , ST 131 , ST 134 , or ST 136 is completed, the signal processing circuit 100 A performs the processing from Step ST 7 to Step ST 13 in the same manner as the procedure illustrated in FIG. 11 .
  • the first processing circuit 110 determines whether the retention gradation value SorGa is retained. Consequently, the third modification can complete the processing at part of Steps ST (Steps ST 124 , ST 126 , ST 129 , and ST 131 ) without the second processing circuit 120 , thereby performing the processing in a simpler manner.
  • FIGS. 15A to 15C are plan views of a modification of the arrangement pattern of the light emitting elements in one pixel group.
  • the red light emitting element 3 R, the first green light emitting element 3 Ga, the second green light emitting element 3 Gb, and the blue light emitting element 3 B are disposed in one pixel Pix as illustrated in FIG. 2 ; however, the arrangement pattern of the light emitting elements 3 is not limited thereto.
  • FIG. 15 A is a plan view of a first arrangement pattern of the light emitting elements in one pixel group according to a fourth modification. In a first arrangement pattern AP 1 illustrated in FIG. 15A , the red light emitting element 3 R and the first green light emitting element 3 Ga are disposed in the second direction Dy.
  • the red light emitting element 3 R and the second green light emitting element 3 Gb are disposed in the first direction Dx.
  • the first green light emitting element 3 Ga and the blue light emitting element 3 B are disposed in the first direction Dx.
  • the second green light emitting element 3 Gb and the blue light emitting element 3 B are disposed in the second direction Dy.
  • the first green light emitting element 3 Ga or the second green light emitting element 3 Gb having a wavelength close to that of the red light emitting element 3 R is preferably disposed at a position adjacent to the red light emitting element 3 R in the first direction Dx or the second direction Dy.
  • the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga may be switched, or the positions of the second green light emitting element 3 Gb and the blue light emitting element 3 B may be switched.
  • the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga may be switched, and the positions of the second green light emitting element 3 Gb and the blue light emitting element 3 B may be switched.
  • FIG. 15B is a plan view of a second arrangement pattern of the light emitting elements in one pixel group.
  • the red light emitting element 3 R and the first green light emitting element 3 Ga are disposed in the first direction Dx.
  • the red light emitting element 3 R and the second green light emitting element 3 Gb are disposed in the second direction Dy.
  • the first green light emitting element 3 Ga and the blue light emitting element 3 B are disposed in the second direction Dy.
  • the second green light emitting element 3 Gb and the blue light emitting element 3 B are disposed in the first direction Dx.
  • the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga may be switched, or the positions of the second green light emitting element 3 Gb and the blue light emitting element 3 B may be switched.
  • the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga may be switched, and the positions of the second green light emitting element 3 Gb and the blue light emitting element 3 B may be switched.
  • the first green light emitting element 3 Ga or the second green light emitting element 3 Gb having a wavelength close to that of the red light emitting element 3 R is preferably disposed at a position adjacent to the red light emitting element 3 R in the first direction Dx or the second direction Dy.
  • FIG. 15C is a plan view of a third arrangement pattern of the light emitting elements in one pixel group.
  • the red light emitting element 3 R and the blue light emitting element 3 B are disposed in the first direction Dx.
  • the red light emitting element 3 R and the second green light emitting element 3 Gb are disposed in the second direction Dy.
  • the blue light emitting element 3 B and the first green light emitting element 3 Ga are disposed in the second direction Dy.
  • the second green light emitting element 3 Gb and the first green light emitting element 3 Ga are disposed in the first direction Dx.
  • the red light emitting element 3 R and the first green light emitting element 3 Ga are arrayed in a diagonal direction intersecting both the first direction Dx and the second direction Dy.
  • the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga may be switched, or the positions of the second green light emitting element 3 Gb and the blue light emitting element 3 B may be switched.
  • the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga may be switched, and the positions of the second green light emitting element 3 Gb and the blue light emitting element 3 B may be switched.
  • the red light emitting element 3 R and one of the second green light emitting element 3 Gb and the blue light emitting element 3 B are disposed in the first direction Dx.
  • the red light emitting element 3 R and the other of the second green light emitting element 3 Gb and the blue light emitting element 3 B are disposed in the second direction Dy.
  • FIGS. 16A to 16C are plan views of a modification of the arrangement pattern of the light emitting elements 3 in two pixel groups.
  • the embodiment and the fourth modification have described the arrangement pattern of the light emitting elements 3 . If all the pixels Pix disposed in a matrix (row-column configuration) have one of the arrangement patterns, the red light emitting elements 3 R, the first green light emitting elements 3 Ga, the second green light emitting elements 3 Gb, and the blue light emitting elements 3 B are each disposed in a certain direction. If the pixels likely to be brought into the OFF state, such as the first green light emitting elements 3 Ga, are arrayed in one direction, they may possibly be visually recognized as streaks and unevenness. To address this, in the fifth modification, two kinds of pixels Pix having different arrangement patterns of the light emitting elements 3 are arranged. With this configuration, the fifth modification can hamper streaks and unevenness from being visually recognized.
  • FIG. 16A is a plan view of a fourth arrangement pattern of the light emitting elements in two pixel groups according to a fifth modification.
  • a fourth arrangement pattern AP 4 illustrated in FIG. 16A the first pixel group Pix 1 and the second pixel group Pix 2 disposed in the first direction Dx are different in the arrangement pattern of the light emitting elements 3 .
  • the first pixel group Pix 1 on the left in FIG. 16A has the same arrangement pattern of the light emitting elements 3 as the first arrangement pattern AP 1 illustrated in FIG. 15A .
  • the second pixel group Pix 2 on the right in FIG. 16A has an arrangement pattern obtained by switching the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga in the first pixel group Pix 1 .
  • the positions of the light emitting elements 3 may differ between the pixels Pix.
  • FIG. 16B is a plan view of a fifth arrangement pattern of the light emitting elements in two pixel groups.
  • the first pixel group Pix 1 and the second pixel group Pix 2 have arrangement patterns of the light emitting elements 3 similar to the second arrangement pattern AP 2 illustrated in FIG. 15B .
  • the first pixel group Pix 1 on the left in FIG. 16B has an arrangement pattern obtained by switching the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga and switching the positions of the second green light emitting element 3 Gb and the blue light emitting element 3 B in the second arrangement pattern AP 2 illustrated in FIG. 15B .
  • the second pixel group Pix 2 on the right in FIG. 16B has an arrangement pattern obtained by switching the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga in the first pixel group Pix 1 .
  • FIG. 16C is a plan view of a sixth arrangement pattern of the light emitting elements in two pixel groups.
  • a sixth arrangement pattern AP 6 illustrated in FIG. 16C the first pixel group Pix 1 on the left has the same arrangement pattern of the light emitting elements 3 as the third arrangement pattern AP 3 illustrated in FIG. 15C .
  • the second pixel group Pix 2 on the right in FIG. 16C has an arrangement pattern obtained by switching the positions of the red light emitting element 3 R and the first green light emitting element 3 Ga in the first pixel group Pix 1 .
  • FIG. 17 is a sectional view of a red light emitting element according to a sixth modification.
  • the light emitting element 3 does not necessarily have a face-up structure.
  • the light emitting element 3 may have what is called a face-down structure in which the lower part of the light emitting element 3 is coupled to the anode electrode 23 and the cathode electrode 22 .
  • FIG. 17 illustrates a sectional structure of a red light emitting element 3 Ra out of the light emitting elements 3 .
  • a buffer layer 32 , the n-type cladding layer 33 , the light emitting layer 34 , the p-type cladding layer 35 , and a p-type electrode 36 are layered on a translucent substrate 31 in the order as listed.
  • the translucent substrate 31 is provided at the upper part, and the p-type electrode 36 is provided at the lower part.
  • the surface of the n-type cladding layer 33 facing the cathode electrode 22 has a region exposed from the light emitting layer 34 . This region is provided with an n-type electrode 38 A.
  • the p-type electrode 36 is made of material having metallic luster that reflects light from the light emitting layer 34 .
  • the p-type electrode 36 is coupled to the anode electrode 23 with a bump 39 A interposed therebetween.
  • the n-type electrode 38 A is coupled to the cathode electrode 22 with a bump 39 B interposed therebetween.
  • An insulating film 97 covers the cathode electrode 22 and the anode electrode 23 .
  • the bumps 39 A and 39 B are coupled to the anode electrode 23 and the cathode electrode 22 , respectively, through openings in the insulating film 97 .
  • the p-type cladding layer 35 (second p-type cladding layer 35 b ) and the n-type cladding layer 33 (second n-type cladding layer 33 b ) are not directly bonded, and another layer (light emitting layer 34 ) is interposed therebetween.
  • This configuration can concentrate carriers, such as electrons and holes, in the light emitting layer 34 , thereby efficiently recombining the carriers (emitting light).
  • the light emitting layer 34 of the red light emitting element 3 Ra is made of GaN to which Eu is added.
  • the light emitting layer 34 of the red light emitting element 3 Ra includes a multi-quantum well structure (MQW structure) in which well layers and barrier layers composed of several atomic layers are cyclically stacked.
  • MQW structure multi-quantum well structure
  • the light emitting layer 34 includes GaN to which Eu is added and the MQW structure stacked on the second p-type cladding layer 35 b in the order as listed.
  • the MQW structure In x Ga (1-x) N layers and GaN layers are repeatedly stacked, for example.
  • the stacking order of GaN to which Eu is added and the MQW structure may be reversed.
  • the GaN to which Eu is added may be included in the MQW structure.
  • the MQW structure may include GaN layers to which Eu is added, In x Ga (1-x) N layers, and GaN layers that are repeatedly stacked.
  • the red light emitting element 3 Ra has higher luminous efficacy because it includes GaN to which Eu is added. In addition, the red light emitting element 3 Ra has a greater half width of the spectrum SPR of light because it includes the MQW structure.
  • FIG. 18 is a sectional view of a red light emitting element according to a seventh modification.
  • a red light emitting element 3 Rb according to the seventh modification illustrated in FIG. 18 a first light emitting layer 34 a and a second light emitting layer 34 b of the light emitting layer 34 are provided in the same layer.
  • the first light emitting layer 34 a and the second light emitting layer 34 b are disposed adjacent to each other on the p-type cladding layer 35 .
  • the upper surface of the first light emitting layer 34 a and the upper surface of the second light emitting layer 34 b are in contact with the n-type cladding layer 33 .
  • the lower surface of the first light emitting layer 34 a and the lower surface of the second light emitting layer 34 b are in contact with the p-type cladding layer 35 .
  • the first light emitting layer 34 a is made of GaN to which Eu is added.
  • the second light emitting layer 34 b has the MQW structure in which In x Ga (1-x) N layers and GaN layers are repeatedly stacked.
  • FIG. 19 is a sectional view of a red light emitting element according to an eighth modification.
  • the p-type cladding layer 35 includes a third p-type cladding layer 35 c .
  • the third p-type cladding layer 35 c is provided between the first p-type cladding layer 35 a and the p-type electrode 36 .
  • the third p-type cladding layer 35 c is made of gallium nitride (P + GaN) having a high-concentration impurity region.
  • the light emitting layer 34 is provided between the n-type cladding layer 33 and the group of the third p-type cladding layer 35 c , the first p-type cladding layer 35 a , and the second p-type cladding layer 35 b .
  • GaN to which Eu is added and the MQW structure are stacked as in the sixth modification.
  • FIG. 20 is a sectional view of a red light emitting element according to a ninth modification.
  • a red light emitting element 3 Rd according to the ninth modification includes a plurality of partial light emitting elements 3 s as in the configuration in FIG. 7 .
  • the p-type cladding layer 35 of the red light emitting element 3 Rd includes the third p-type cladding layer 35 c .
  • the third p-type cladding layer 35 c is made of gallium nitride (P + GaN) having a high-concentration impurity region.
  • the third p-type cladding layer 35 c is provided between the first p-type cladding layer 35 a and the p-type electrode 37 .
  • the light emitting layer 34 is provided between the n-type cladding layer 33 and the group of the third p-type cladding layer 35 c , the first p-type cladding layer 35 a , and the second p-type cladding layer 35 b.
  • FIG. 21 is a sectional view of a red light emitting element according to a tenth modification.
  • a red light emitting element 3 Re according to the tenth modification illustrated in FIG. 21 , the first light emitting layer 34 a and the second light emitting layer 34 b of the light emitting layer 34 are stacked on the p-type cladding layer 35 in the order as listed.
  • the stacking order of the first light emitting layer 34 a and the second light emitting layer 34 b may be reversed.
  • the first light emitting layer 34 a is made of GaN to which Eu is added.
  • the second light emitting layer 34 b has the MQW structure in which In x Ga (1-x) N layers and GaN layers are repeatedly stacked.
  • the second light emitting layer 34 b is not necessarily stacked on the first light emitting layer 34 a .
  • the second light emitting layer 34 b may be included in the first light emitting layer 34 a and serve as part of the MQW structure.

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