US10930774B2 - Shielded gate trench MOSFETs with floating trenched gates and channel stop trenched gates in termination - Google Patents

Shielded gate trench MOSFETs with floating trenched gates and channel stop trenched gates in termination Download PDF

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US10930774B2
US10930774B2 US16/512,538 US201916512538A US10930774B2 US 10930774 B2 US10930774 B2 US 10930774B2 US 201916512538 A US201916512538 A US 201916512538A US 10930774 B2 US10930774 B2 US 10930774B2
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trenched
gate
gates
shielded
floating
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US20210020776A1 (en
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Fu-Yuan Hsieh
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Nami Mos Co Ltd
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Nami Mos Co Ltd
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Definitions

  • This invention relates generally to the cell structure and layout structure of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and layout structure for fabricating shielded trench metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with floating trenched gates and channel stop gates in termination.
  • MOSFETs shielded trench metal-oxide-semiconductor-field-effect-transistors
  • a trench metal-oxide-semiconductor-field-effect-transistor (MOSFET) having shielded gate structure in active area is more attractive due to its reduced Cgd (capacitance between gate and drain) in accordance with reduced Qgd (charge between gate and drain) and lower Rsp (Specific on-resistance).
  • Cgd capacitance between gate and drain
  • Qgd charge between gate and drain
  • Rsp Restric on-resistance
  • the termination area is only composed of multiple trenched floating gates (FTG 1 , FTG 2 , and FTG 3 ) between gate contact area (E-F) and scribe line (S.L).
  • FSG 1 , FTG 2 , and FTG 3 gate contact area
  • E-F gate contact area
  • S.L scribe line
  • floating trenched gates may induce positive charge forming multiple P type channeling regions (Pi) along an interface between floating trenched gates and N epitaxial layer (N EPI), causing a leakage path (as illustrated) between drain region and source region through a conductive path formed in scribe line by die sawing. Therefore, an electrical current will directly flow from edge of the termination area to n+ source regions in the active area without being blocked by the floating trenched gates in the termination area.
  • the present invention provides shielded trench MOSFET having shielded gates in active area and floating trenched gates in termination area, specifically, the present invention also introduces channel stop gates in the termination area to prevent formation of a leakage path between drain region and source region.
  • main die area and scribe line area are sometime designed by different parties such as the main die is designed by design house and the scribe line is designed by foundry, the invention may not be feasibly achieved by a single die layout, therefore, the present invention discloses a layout way to make it happen by providing a device consist of at least two trench MOSFETs.
  • the invention features a semiconductor power device layout consisted of at least two shielded trench MOSFETs with each comprises: multiple floating trenched gates formed in parallel in a termination area around outside of an active area, the multiple floating trenched gates all have floating voltage and are surrounded by body regions without having source regions whereon, the multiple floating trenched gates all have trench depth equal to or deeper than junction depth of the body regions; at least one channel stop trenched gate formed in the termination area and around outside of the multiple floating trenched gates, each the channel stop trenched gate is connected to at least one sawing trenched gate which is extended across over a scribe line.
  • the at least one channel stop trenched gate and the at least one sawing trenched gate of each trench MOSFET are all shorted with a drain region after die sawing through the at least one sawing trenched gate for separation of the at least two shielded trench MOSFETs.
  • each of the multiple floating trenched gates in the termination area comprises a single shielded electrode having the same conductive material as the shielded electrode in the active area, and padded by the first type gate oxide.
  • each of the multiple floating trenched gates in the termination area has dual electrodes, which is the same as the shielded trenched gates in the active area.
  • some of the multiple floating trenched gates in the termination area have single shielded electrode while others have dual electrodes.
  • the at least one channel stop trenched gate comprises a single shielded electrode having the same conductive material as the shielded electrode in the active area, and padded by the first type gate oxide.
  • the at least one channel stop trenched gates comprises dual electrodes, which is the same as the shielded trenched gates in the active area.
  • the source regions in the active area have uniform doping concentration and junction depth along the top surface of the epitaxial layer.
  • each of the source regions has a doping concentration of Gaussian-distribution from edge of a trenched source-body contact to an adjacent channel region near the shielded trenched gate, and has junction depth near edge of the trenched source-body contact greater than near the adjacent channel region.
  • the first conductivity type is N type and the second conductivity type is P type. In some other preferred embodiments, the first conductivity type is P type while the second conductivity type is N type.
  • the first type gate oxide has thickness greater than the second type gate oxide
  • the trench MOSFET further comprises at least one first type wide trenched gate filled with the single shielded electrode padded by the first type gate oxide, and extended from the shielded trenched gates for connection of the shielded electrode to the source metal
  • the shielded trenched gates further extend to at least one second type wider trenched gate for connection of the gate electrode to the gate metal, wherein the second type wider trenched gate has the same dual electrodes structure as the shielded trenched gates in the active area but with a greater width
  • the trench MOSFET further comprises a plurality of trenched source-body contacts with each filled with a metal plug, penetrating through the insulation layer, the source regions and extending into the first type body regions, wherein the metal plug is padded by a barrier layer of Ti/TiN or Co/TiN or Ta/TiN, and contacting with the source metal
  • the trench MOSFET further comprises at least a trenched gate electrode contact with
  • FIG. 1A is top view of a trench MOSFET in prior art.
  • FIG. 1B is a cross-sectional view of the trench MOSFET in FIG. 1A .
  • FIG. 2A is a layout structure of a preferred embodiment according to the present invention.
  • FIG. 2B is a cross-sectional view of a preferred embodiment according to the present invention, which is also a preferred A-B-C cross section of FIG. 1A .
  • FIG. 2C is a layout structure of a preferred embodiment according to the present invention.
  • FIG. 3A is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 3B is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 3C is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 3D is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 4A is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 4B is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 4C is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 4D is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 5A is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 5B is a cross-sectional view of another preferred embodiment according to the present invention.
  • FIG. 6A is a dual dies layout of a preferred embodiment according to the present invention.
  • FIG. 6B is a three dies layout of a preferred embodiment according to the present invention.
  • FIG. 6C is a four dies layout of a preferred embodiment according to the present invention.
  • FIG. 2A for a preferred trench MOSFET layout of this invention wherein an termination area surrounding outsider of an area underneath source metal, gate metal pad and gate metal runner, comprises multiple floating trenched gates and at least one channel stop trenched gate, for example, two floating trenched gates (FTG 1 and FTG 2 ) and one channel stop trenched gate (CSTG 1 ) in this embodiment.
  • the channel stop trenched gate CSTG 1 is further connected to two sawing trenched gates SWTG 1 and SWTG 2 cross a Y scribe line (in Y direction). After die sawing, the sawing trenched gates SWTG 1 , SWTG 2 and the channel stop trenched gate CSTG 1 are electrically shorted at scribe line to drain region and body region for prevention of the leakage path formation as discussed above.
  • FIG. 2B is also a preferred A-B-C cross section of FIG. 2A , wherein an N-channel trench MOSFET 200 ′ is formed in an N epitaxial layer 202 onto an N+ substrate 200 with a metal layer on rear side as drain.
  • a plurality of shielded trenched gates 210 and at least one first type trenched gate 211 for shielded electrode contact are formed in an active area, multiple floating trenched gates 212 and at least one channel stop trenched gate 213 are formed in the termination are, at least one second type wide trenched gate 214 for gate contact is formed underneath the gate metal between the active area and the termination area, and at least one sawing trenched gate 215 is formed cross a scribe line.
  • the shielded trenched gates 210 and the second type wide trenched gate 214 are each implemented by comprising a shielded electrode 216 padded by a first type gate oxide 217 in a lower portion and a gate electrode 218 padded by a second type gate oxide 219 in an upper portion, wherein the gate electrode 218 and the shielded electrode 216 are insulated from each other by an inter-electrode insulation layer 220 .
  • the other trenched gates are each implemented by comprising a single shielded electrode 221 padded by the first type gate oxide 217 .
  • the multiple trenched gates 212 each has trench depth equal to or deeper than junction depth of the second type P body regions 224 to maintain breakdown voltage while preventing heavy leakage current.
  • the N-channel trench MOSFET 200 ′ further comprises: a plurality of trenched source-body contacts each filled with a metal plug 225 , penetrating through an insulation layer 226 , the n+ source regions 223 and extending into the first type P body regions 222 , wherein the meal plug 225 is surrounded by a p+ body contact region 227 around its bottom to further reduce the contact resistance; at least a trenched shielded electrode contact filled with a metal pug 228 , penetrating through the insulation layer 226 and extending into the single shielded electrode 221 in the first type wider trenched gate 211 ; at least a trenched gate electrode contact filled with a metal pug 229 , penetrating through the insulation layer 226 and extending into the gate electrode 216 in the second type wider trenched gate 214 ;
  • the N-channel trench MOSFET 200 ′ further comprises a source metal pad 230 and a gate metal 231 (which is a gate metal pad or gate metal runner connecting to the gate
  • the structure does not have n+ source regions between two adjacent trenched floating gates 212 , no current will flow from drain region through channel region to the source regions in the active area even the trenched floating gates 212 are turned on.
  • the at least one channel stop trenched gate 213 is connecting to the at least one sawing trenched gate 215 , wherein the sawing trenched gate 215 is sawed in the Y-scribe line to ensure that the sawing trenched gate 215 and the channel stop trenched gate 213 are both electrically shorted to the N epitaxial layer 202 and to the second type body regions 224 surrounding the sawing trenched gate 215 (illustrated by the black dots connected by lines in FIG. 2B ).
  • the channel stop trenched gate 213 is electrically shorted to the N epitaxial layer 202 , there is no channeling region Pi formed surrounding the channel stop trenched gate 213 below the second type P body region 224 , therefore, the channel stop trenched gate 213 is acted to stop the channeling region for prevention of leakage path formation between the drain region and the source region.
  • the multiple trenched floating gates 212 and the second type P body regions 224 all have floating voltage.
  • the termination area comprises two floating trenched gates (FTG 1 and FTG 2 ) and two channel stop trenched gates (CSTG 1 and CSTG 2 ) in this embodiment.
  • the termination area in trench MOSFET 300 ′ comprises four floating trenched gates (FTG 1 , FTG 2 , FTG 3 and FTG 4 ) and one channel stop trenched gate (CSTG 1 ), and all the trenched gates in termination area including the sawing trenched gate SWTG 1 are implemented by using single shielded electrode structure.
  • the termination area in trench MOSFET 310 ′ comprises four floating trenched gates (FTG 1 , FTG 2 , FTG 3 and FTG 4 ) and one channel stop trenched gate (CSTG 1 ), and all the trenched gates in termination area including the sawing trenched gate SWTG 1 are implemented by using double electrodes structure which comprises a gate electrode in upper portion and a shielded electrode in lower portion.
  • the termination area in trench MOSFET 320 ′ comprises four floating trenched gates (FTG 1 , FTG 2 , FTG 3 and FTG 4 ) and one channel stop trenched gate (CSTG 1 ).
  • Some of the floating trenched gates (two in this embodiment) near active area are implemented by using single shielded electrode structure, and the rest trenched gates including the sawing trenched gate SWTG 1 are implemented by using double electrodes structure which comprises a gate electrode in upper portion and a shielded electrode in lower portion.
  • the termination area in trench MOSFET 330 ′ comprises four floating trenched gates (FTG 1 , FTG 2 , FTG 3 and FTG 4 ) and one channel stop trenched gate (CSTG 1 ).
  • Some of the floating trenched gates (two in this embodiment) near active area are implemented by using double electrodes structure which comprises a gate electrode in upper portion and a shielded electrode in lower portion, and the rest trenched gates including the sawing trenched gate SWTG 1 are implemented by using single shielded electrode structure.
  • trench MOSFET 400 ′ is a P type trench MOSFET formed in P type epitaxial layer.
  • trench MOSFET 410 ′ is a P type trench MOSFET formed in P type epitaxial layer.
  • trench MOSFET 420 ′ is a P type trench MOSFET formed in P type epitaxial layer.
  • trench MOSFET 430 ′ is a P type trench MOSFET formed in P type epitaxial layer.
  • the n+ source region 503 in the trench MOSFET 500 ′ has a doping concentration of Gaussian-distribution from edge of a trenched source-body contact 504 to an adjacent channel region near the gate electrode 505 near the shielded trenched gate 506 , and has junction depth near edge of the trenched source-body contact 504 greater than near the adjacent channel region.
  • the p+ source region 513 in the trench MOSFET 510 ′ has a doping concentration of Gaussian-distribution from edge of a trenched source-body contact 514 to an adjacent channel region near the gate electrode 515 near the shielded trenched gate 516 , and has junction depth near edge of the trenched source-body contact 514 greater than near the adjacent channel region.
  • FIG. 6A for a preferred trench MOSFET layout structure composed of dual dies layout, wherein dies are connected together with multiple sawing trenched gates (SWTGs, as illustrated), what should be noticed is that, die to die space (Sdd, as illustrated in FIG. 6C ) is same as the scribe line width (W SL , a illustrated in FIG. 6C ), which makes it happen to achieve a feasible trench MOSFET with the invented structure.
  • SWTGs sawing trenched gates
  • FIG. 6B Please refer to FIG. 6B for a preferred trench MOSFET layout structure composed of three dies layout, wherein dies are connected together with multiple sawing trenched gates (SWTGs, as illustrated), what should be noticed is that, die to die space (Sdd, as illustrated in FIG. 6C ) is same as the scribe line width (W SL , a illustrated in FIG. 6C ), which makes it happen to achieve a feasible trench MOSFET with the invented structure.
  • SWTGs sawing trenched gates
  • FIG. 6C for a preferred trench MOSFET layout structure composed of four dies layout, wherein dies are connected to each other with multiple sawing trenched gates (SWTGs, as illustrated), what should be noticed is that, die to die space (Sdd, as illustrated) is same as the scribe line width (W SL , a illustrated), which makes it happen to achieve a feasible trench MOSFET with the invented structure.
  • SWTGs sawing trenched gates

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951771B (zh) * 2019-12-10 2024-08-13 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
CN111129152B (zh) * 2019-12-17 2023-09-26 杭州芯迈半导体技术有限公司 沟槽mosfet结构及其制造方法
US20210202470A1 (en) * 2019-12-31 2021-07-01 Nami MOS CO., LTD. Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed
CN111312824B (zh) * 2020-01-09 2022-03-04 安建科技(深圳)有限公司 沟槽型功率半导体器件及其制备方法
EP3863065A1 (en) * 2020-02-04 2021-08-11 Infineon Technologies Austria AG Semiconductor die and method of manufacturing the same
US11329155B2 (en) * 2020-02-26 2022-05-10 Nami MOS CO., LTD. Trench MOSFETs integrated with clamped diodes having trench field plate termination to avoid breakdown voltage degradation
US20210296488A1 (en) * 2020-03-19 2021-09-23 Nami MOS CO., LTD. Shielded gate trench mosfet having super junction region for dc/ac performance improvement
US11380787B2 (en) * 2020-05-08 2022-07-05 Nami Mos Co, Ltd Shielded gate trench MOSFET integrated with super barrier rectifier having short channel
JP7387566B2 (ja) * 2020-09-18 2023-11-28 株式会社東芝 半導体装置
CN114280863B (zh) * 2021-12-17 2024-04-12 滁州惠科光电科技有限公司 阵列基板及显示面板
CN114597264B (zh) * 2022-05-10 2022-07-26 南京微盟电子有限公司 一种功率mosfet器件及其制作方法
CN115188822A (zh) * 2022-09-13 2022-10-14 华羿微电子股份有限公司 沟槽型mosfet终端
CN116646384B (zh) * 2023-07-27 2024-03-26 深圳芯能半导体技术有限公司 一种具沟槽场截止结构的igbt芯片及其制作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8643092B2 (en) 2009-11-20 2014-02-04 Force Mos Technology Co., Ltd. Shielded trench MOSFET with multiple trenched floating gates as termination
US20140291753A1 (en) * 2013-03-27 2014-10-02 Force Mos Technology Co., Ltd. Trench mosfet structure having self-aligned features for mask saving and on-resistance reduction

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006127914A2 (en) * 2005-05-26 2006-11-30 Fairchild Semiconductor Corporation Trench-gate field effect transistors and methods of forming the same
DE102006024504B4 (de) * 2006-05-23 2010-09-02 Infineon Technologies Austria Ag Leistungshalbleiterbauelement mit vertikaler Gatezone und Verfahren zur Herstellung desselben
US20110254071A1 (en) * 2009-11-20 2011-10-20 Force Mos Technology Co. Ltd. Shielded trench mosfet with multiple trenched floating gates as termination
US8907415B2 (en) * 2011-05-16 2014-12-09 Force Mos Technology Co., Ltd. High switching trench MOSFET
US8487372B1 (en) * 2012-06-29 2013-07-16 Force Mos Technology Co., Ltd. Trench MOSFET layout with trenched floating gates and trenched channel stop gates in termination
US8704297B1 (en) * 2012-10-12 2014-04-22 Force Mos Technology Co., Ltd. Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge
CN103730499A (zh) * 2012-10-12 2014-04-16 力士科技股份有限公司 沟槽式金属氧化物半导体场效应管
JP6471508B2 (ja) * 2015-01-19 2019-02-20 富士電機株式会社 半導体装置
US9953969B2 (en) * 2016-03-25 2018-04-24 Force Mos Technology Co., Ltd. Semiconductor power device having shielded gate structure and ESD clamp diode manufactured with less mask process
CN105702739B (zh) * 2016-05-04 2019-04-23 深圳尚阳通科技有限公司 屏蔽栅沟槽mosfet器件及其制造方法
CN107681006A (zh) * 2017-11-01 2018-02-09 苏州凤凰芯电子科技有限公司 一种具有阶梯形氧化层的屏蔽栅mos结构

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8643092B2 (en) 2009-11-20 2014-02-04 Force Mos Technology Co., Ltd. Shielded trench MOSFET with multiple trenched floating gates as termination
US20140291753A1 (en) * 2013-03-27 2014-10-02 Force Mos Technology Co., Ltd. Trench mosfet structure having self-aligned features for mask saving and on-resistance reduction

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