US10885989B1 - Data storage apparatus and internal voltage trimming circuit and method for trimming an internal voltage - Google Patents

Data storage apparatus and internal voltage trimming circuit and method for trimming an internal voltage Download PDF

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US10885989B1
US10885989B1 US16/806,644 US202016806644A US10885989B1 US 10885989 B1 US10885989 B1 US 10885989B1 US 202016806644 A US202016806644 A US 202016806644A US 10885989 B1 US10885989 B1 US 10885989B1
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signal
integration
trimming
output
circuit
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Young Jin Moon
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MIMIRIP LLC
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SK Hynix Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
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    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45048—Calibrating and standardising a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45156—At least one capacitor being added at the input of a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45174—Indexing scheme relating to differential amplifiers the application of the differential amplifier being in an integrator circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45332—Indexing scheme relating to differential amplifiers the AAC comprising one or more capacitors as feedback circuit elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45514—Indexing scheme relating to differential amplifiers the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45616—Indexing scheme relating to differential amplifiers the IC comprising more than one switch, which are not cross coupled

Definitions

  • Various embodiments may generally relate to a semiconductor integrated device, and more particularly, to a data storage apparatus and an interval voltage trimming circuit and method for trimming an internal voltage.
  • Semiconductor devices operate by internal voltages which are generated using an external voltage supplied from the outside and need to generate accurate internal voltages for stable operation.
  • the internal voltages may be generated to desired levels, for example, through trimming.
  • External test equipment outside the semiconductor device may be used for voltage trimming.
  • an embedded test device called a built-in self-test (BIST) device has been introduced.
  • BIST is for trimming a voltage to a target level through an internal circuit of a semiconductor device and reduces the test time and cost.
  • a data storage apparatus may include storage and a controller configured to control the storage in response to a request from a host.
  • the controller includes an internal voltage trimming circuit which is includes include: an integration circuit configured to generate an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage; a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage; a transition detection circuit configured to output a detection signal in response to level transition of the comparison signal; a counter configured to receive an initial trimming code and generate a preliminary trimming code by increasing or reducing the initial trimming code; and an average circuit configured to generate a final trimming code by averaging the preliminary trimming code for a determined time interval and provide the final trimming code to the storage.
  • DUT device under test
  • a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage
  • a transition detection circuit configured to output a detection signal in response to level transition of the comparison signal
  • a counter configured to receive an initial trimming code and generate
  • an internal voltage trimming circuit configured to provide a trimming code for generating an internal voltage of a semiconductor device.
  • the internal voltage trimming circuit may include: an integration circuit configured to generate an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage; a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage; a transition detection circuit configured to output a detection signal in response to level transition of the comparison signal; a counter configured to receive an initial trimming code and generate a preliminary trimming code by increasing or reducing the initial trimming code in response to the detection signal; and an average circuit configured to generate a final trimming code by averaging the preliminary trimming code for a determined time interval and provide the final trimming code to the semiconductor device.
  • a trimming method performed by an internal voltage trimming circuit for generating an internal voltage of a semiconductor device may include: generating an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage; generating a comparison signal by comparing the integration signal and the reference voltage; outputting a detection signal in response to level transition of the comparison signal; generating a preliminary trimming code by increasing or reducing an initial trimming code in response to the detection signal; and generating a final trimming code by averaging the preliminary trimming code for a determined time interval and providing the final trimming code to the semiconductor device.
  • DUT device under test
  • FIG. 1 is a diagram illustrating a configuration of a data storage apparatus according to an embodiment of the present disclosure
  • FIG. 2 is a diagram illustrating a configuration of a nonvolatile memory device included in a data storage apparatus according to an embodiment of the present disclosure
  • FIG. 3 is a diagram illustrating a configuration of an internal voltage trimming circuit according to an embodiment of the present disclosure
  • FIG. 4 is a diagram illustrating a configuration of an integration circuit according to an embodiment of the present disclosure
  • FIG. 5 is a diagram illustrating a configuration of an average circuit according to an embodiment of the present disclosure.
  • FIGS. 6 to 8 are timing diagrams for describing trimming code generating methods according to embodiments of the present disclosure.
  • FIG. 9 is a diagram for describing a trimming code generating method according to an embodiment of the present disclosure.
  • FIGS. 10, 11, and 12 are timing diagrams for describing to trimming code generating methods according to embodiments of the present disclosure
  • FIG. 13 is a diagram illustrating a configuration of an integration circuit according to an embodiment of the present disclosure.
  • FIG. 14 is a diagram illustrating a configuration of an integration circuit according to an embodiment of the present disclosure.
  • FIG. 1 is a diagram illustrating a configuration of a data storage apparatus according to an embodiment.
  • a data storage apparatus 10 may include a controller 110 and storage 120 and may operate according to control of a host (not shown).
  • the controller 110 may control the storage 120 in response to a request of the host. For example, the controller 110 may control data to be programmed in the storage 120 in response to a write request from the host. The controller 110 may provide data stored in the storage 120 to the host in response to a read request from the host.
  • the storage 120 may store data or output stored data according to control of the controller 110 .
  • the storage 120 may be configured of a volatile or nonvolatile memory device.
  • the storage 120 may be implemented using a memory device selected among various nonvolatile memory devices such as an electrically erasable and programmable read only memory (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change random access memory (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), a spin torque transfer magnetic RAM (STT-MRAM), and the like.
  • the storage 120 may include a plurality of nonvolatile memory devices (NVMs) 121 , 122 , 123 , . . . .
  • the nonvolatile memory device may include a plurality of dies, a plurality of chips, or a plurality of packages.
  • the storage 120 may operate as a single-level cell (SLC) in which one-bit data is to be stored in one memory cell or a multi-level cell in which multi-bit data is to be stored in one memory cell.
  • SLC single-level cell
  • the storage 120 may generate an internal voltage by receiving an internal voltage trimming code CODE_TRIM from the controller 110 to perform a program, erase, or read operation according to control of the controller 110 .
  • the controller 110 may include an internal voltage trimming circuit 20 .
  • the internal voltage trimming circuit 20 may be coupled to an off-chip test device 30 , which is an external tester in some embodiments.
  • the internal voltage trimming circuit 20 may perform a test operation such as an operation of generating the internal voltage trimming code CODE_TRIM in response to a test command CMD of the off-chip test device 30 and provide a test result RSLT to the off-chip test device 30 .
  • the internal voltage trimming circuit 20 may be implemented in a BIST device type and embedded in the inside of the controller 110 . Accordingly, various tests including the internal voltage trimming operation may be performed on-chip.
  • the internal voltage trimming circuit 20 may provide the off-chip test device 30 with the test result RSLT after the completion of the trimming operation.
  • the internal voltage trimming code CODE_TRIM determined through the internal voltage trimming circuit 20 may be stored in control logic of the storage 120 and may be used for the internal operations of the storage 120 such as the program, erase, and read operations.
  • FIG. 2 is a diagram illustrating a configuration of a nonvolatile memory device 300 included in a data storage apparatus according to an embodiment.
  • the nonvolatile memory device 300 may include a memory cell array 310 , a row decoder 320 , a data read/write block 330 , a column decoder 340 , a voltage generator 350 , and control logic 360 .
  • the memory cell array 310 may include memory cells MC which are arranged in regions where word lines WL 1 to WLm and bit lines BL 1 to BLn cross each other.
  • the memory cell array 310 may include a three-dimensional (3D) memory array.
  • the 3D memory array may refer to an array structure including a NAND string having a directivity perpendicular to one surface of a semiconductor substrate, that at least one memory cell is vertically located over another memory cell.
  • the 3D memory array is not limited thereto and any memory array highly integrated in a vertical directivity as well as a horizontal directivity may be selectively adapted to the 3D memory array.
  • the row decoder 320 may be coupled with the memory cell array 310 through the word lines WL 1 to WLm.
  • the row decoder 320 may operate according to control of the control logic 360 .
  • the row decoder 320 may decode addresses provided from an external device (not shown).
  • the row decoder 320 may select and drive the word lines WL 1 to WLm, based on the decoding results. For example, the row decoder 320 may provide word line voltages provided from the voltage generator 350 , to the word lines WL 1 to WLm.
  • the data read/write block 330 may be coupled with the memory cell array 310 through the bit lines BL 1 to BLn.
  • the data read/write block 330 may include read/write circuits RW 1 to RWn corresponding to the bit lines BL 1 to BLn.
  • the data read/write block 330 may operate according to control of the control logic 360 .
  • the data read/write block 330 may operate as a write driver or a sense amplifier according to an operation mode.
  • the data read/write block 330 may operate as a write driver which stores data provided from the external device, in the memory cell array 310 in a write operation.
  • the data read/write block 330 may operate as a sense amplifier which reads out data from the memory cell array 310 in a read operation.
  • the column decoder 340 may operate according to control of the control logic 360 .
  • the column decoder 340 may decode addresses provided from the external device.
  • the column decoder 340 may couple data input/output lines (or data input/output buffers) with the read/write circuits RW 1 to RWn of the data read/write block 330 which respectively correspond to the bit lines BL 1 to BLn, based on decoding results.
  • the voltage generator 350 may generate voltages used for operations of the nonvolatile memory devices 300 .
  • the voltages generated by the voltage generator 350 may be applied to the memory cells MC of the memory cell array 310 .
  • a program voltage generated in a program operation may be applied to a word line of memory cells on which the program operation is to be performed.
  • an erase voltage generated in an erase operation may be applied to a well region of memory cells on which the erase operation is to be performed.
  • a read voltage generated in a read operation may be applied to a word line of memory cells on which the read operation is to be performed.
  • the control logic 360 may control an overall operation of the nonvolatile memory device 300 , based on control signals provided from the external device. For example, the control logic 360 may control the read, write, and erase operations of the nonvolatile memory device 300 .
  • the control logic 360 may be implemented as hardware, software, or a combination of hardware and software.
  • the control logic 360 may be a control logic circuit operating in accordance with an algorithm and/or a processor executing control logic code.
  • the trimming code CODE_TRIM provided from the controller 110 may be stored in read-only memory (ROM) inside the control logic 360 and the voltage generator 350 may generate an internal voltage based on the trimming code CODE_TRIM.
  • ROM read-only memory
  • the internal voltage trimming circuit 20 may integrate a difference between an output voltage of a device under test (DUT) and a reference voltage, compare an integrated result with the reference voltage, and increase or reduce the trimming code according to a comparison result.
  • the internal voltage trimming circuit 20 may generate a final trimming code by averaging the trimming code output for a determined time interval.
  • the interval voltage trimming circuit 20 may use an offset cancelled integrator to exclude influence due to external noise and fluctuations of process variables.
  • the internal voltage trimming circuit 20 may allow the response characteristic of the integration circuit to converge near a reference voltage level by adding a zero or pole to the integration circuit so that the fluctuation rate of the trimming code may be minimized.
  • FIG. 3 is a diagram illustrating a configuration of an internal voltage trimming circuit 20 according to an embodiment.
  • the internal voltage trimming circuit 20 may include a DUT 210 , an integration circuit 220 , a comparison circuit 230 , a transition detection circuit 240 , a counter 250 , and an average circuit 260 .
  • the DUT 210 may be configured to output a test voltage DOUT in response to the trimming code CODE_TRIM.
  • the integration circuit 220 may be configured to integrate a difference between the test voltage DOUT output from the DUT 210 and a reference voltage VREF.
  • the integration circuit 220 may be configured to receive differential input signals generated from the test voltage DOUT and generate differential integration signals INTOUTP and INTOUTN, but this is not limited thereto.
  • the comparison circuit 230 may be configured to receive the differential integration signals INTOUTP and INTOUTN provided from the integration circuit 220 and generate a comparison signal COMP by comparing the differential integration signals INTOUTP and INTOUTN and the reference voltage VREF.
  • the transition detection circuit 240 may be configured to receive the comparison signal COMP and output a detection signal DET when a level of the comparison signal COMP is transited.
  • the counter 250 may be configured to receive an initial trimming code CODE_DFT and output a count signal CNT, which is a preliminary trimming code in other points of view, by increasing or reducing the initial trimming code CODE_DFT in response to the detection signal DET.
  • the average circuit 260 may be configured to generate a final trimming code CODE_TRIM by averaging the count signal CNT output from the counter 250 for a determined time interval.
  • the counter 250 might not increase or reduce the trimming code CODE_TRIM in response to every clock signal but may increase or reduce the trimming code CODE_TRIM when the output signal COMP of the comparison circuit 230 is transited, so that the frequent fluctuation of the trimming code CODE_TRIM may be mitigated or prevented.
  • the trimming code CODE_TRIM is maintained to a specific level for a determined time interval, the trimming code CODE_TRIM with no error may be generated even when the trimming code CODE_TRIM is collected and averaged for a short time.
  • the integration circuit 220 may use an offset cancelled integrator to exclude influence due to external noise and fluctuations of process variables when comparing the output voltage DOUT of the DUT 210 and the reference voltage VREF and may be configured, for example, as in FIG. 4 .
  • FIG. 4 is a diagram illustrating a configuration of an integration circuit 220 according to an embodiment.
  • the integration circuit 220 may include a sampling unit 221 and an amplifying integration unit 223 .
  • the sampling unit 221 may be configured to: receive a positive (+) input signal DOUTP, a negative ( ⁇ ) input signal DOUTN, and the reference voltage VREF; sample the positive (+) input signal DOUTP and the negative ( ⁇ ) input signal in response to a first control signal ⁇ 1 and a second control signal ⁇ 2 ; and output sampling signals to the amplifying integration unit 223 .
  • the amplifying integration circuit 223 may be configured to integrate the sampling signals output from the sampling unit 221 and output integrating results to a positive (+) output terminal INTOUTN and a negative ( ⁇ ) output terminal INTOUTP.
  • the sampling unit 221 may include a first sampling switch S 11 coupled to the positive (+) input terminal DOUTP and driven in response to the first control signal ⁇ 1 , a first output switch S 12 coupled between the first sampling switch S 11 and a reference voltage VREF input terminal and driven in response to the second control signal ⁇ 2 , a first sampling capacitor CS 1 of which one terminal is coupled to the first sampling switch S 11 , a second sampling switch S 13 coupled between the other terminal of the first sampling capacitor CS 1 and the reference voltage VREF input terminal and driven in response to the first control signal ⁇ 1 , and a second output switch S 14 coupled to the other terminal of the first sampling capacitor CS 1 and driven in response to the second control signal ⁇ 2 .
  • the first sampling switch S 11 , the first output switch S 12 , the first sampling capacitor CS 1 , the second sampling switch S 13 , and the second output switch S 14 may constitute a first sampling unit 2211 .
  • the sampling unit 221 may further include a third sampling switch S 21 coupled to the negative ( ⁇ ) input terminal DOUTN and driven in response to the first control signal ⁇ 1 , a third output switch S 22 coupled between the third sampling switch S 21 and the reference voltage VREF input terminal and driven in response to the second control signal ⁇ 2 , a second sampling capacitor CS 2 of which one terminal is coupled to the third sampling switch S 21 , a fourth sampling switch S 23 coupled between the other terminal of the second sampling capacitor CS 2 and the reference voltage VREF input terminal and driven in response to the first control signal ⁇ 1 , and a fourth output switch S 24 coupled to the other terminal of the second sampling capacitor CS 2 and driven in response to the second control signal ⁇ 2 .
  • the third sampling switch S 21 , the third output switch S 22 , the second sampling capacitor CS 2 , the fourth sampling switch S 23 , and the fourth output switch S 24 may constitute a second sampling unit 2213 .
  • the first control signal ⁇ 1 and the second control signal ⁇ 2 may be signals having clock phases such that high level intervals are alternately repeated and non-overlapping.
  • the differences between the input signals DOUTP and DOUTN and the reference voltage VREF may be sampled through the first and second sampling capacitors CS 1 and CS 2 during the high level interval of the first control signal ⁇ 1 .
  • the voltages sampled through the first and second sampling capacitors CS 1 and CS 2 may be transferred and integrated to and in the amplifying integration unit 223 during the high level interval of the second control signal ⁇ 2 .
  • the amplifying integration unit 223 may include a first offset cancellation unit 2231 , a second offset cancellation unit 2233 , a first integration unit 2235 , a second integration unit 2237 , and an amplification unit 2239 .
  • the first integration unit 2235 may include a fifth output switch S 15 coupled to an output terminal of the first sampling unit 2211 and driven in response to the second control signal ⁇ 2 , a first integration capacitor CINT 1 coupled between the fifth output switch S 15 and the negative ( ⁇ ) output terminal INTOUTP of the amplification unit 2239 , and a fifth sampling switch S 16 coupled between a positive (+) input terminal of the amplification unit 2239 and the first integration capacitor CINT 1 and driven in response to the first control signal ⁇ 1 .
  • the first offset cancellation unit 2231 may include a first offset cancellation capacitor COC 1 of which one terminal is coupled to the output terminal of the first sampling unit 2211 and the other terminal is coupled to the positive (+) input terminal of the amplification unit 2239 .
  • the second integration unit 2237 may include a sixth output switch S 25 coupled to an output terminal of the second sampling unit 2213 and driven in response to the second control signal ⁇ 2 , a second integration capacitor CINT 2 coupled between the sixth output switch S 25 and the positive (+) output terminal INTOUTN of the amplification unit 2239 , and a sixth sampling switch S 26 coupled between a negative ( ⁇ ) input terminal of the amplification unit 2239 and the second integration capacitor CINT 2 and driven in response to the first control signal ⁇ 1 .
  • the second offset cancellation unit 2233 may include a second offset cancellation capacitor COC 2 of which one terminal is coupled to the output terminal of the second sampling unit 2213 and the other terminal is coupled to the negative ( ⁇ ) input terminal of the amplification unit 2239 .
  • the amplification unit 2239 may have a differential output including an inverting output signal INTOUTP and a noninverting output signal INTOUTN. Noise may be generated in proportion to the differential output and thus the effect due to the external noise may be mitigated or eliminated.
  • the malfunction due to the fluctuations of the process variables may be compensated through the first and second offset cancellation capacitors COC 1 and COC 2 arranged in the input terminals of the amplification unit 2239 .
  • FIG. 5 is a diagram illustrating a configuration of an average circuit 250 according to an embodiment.
  • the average circuit 250 may include a subtractor 251 , a first adder 253 , a first register 255 , a second adder 257 , and a second register 259 .
  • the subtractor 251 may detect a difference between the initial trimming code CODE_DFT and the count signal CNT.
  • the first adder 253 may be configured to add an output signal of the subtractor 251 and an output signal of the first register 255 for a preset time.
  • the first register 255 may store an output signal of the first adder 253 .
  • the second adder 257 may be configured to add the output signal of the first register 255 and the initial trimming code CODE_DFT.
  • the second register 259 may store the final trimming code CODE_TRIM which is an output signal of the second adder 257 and transmit the final trimming code CODE_TRIM to the DUT 210 and the storage 120 .
  • FIGS. 6 to 8 are timing diagrams for describing trimming code generating methods according to embodiments.
  • the test voltage DOUT may be output from the DUT 210 according to the initial trimming code CODE_DFT and the integration circuit 220 may receive the test voltage DOUT and the reference voltage VREF and output the integration signal INTOUT by integrating the difference between the test voltage DOUT and the reference voltage VREF.
  • the comparison circuit 230 may compare the output signal of the integration circuit 220 and the reference voltage VREF.
  • the comparison circuit 230 may output the comparison signal COMP having a logic high level when the test voltage DOUT is lower than the reference voltage VREF and the output of the integration circuit 220 falls.
  • the comparison circuit 230 may output the comparison signal COMP having a logic low level when the test voltage DOUT is higher than the reference voltage VREF and the output of the integration circuit 220 rises.
  • the counter 250 may reduce the trimming code CODE_TRIM by 1 code in response to the low-level comparison signal COMP and increase the trimming code CODE_TRIM by 1 code in response to the high-level comparison signal COMP.
  • the average circuit 260 may generate the final trimming code CODE_TRIM by averaging the preliminary trimming code CNT output from the counter 250 for a determined time interval.
  • the trimming code CODE_TRIM When the trimming code CODE_TRIM is changed in response to every clock signal, the code fluctuates frequently as illustrated in FIGS. 6 and 7 . Therefore, an error may occur when the code is averaged for a short interval. When the code is averaged for a long interval to solve the problem, a long time may be necessary to generate the trimming code and a circuit size may be increased.
  • the time and cost required to generate the trimming code may be increased.
  • the time and cost required to generate the trimming code may be increased. Further, when a result that needs to be rounded is obtained, a code error may be caused.
  • FIG. 9 is a diagram for describing a trimming code generating method according to an embodiment.
  • the present technology might not increase and reduce the trimming code CODE_TRIM every clock signal and may change the trimming code CODE_TRIM in response to transition of the output signal of the comparison circuit.
  • the high-level comparison signal COMP may be output from the comparison circuit 230 .
  • the output signal of the comparison circuit 230 may be transited to a low level.
  • the transition detection circuit 240 may detect transition of the output signal of the comparison circuit 230 and the counter 250 may increase or reduce the trimming code CODE_TRIM when the transition of the output signal of the comparison circuit 230 is detected.
  • the average circuit 260 may generate the final trimming code CODE_TRIM by averaging the trimming code CODE_TRIM for a determined time interval.
  • FIGS. 10 to 12 are timing diagrams for describing trimming code generating methods according to embodiments.
  • the trimming code CODE_TRIM may be averaged and an average 0 (zero) code may be calculated.
  • the trimming code CODE_TRIM is averaged in the respective intervals B and C and ⁇ 0.2 code is calculated. Because ⁇ 0.5 code or less might not be rounded to and may be neglected when the code is averaged and thus the error code might not be caused.
  • the reliable trimming code may be obtained and a circuit size due to calculation simplification may be reduced or minimized.
  • FIG. 13 is a diagram illustrating a configuration of an integration circuit 220 - 1 according to an embodiment.
  • the integration circuit 220 - 1 may further include a first pole addition unit 225 coupled between the first sampling unit 2211 and the negative ( ⁇ ) output terminal INTOUTP of the amplification unit 2239 and a second pole addition unit 227 coupled between the second sampling unit 2213 and the positive (+) output terminal INTOUTN of the amplification unit 2239 .
  • the first pole addition unit 225 may include a first pole switch S 17 coupled to the first sampling unit 2211 and driven in response to the first control signal ⁇ 1 , a second pole switch S 18 coupled between the first pole switch S 17 and a ground terminal and driven in response to the second control signal ⁇ 2 , a first pole capacitor CP 1 of which one terminal is coupled to the second pole switch S 18 , a third pole switch S 19 coupled between the other terminal of the first pole capacitor CP 1 and the ground terminal and driven in response to the second control signal ⁇ 2 , and a fourth pole switch S 20 coupled between the other terminal of the first pole capacitor CP 1 and the negative ( ⁇ ) output terminal INTOUTP of the amplification unit 2239 .
  • the second pole addition unit 227 may include a fifth pole switch S 27 coupled to the second sampling unit 2213 and driven in response to the first control signal ⁇ 1 , a sixth pole switch S 28 coupled between the fifth pole switch S 27 and the ground terminal and driven in response to the second control signal ⁇ 2 , a second pole capacitor CP 2 of which one terminal is coupled to the sixth pole switch S 28 , a seventh pole switch S 29 coupled between the other terminal of the second pole capacitor CP 2 and the ground terminal and driven in response to the second control signal ⁇ 2 , and a eighth pole switch S 30 coupled between the other terminal of the second pole capacitor CP 2 and the positive (+) output terminal INTOUTN of the amplification unit 2239 .
  • the integration circuit 220 - 1 illustrated in FIG. 13 may add the pole to the output signals (e.g., INTOUTP and INTOUTN) and feedback the pole-added output signals to the input terminals (e.g., DOUTP and DOUTN. Accordingly, the levels of the output signals of the integration circuit 220 - 1 may be formed near the level of the reference voltage VREF which is a common mode voltage and thus the fluctuation of the trimming code may be minimized.
  • the reference voltage VREF which is a common mode voltage
  • Capacitances of the pole capacitors CP 1 and CP 2 may be selected as values which satisfy the desired poles.
  • FIG. 14 is a diagram illustrating a configuration of an integration circuit 220 - 2 according to an embodiment.
  • the integration circuit 220 - 2 may further include a first zero addition unit 228 and a second zero addition unit 229 in addition to the components of the integration circuit 220 illustrated in FIG. 4 .
  • the first zero addition unit 228 may include a first zero capacitor CZ 1 coupled between the input terminal DOUTP of the first sampling unit 2211 and the first integration unit 2235 .
  • the second zero addition unit 229 may include a second zero capacitor CZ 2 coupled between the input terminal DOUTN of the second sampling unit 2213 and the second integration unit 2237 .
  • the present technology may allow the response characteristic of the integration circuit 220 - 2 to converge near the level of the reference level VREF, in the interval for which the phase of the first control signal ⁇ 1 is a high level, through the first and second zero addition units 228 and 229 and thus may minimize the fluctuation rate of the trimming code CODE_TRIM.

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