US10748485B2 - Pixel circuit, display panel, display device and driving method - Google Patents

Pixel circuit, display panel, display device and driving method Download PDF

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US10748485B2
US10748485B2 US15/557,691 US201715557691A US10748485B2 US 10748485 B2 US10748485 B2 US 10748485B2 US 201715557691 A US201715557691 A US 201715557691A US 10748485 B2 US10748485 B2 US 10748485B2
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transistor
node
voltage
signal
light emission
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US20180308427A1 (en
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Kai Zhang
Yi Zhang
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Assigned to BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment BOE TECHNOLOGY GROUP CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZHANG, KAI
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H10K50/805—Electrodes
    • H10K50/81—Anodes
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a display panel, a display device, and a driving method.
  • organic light-emitting diode (OLED) display panels have a broad development prospect due to characteristics such as self-illumination, high contrast, low power consumption, a wide viewing angle, fast response, capability of being used in a flexible panel, a wide usage temperature range, simplicity in fabrication, and so on. Due to the above-described characteristics, the organic light-emitting diode (OLED) display panels may be applied on mobile phones, monitors, laptops, digital cameras, instruments and other devices having a display function.
  • Embodiments of the disclosure provide a pixel circuit, comprising: a storage capacitor, including a first terminal and a second terminal, wherein the first terminal is connected with a first node, and the second terminal is connected with a reference voltage line to receive a reference voltage; an organic light-emitting diode, including an anode and a cathode, wherein the anode is connected with a second node, and the cathode is connected with a second power line to receive a second voltage; a driving transistor, including a gate electrode connected with the first node, wherein the driving transistor is configured to control light emission of the organic light-emitting diode according to a voltage of the first node; a first reset circuit, configured to supply an initial voltage to the first node in response to a reset signal; a scanning circuit, configured to supply a data signal to a third node in response to a scanning signal; a compensating circuit, configured to supply a compensating voltage to the first node in response to the scanning signal, where
  • the light emission control circuit includes: a first light emission control circuit, configured to supply a first voltage of a first power line to a fourth node in response to the light emission control signal; and a second light emission control circuit, configured to conduct the third node and the second node in response to the light emission control signal.
  • At least one of the first reset circuit, the scanning circuit, the compensating circuit and the light emission control circuit includes a transistor.
  • the first reset circuit includes a first transistor, a first electrode of the first transistor is connected with an initial signal line to receive the initial voltage, a gate electrode of the first transistor is connected with a reset signal line to receive the reset signal, and a second electrode of the first transistor is connected with the first node;
  • the compensating circuit includes a second transistor, a first electrode of the second transistor is connected with the first node, a gate electrode of the second transistor is connected with a scanning signal line to receive the scanning signal, and a second electrode of the second transistor is connected with the fourth node;
  • the scanning circuit includes a fourth transistor, a first electrode of the fourth transistor is connected with a data signal line to receive the data signal, a gate electrode of the fourth transistor is connected with the scanning signal line to receive the scanning signal, and a second electrode of the fourth transistor is connected with the third node; and a first electrode of the driving transistor is connected with the fourth node, a gate electrode of the driving transistor is connected with the first node, and
  • the first light emission control circuit includes a fifth transistor, a first electrode of the fifth transistor is connected with the first power line to receive the first voltage, a gate electrode of the fifth transistor is connected with a light emission control signal line to receive the light emission control signal, and a second electrode of the fifth transistor is connected with the fourth node; and the second light emission control circuit is a sixth transistor, a first electrode of the sixth transistor is connected with the third node, a gate electrode of the sixth transistor is connected with the light emission control signal line to receive the light emission control signal, and a second electrode of the sixth transistor is connected with the second node.
  • the pixel circuit provided in embodiments of the disclosure further comprises a second reset circuit, configured to supply the initial voltage to the second node in response to the reset signal.
  • At least one of the first reset circuit, the scanning circuit, the second reset circuit and the compensating circuit includes a transistor; and the light emission control circuit includes a fifth transistor and a sixth transistor.
  • the first reset circuit includes a first transistor, a first electrode of the first transistor is connected with an initial signal line to receive the initial voltage, a gate electrode of the first transistor is connected with a reset signal line to receive the reset signal, and a second electrode of the first transistor is connected with the first node;
  • the compensating circuit includes a second transistor, a first electrode of the second transistor is connected with the first node, a gate electrode of the second transistor is connected with a scanning signal line to receive the scanning signal, and a second electrode of the second transistor is connected with the fourth node;
  • the scanning circuit includes a fourth transistor, a first electrode of the fourth transistor is connected with a data signal line to receive the data signal, a gate electrode of the fourth transistor is connected with the scanning signal line to receive the scanning signal, and a second electrode of the fourth transistor is connected with the third node;
  • the first electrode of the driving transistor is connected with the fourth node, the gate electrode of the driving transistor is connected with the first node, and the second electrode of
  • the first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all P-type transistors.
  • the first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all thin film transistors.
  • Embodiments of the disclosure further provide a display panel, comprising the pixel circuit described above.
  • the display panel further comprises: a first power line, for supplying a first voltage; a second power line, for supplying a second voltage; a reference voltage line, a data signal line, a reset signal line, and a scanning signal line, wherein the data signal line and the reset signal line are arranged to extend across each other, the data signal line and the scanning signal line are arranged to extend across each other, and the reference voltage line is parallel to at least one of the data signal line, the reset signal line and the scanning signal line; a scan driving circuit, configured to supply the scanning signal to a scanning signal line; and a data driving circuit, configured to supply the data signal to a data signal line.
  • Embodiments of the disclosure further provide a display device, comprising the display panel described above.
  • Embodiments of the disclosure further provide a driving method of the pixel circuit described above, comprising a reset stage, a data write and threshold compensation stage and a light emission stage, wherein: in the reset stage, a light emission control signal is set to a turning-off voltage, a reset signal is set to a turning-on voltage, a scanning signal is set to the turning-on voltage, and a data signal is set to an invalid data signal; in the data write and threshold compensation stage, the light emission control signal is set to the turning-off voltage, the reset signal is set to the turning-off voltage, the scanning signal is set to the turning-on voltage, and the data signal is set to a valid data signal; and in the light emission stage, the light emission control signal is set to the turning-on voltage, the reset signal is set to the turning-off voltage, the scanning signal is set to the turning-off voltage, and the data signal is set to the invalid data signal.
  • the driving method provided in embodiments of the disclosure further comprises a pre-reset stage prior to the reset stage; wherein in the pre-reset stage, the light emission control signal is set to the turning-off voltage, the reset signal is set to the turning-off voltage, the scanning signal is set to the turning-off voltage, and the data signal is set to the invalid data signal.
  • the driving method provided in embodiments of the disclosure further comprises a signal write preparation stage between the reset stage and the data write and threshold compensation stage; wherein in the signal write preparation stage, the light emission control signal is set to the turning-off voltage, the reset signal is set to the turning-off voltage, the scanning signal is set to the turning-off voltage, and the data signal is set to the invalid data signal.
  • the driving method provided in embodiments of the disclosure further comprises a pre-emission stage between the data write and threshold compensation stage and the light emission stage; wherein in the pre-emission stage, the scanning signal is set to the turning-off voltage, the reset signal is set to the turning-off voltage, the data signal is set to the invalid data signal, and the light emission control signal is set to the turning-off voltage.
  • FIG. 1 is a first schematic Diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a second schematic Diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a third schematic Diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a fourth schematic Diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 5A is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 5B to FIG. 5D provide three example wiring schematic diagrams with respect to reference voltage lines of the display panel of FIG. 5A ;
  • FIG. 6 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 7 is an exemplary driving timing chart of the pixel circuit as shown in FIG. 2 or FIG. 4 provided by embodiments of the present disclosure.
  • IR drop resistance voltage drop
  • the IR drop is caused by self-resistance voltage division of a wire in the display panel, that is, when a current passes through the wire (for example, a power supply line) in the display panel, a certain voltage drop will occur on the wire according to Ohm's law.
  • pixel units at different locations are affected by the IR drop to different extents, which results in unevenness of display of the display panel. Therefore, it is needed to compensate the IR drop in the OLED display panel.
  • threshold voltages of driving transistors in respective pixel units may be different from each other due to manufacture processes; and due to, for example, influence of change of temperature, the threshold voltages of the driving transistors may also drift. Therefore, difference in the threshold voltages of the respective driving transistors may also result in unevenness of display of the display panel. Therefore, it is also needed to compensate the threshold voltages of the driving transistors.
  • one terminal of a storage capacitor stores a data signal
  • the other terminal of the storage capacitor is connected with a certain reference voltage in the circuit.
  • one terminal of the storage capacitor is generally connected with a power supply line of the organic light-emitting diode or an output terminal of a certain thin film transistor to obtain the reference voltage, and so, when the IR drop is more noticeable, the reference voltage of the storage capacitor may become unstable.
  • the reference voltage is also associated with the thin film transistor, a switching process of the thin film transistor is also apt to cause fluctuation of the reference voltage.
  • the fluctuation of the reference voltage may further cause change in the data signal stored in the storage capacitor, resulting in occurrence of crosstalk or mura and other undesirable phenomena in display.
  • Embodiments of the present disclosure provide a pixel circuit, a display panel, a display device and a driving method.
  • a storage capacitor is connected with an independent and unaffected reference voltage, and thus, accuracy and stability of the data signal stored in the storage capacitor is increased.
  • a driving transistor can be implemented as a diode-conduction approach, which compensates the threshold voltage of the driving transistor, so as to eliminate the phenomenon of mura of the organic light-emitting diode caused by threshold voltage drift of the driving transistor.
  • a separate thin film transistor is used in a reset stage of the circuit for discharging of an organic light-emitting diode anode, which avoids abnormal light emission of the organic light-emitting diode.
  • the pixel circuit 100 comprises: a storage capacitor Cst, a first reset circuit 110 , a compensating circuit 120 , a driving transistor T 3 , a scanning circuit 140 , a light emission control circuit 150 , and an organic light-emitting diode (OLED).
  • a storage capacitor Cst As shown in FIG. 1 , the pixel circuit 100 comprises: a storage capacitor Cst, a first reset circuit 110 , a compensating circuit 120 , a driving transistor T 3 , a scanning circuit 140 , a light emission control circuit 150 , and an organic light-emitting diode (OLED).
  • OLED organic light-emitting diode
  • the storage capacitor Cst includes a first terminal and a second terminal, the first terminal being connected with a first node N 1 and a second terminal being connected with a reference voltage line to receive a reference voltage Vref.
  • the organic light-emitting diode (OLED) includes an anode and a cathode, the anode being connected with the second node N 2 , and the cathode being connected with a second power line to receive a second voltage Vss.
  • the driving transistor T 3 includes a gate electrode connected with the first node N 1 , and the driving transistor T 3 is configured to be turned on or off according to a voltage of the first node N 1 , so as to control the organic light-emitting diode (OLED) to emit light.
  • the first reset circuit 110 is connected with the first node N 1 , and is configured to supply an initial voltage Vini to the first node N 1 in response to a reset signal Reset.
  • the scanning circuit 140 is configured to supply a data signal Data to a third node N 3 in response to a scanning signal Gate.
  • the compensating circuit 120 is connected between the first node N 1 and a fourth node N 4 , and is configured to supply a compensating voltage to the first node N 1 in response to the scanning signal Gate.
  • the compensating voltage may be a sum of the data signal Data and a threshold voltage Vth of the driving transistor, e.g., “Data+Vth”.
  • the light emission control circuit 150 may be configured to control the organic light-emitting diode (OLED) to emit light in response to a light emission control signal EM.
  • OLED organic light-emitting diode
  • the light emission control circuit 150 may include: a first light emission control circuit 150 A and a second light emission control circuit 150 B.
  • the first light emission control circuit 150 A is configured to supply a first voltage Vdd of a first power line to the fourth node N 4 in response to the light emission control signal EM.
  • the second light emission control circuit 150 B is configured to conduct the third node N 3 to the second node N 2 (for example, to supply a voltage of the third node N 3 to the second node N 2 ) in response to the light emission control signal EM.
  • the first reset circuit 110 , the scanning circuit 140 , the compensating circuit 120 , the first light emission control circuit 150 A, and the second light emission control circuit 150 B may be at least implemented by using transistors.
  • FIG. 2 provides an example in which the first reset circuit 110 , the scanning circuit 140 , the compensating circuit 120 , the first light emission control circuit 150 A, and the second light emission control circuit 150 B are all transistors.
  • the first reset circuit 110 includes a first transistor T 1 , a first electrode of the first transistor T 1 is connected with an initial signal line to receive the initial voltage Vini, a gate electrode of the first transistor T 1 is connected with a reset signal line to receive the reset signal Reset, and a second electrode of the first transistor T 1 is connected with the first node N 1 .
  • the compensating circuit 120 includes a second transistor T 2 , a first electrode of the second transistor T 2 is connected with the first node N 1 , a gate electrode of the second transistor T 2 is connected with a scanning signal line to receive the scanning signal Gate, and a second electrode of the second transistor T 2 is connected with the fourth node N 4 .
  • the scanning circuit 140 includes a fourth transistor T 4 , a first electrode of the fourth transistor T 4 is connected with the data signal line to receive the data signal Data, a gate electrode of the fourth transistor T 4 is connected with the scanning signal to receive the scanning signal Gate, and a second electrode of the fourth transistor T 4 is connected with the third node N 3 .
  • a first electrode of the driving transistor T 3 is connected with the fourth node N 4
  • a gate electrode of the driving transistor T 3 is connected with the first node N 1
  • a second electrode of the driving transistor T 3 is connected with the third node N 3 .
  • the first light emission control circuit 150 A includes a fifth transistor T 5 , a first electrode of the fifth transistor T 5 is connected with a first power line to receive the first voltage Vdd, a gate electrode of the fifth transistor T 5 is connected with a light emission control signal line to receive the light emission control signal EM, and a second electrode of the fifth transistor T 5 is connected with the fourth node N 4 .
  • the second light emission control circuit 150 B includes a sixth transistor T 6 , a first electrode of the sixth transistor T 6 is connected with the third node N 3 , a gate electrode of the sixth transistor T 6 is connected with the light emission control signal line to receive the light emission control signal EM, and a second electrode of the sixth transistor T 6 is connected with the second node N 2 .
  • the pixel circuit shown in FIG. 1 or FIG. 2 receives an independent and unaffected reference voltage Vref by connecting the storage capacitor Cst with the reference voltage line, which ensures accuracy and stability of the data signal stored in the storage capacitor Cst.
  • the pixel circuit shown in FIG. 2 may also compensate for change of the threshold voltage of the driving transistor T 3 , so as to mitigate or eliminate a mura issue of the organic light-emitting diode caused by threshold voltage offset of the driving transistor.
  • FIG. 3 shows a pixel circuit 300
  • the pixel circuit 300 differs from the pixel circuit 100 provided by FIG. 1 in that the pixel circuit shown in FIG. 3 has an additional second reset circuit 370 .
  • the pixel circuit 300 not only comprises the storage capacitor Cst, the first reset circuit 310 , the compensating circuit 320 , the driving transistor T 3 , the scanning circuit 340 , the light emission control circuit 350 , and the organic light-emitting diode (OLED), but also comprises a second reset circuit 370 .
  • the second reset circuit 370 is configured to supply the initial voltage Vini to the second node N 2 in response to the reset signal.
  • the first reset circuit 310 , the scanning circuit 340 , the second reset circuit 370 and the compensating circuit 320 may be at least implemented by transistors.
  • the light emission control circuit 350 may include a fifth transistor and a sixth transistor.
  • FIG. 4 is an example of the pixel circuit shown in FIG. 3 .
  • the first reset circuit 310 includes the first transistor T 1 , the first electrode of the first transistor T 1 is connected with the initial signal line to receive the initial voltage Vini, the gate electrode of the first transistor T 1 is connected with the reset signal line to receive the reset signal Reset, and the second electrode of the first transistor T 1 is connected with the first node N 1 .
  • the compensating circuit 320 includes the second transistor T 2 , the first electrode of the second transistor T 2 is connected with the first node N 1 , the gate electrode of the second transistor T 2 is connected with the scanning signal line to receive the scanning signal Gate, and the second electrode of the second transistor T 2 is connected with the fourth node N 4 .
  • the scanning circuit 340 shown in FIG. 3 includes the fourth transistor T 4 , the first electrode of the fourth transistor T 4 is connected with the data signal line to receive the data signal Data, the gate electrode of the fourth transistor T 4 is connected with the scanning signal to receive the scanning signal Gate, and the second electrode of the fourth transistor T 4 is connected with the third node N 3 .
  • the first electrode of the driving transistor T 3 is connected with the fourth node N 4
  • the gate electrode of the driving transistor T 3 is connected with the first node N 1
  • the second electrode of the driving transistor T 3 is connected with the third node N 3 .
  • the second reset circuit 370 includes a seventh transistor T 7 , a first electrode of the seventh transistor T 7 is connected with the initial signal line to receive the initial voltage Vini, a gate electrode of the seventh transistor T 7 is connected with the reset signal line to receive the reset signal Reset, and a second electrode of the seventh transistor T 7 is connected with the second node N 2 .
  • the first electrode of the fifth transistor T 5 is connected with the first power line to receive the first voltage Vdd
  • the gate electrode of the fifth transistor T 5 is connected with the light emission control signal line to receive the light emission control signal EM
  • the second electrode of the fifth transistor T 5 is connected with the fourth node N 4 .
  • the first electrode of the sixth transistor T 6 is connected with the third node N 3
  • the gate electrode of the sixth transistor T 6 is connected with the light emission control signal line to receive the light emission control signal EM
  • the second electrode of the sixth transistor T 6 is connected with the second node N 2 .
  • the first transistor T 1 , the second transistor T 2 , the driving transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , the sixth transistor T 6 , and the seventh transistor T 7 shown in FIG. 4 are all P-type transistors.
  • the first transistor T 1 , the second transistor T 2 , the driving transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , the sixth transistor T 6 , and the seventh transistor T 7 shown in FIG. 4 are all thin film transistors.
  • the pixel circuit shown in FIG. 3 or FIG. 4 receives the independent and unaffected reference voltage Vref by connecting the storage capacitor Cst with the reference voltage line, which ensures accuracy and stability of the data signal stored in the storage capacitor Cst.
  • the pixel circuit shown in FIG. 3 or FIG. 4 may also compensate the threshold voltage of the driving transistor T 3 , so as to mitigate or eliminate mura of the organic light-emitting diode caused by threshold voltage offset of the driving transistor.
  • the pixel circuit shown in FIG. 4 may also discharge an anode of the organic light-emitting diode during circuit initialization by using the seventh transistor T 7 , so as to avoid abnormal light emission (crosstalk) of the organic light-emitting diode in an initial stage of an image frame.
  • all the transistors used in embodiments of the present disclosure may be thin film transistors or field-effect transistors or other switching devices of a same characteristic.
  • a source electrode and a drain electrode of the transistor used here may be symmetrical in structure, so that the source electrode and the drain electrode thereof may have no difference in structure.
  • one electrode therein is the first electrode, and the other electrode is the second electrode.
  • the first electrode and the second electrode of all or some of the transistors in the embodiments of the present disclosure may be interchangeable according to actual needs.
  • the first electrode of the transistor as described in the embodiments of the present disclosure may be a source electrode, and the second electrode may be a drain electrode; or, the first electrode of the transistor is a drain electrode, and the second electrode is a source electrode.
  • a transistor may be classified into an N-type transistor or a P-type transistor according to the characteristics of the transistor. In the embodiments of the present disclosure, it is illustrated with a case where the driving transistor T 3 , the first transistor T 1 , the second transistor T 2 , the driving transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , the sixth transistor T 6 and the seventh transistor T 7 are all P-type transistors as an example.
  • An embodiment of the present disclosure further provides a display panel 500 , and as shown in FIG. 5A , the display panel 500 comprises a plurality of pixel circuits 580 provided by any one of the embodiments of the present disclosure.
  • a pixel circuit 580 may be the pixel circuit shown in any one of FIG. 1 to FIG. 4 .
  • the display panel 500 may further comprise: a scanning signal line 511 , a reference voltage line 512 , a reset signal line 513 , a data signal line 521 , a first power line 523 , and a second power line 524 .
  • the data signal line 521 and the reset signal line 513 extend across each other, and the data signal line 521 and the scanning signal line 511 extend across each other.
  • the reference voltage line 512 is parallel to at least one of the data signal line 521 , the reset signal line 513 or the scanning signal line 511 (for example, as shown in FIG. 5A , the reference voltage line 512 is parallel to the reset signal line 513 and the scanning signal line 511 ).
  • a reference voltage Vref is introduced into a display region of an entire display device by using independent reference voltage lines 512 .
  • the reference voltage line 512 may be introduced laterally from both sides of the display region, and the reference voltage line 512 may connect a capacitance plate (e.g., a second terminal of the storage capacitor Cst shown in FIG. 1 ) of each of all the storage capacitors Cst in pixels of a same row together through a via hole 550 , and use the capacitance plate as a portion of a transverse wire of the reference voltage line.
  • a capacitance plate e.g., a second terminal of the storage capacitor Cst shown in FIG. 1
  • layout of the reference voltage line 512 may also be a longitudinal wire, which is connected with the capacitance plates of the storage capacitors through the via holes 550 to supply the reference voltage Vref to the capacitance plates of all pixels in a same column.
  • layout of the reference voltage lines 512 may also have both of the above-described connection approaches used at the same time (i.e., both lateral introduction and longitudinal introduction are used at the same time), so as to form a grid-like wiring.
  • a scan driving circuit 510 shown in FIG. 5A is configured to supply scanning signals Gate to a plurality of scanning signal lines 511 .
  • a data driving circuit 520 shown in FIG. 5A may provide the data signals Data to a plurality of data lines 521 .
  • the first power line 523 shown in FIG. 5A may be used for providing a first voltage Vdd
  • the second power line 524 is used for providing a second voltage Vss.
  • the first voltage Vdd is greater than the second voltage Vss.
  • the second voltage Vss may be a ground voltage.
  • An embodiment of the present disclosure further provides a display device 600 .
  • the display device 600 comprises a display panel 610 .
  • the display panel 500 provided by any one of the embodiments of the present disclosure may be referred to.
  • the display device 600 may further comprise a signal processing unit and the like, for performing signal reception, data decoding, and other operations.
  • the display device may comprise any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • An embodiment of the present disclosure further provides a driving method used in the pixel circuit 200 as shown in FIG. 2 .
  • the driving method may comprise a reset stage t 2 , a data write and threshold compensation stage t 4 , and a light emission stage t 6 .
  • a light emission control signal EM is set to a turning-off voltage
  • a reset signal Reset is set to a turning-on voltage
  • a scanning signal Gate is set to the turning-on voltage
  • a data signal Data is set to an invalid data signal.
  • the light emission control signal EM is set to the turning-off voltage
  • the reset signal Reset is set to the turning-off voltage
  • the scanning signal Gate is set to the turning-on voltage
  • the data signal Data is set to a valid data signal.
  • the light emission control signal EM is set to the turning-on voltage
  • the reset signal Reset is set to the turning-off voltage
  • the scanning signal Gate is set to the turning-off voltage
  • the data signal Data is set to the invalid data signal.
  • the turning-on voltage refers to a voltage that enables a first electrode and a second electrode of a corresponding transistor to be conducted
  • the turning-off voltage refers to a voltage that enables the first electrode and the second electrode of the corresponding transistor to be disconnected (turned off).
  • the transistor is a P-type transistor
  • the turning-on voltage is a low voltage (for example, 0V or other voltages)
  • the turning-off voltage is a high voltage (for example, 5V or other voltages)
  • the turning-on voltage is a high voltage (for example, 5V or other voltages)
  • the turning-off voltage is a low voltage (for example, 0V or other voltages).
  • Driving waveforms shown in FIG. 7 are all illustrated with the P-type transistors as an example, that is, the turning-on voltage of the corresponding transistor in FIG. 7 is a low voltage (for example, 0V or other voltages), and the turning-off voltage is a high voltage (for example, 5V or other voltages).
  • the invalid data signal is, for example, a low voltage signal (for example, 0 V)
  • the valid data signal is, for example, a signal including light emission data information
  • the valid data signal in FIG. 7 is illustrated with a high voltage signal as an example.
  • the driving method shown in FIG. 7 may further comprise a pre-reset stage t 1 , the pre-reset stage t 1 being located before the reset stage t 2 .
  • the light emission control signal EM is set to the turning-off voltage
  • the reset signal Reset is set to the turning-off voltage
  • the scanning signal Gate is set to the turning-off voltage
  • the data signal Data is set to the invalid data signal.
  • the driving method shown in FIG. 7 may further comprise a signal write preparation stage t 3 , the signal write preparation stage t 3 being located between the reset stage t 2 and the data write and threshold compensation stage t 4 .
  • the light emission control signal EM is set to the turning-off voltage
  • the reset signal Reset is set to the turning-off voltage
  • the scanning signal Gate is set to the turning-off voltage
  • the data signal Data is set to the invalid data signal.
  • the driving method shown in FIG. 7 may further comprise a pre-emission stage t 5 , the pre-emission stage t 5 being located between the data write and threshold compensation stage t 4 and the light emission stage t 6 .
  • the scanning signal Gate is set to the turning-off voltage
  • the reset signal Reset is set to the turning-off voltage
  • the data signal Data is set to the invalid data signal
  • the light emission control signal EM is set to the turning-off voltage.
  • An embodiment of the present disclosure further provides a driving method comprising the above-described six stages, i.e., the pre-reset stage t 1 , the reset stage t 2 , the signal write preparation stage t 3 , the data write and threshold compensation stage t 4 , the pre-emission stage t 5 , and the light emission stage t 6 .
  • the driving method comprising all the six stages is described, with a case where all the transistors involved are the P-type transistors as an example with reference to FIG. 2 and FIG. 4 .
  • an embodiment of the present disclosure provides a driving method comprising the above-described six stages used in the pixel circuit 200 of FIG. 2 .
  • the driving method comprises the following operations:
  • the reset signal Reset is at a high level; the scanning signal gate is at a high level; the first transistor T 1 , the second transistor T 2 and the fourth transistor T 4 are turned off; the light emission control line EM is at a high level, and at this point, the fifth transistor T 5 and the sixth transistor T 6 are turned off.
  • the pre-reset stage t 1 provides a pixel circuit stabilization process, to prevent the circuit from being abnormal and to prepare for the reset stage.
  • the reset signal Reset is at a low level; the first transistor T 1 is turned on; the scanning signal Gate is maintained at the high level; the second transistor T 2 and the fourth transistor T 4 are turned off; the light emission control signal EM is maintained at the high level; the fifth transistor T 5 and the sixth transistor T 6 are turned off; and the initial voltage Vini is transmitted to the first node N 1 through the first transistor T 1 to reset the first node N 1 .
  • the reset signal Reset is at a high level; the first transistor T 1 is turned off; the scanning signal Gate and the light emission control signal EM are maintained at the high level; the first transistor T 1 , the second transistor T 2 , the fourth transistor T 4 , the fifth transistor T 5 and the sixth transistor T 6 are turned off; the signal write preparation stage t 3 provides a pixel circuit stabilization process, to prevent the circuit from being abnormal and to prepare for the data write and threshold compensation stage.
  • the reset signal Reset is maintained at the high level; the scanning signal Gate is at a low level; a this point, the second transistor T 2 and the fourth transistor T 4 are turned on, and the data signal Data is transmitted to the third node N 3 through the fourth transistor T 4 . Since the second transistor T 2 is turned on, the gate electrode and the source electrode of the driving transistor T 3 are connected with each other, causing the driving transistor T 3 to form a diode structure. Since at this point a potential of the first node N 1 is the initial voltage Vini (for example, the low level) and the source electrode of the driving transistor T 3 is connected with a high-level data signal Data, the driving transistor T 3 is in a diode-turing-on state. Due to the threshold voltage of the driving transistor T 3 itself being Vth, when the driving transistor T 3 is turned on as a diode, the potential of the first node N 1 becomes Data+Vth, and then the driving transistor T 3 maintains a turning-off state.
  • the reset signal Reset is maintained at the high level; the scanning signal Gate is at a high level; and at this point, the storage capacitor Cst maintains a voltage at the first node N 1 as “Data+Vth”.
  • the pre-emission stage t 5 provides a pixel circuit stabilization process, to prevent the circuit from being abnormal.
  • a current Ion passing through the driving transistor T 3 is calculated with a formula below:
  • the current Ion passing through the driving transistor T 3 is not related to the threshold voltage of the driving transistor T 3 . That is, the threshold voltage of the driving transistor is compensated, which improves evenness of light emission of the organic light-emitting diode.
  • an embodiment of the present disclosure provides a driving method comprising the above-described six stages used in the pixel circuit 400 of FIG. 4 .
  • the driving method comprises the following operations:
  • the reset signal. Reset is at a high level; the scanning signal gate is at a high level; the first transistor T 1 , the second transistor T 2 , the fourth transistor T 4 and the seventh transistor T 7 are turned off, and the light emission control line EM is at a high level. At this point, the fifth transistor T 5 and the sixth transistor T 6 are turned off.
  • the pre-reset stage t 1 provides a pixel circuit stabilization process, to prevent the circuit from being abnormal and to prepare for the reset stage.
  • the reset signal Reset is at a low level
  • the first transistor T 1 and the seventh transistor T 7 are turned on
  • the scanning signal Gate is maintained at the high level
  • the second transistor T 2 and the fourth transistor T 4 are turned off
  • the light emission control signal EM are maintained at the high level
  • the fifth transistor T 5 and the sixth transistor T 6 are turned off
  • the initial voltage Vini is transmitted to the first node N 1 through the first transistor T 1 to reset the first node N 1 .
  • the initial voltage Vini is transmitted to the second node N 2 through the seventh transistor T 7 , to reset the second node N 2 , that is, to discharge an anode of the organic light-emitting diode, so as to avoid abnormal light emission of the organic light-emitting diode.
  • the reset signal Reset is at a high level
  • the first transistor T 1 and the seventh transistor T 7 are turned off
  • the scanning signal Gate and the light emission control signal EM are maintained at the high level.
  • the first transistor T 1 , the second transistor T 2 and the fourth transistor T 4 , the fifth transistor T 5 and the sixth transistor T 6 are turned off.
  • the signal write preparation stage t 3 provides a pixel circuit stabilization process, to prevent the circuit from being abnormal and to prepare for the data write and threshold compensation stage.
  • the reset signal Reset is maintained at the high level
  • the scanning signal Gate is at a low level
  • the second transistor T 2 and the fourth transistor T 4 are turned on
  • the data signal Data is transmitted to the third node N 3 through the fourth transistor T 4 ; since the second transistor T 2 is turned on, the gate electrode and the source electrode of the driving transistor T 3 are connected with each other, causing the driving transistor T 3 to form a diode structure; since at this point a potential of the first node N 1 is the initial voltage Vini (for example, the low level) and the source electrode of the driving transistor T 3 is connected with a high-level data signal Data, the driving transistor T 3 is in a diode-turning-on state. Due to the threshold voltage of the driving transistor T 3 itself being Vth, when the driving transistor T 3 is turned on as the diode, the potential of the first node N 1 becomes “Data+Vth”, and then the driving transistor T 3 maintains a turning-off state.
  • the reset signal Reset is maintained at the high level
  • the scanning signal Gate is at a high level
  • the storage capacitor Cst maintains a voltage at the first node N 1 as “Data+Vth”.
  • the pre-emission stage t 5 provides a pixel circuit stabilization process, to prevent the circuit from being abnormal.
  • a current output from the driving transistor T 3 is proportional to a square of the voltage difference between the data signal and the first power line, and is irrelevant to the threshold voltage of the driving transistor T 3 itself; and therefore, it is able to avoid mura of the organic light-emitting diode caused by the threshold voltage offset.
  • a light-emitting display including the pixel circuit can have even and stable images.
  • the seventh transistor T 7 is also used in the circuit reset stage for discharging the anode of the organic light-emitting diode, so as to avoid abnormal light emission of the organic light-emitting diode.
  • the storage capacitor is connected with the independent and unaffected reference voltage, which ensures accuracy and stability of the data signal stored in the storage capacitor.
  • the above description in the embodiments of the present disclosure is provided with the P-type transistors as an example, and the embodiments of the present disclosure may also be implemented with the N-type transistors as well.

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