UA93732U - driver ofThree-pulse SINGLE CODE SERIES with programmable time parameters - Google Patents
driver ofThree-pulse SINGLE CODE SERIES with programmable time parametersInfo
- Publication number
- UA93732U UA93732U UAU201405299U UAU201405299U UA93732U UA 93732 U UA93732 U UA 93732U UA U201405299 U UAU201405299 U UA U201405299U UA U201405299 U UAU201405299 U UA U201405299U UA 93732 U UA93732 U UA 93732U
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Abstract
The driver of single three-pulse code series with programmable time parameters includes two reversible binary counters which have input of synchronization pulses, input of adjustment to the addition / subtraction mode, input pf permit of synchronous parallel loading and data inputs, counting mode permit input, the input of asynchronous installation to zero state, the overflow output; inverter; first and second OR elements; circuit of connected in series resistor and capacitor; synchronous D-flip-flop with input of asynchronous installation to zero state, the first and second two-input elements AND. Are included: third, fourth and fifth elements OR; a second inverter; NOR element; second synchronous D-flip-flop with input of asynchronous installation of zero state; the first and second JK-flip-flops with input of asynchronous installation to zero state, at that the inputs of the second OR gate are connected to the outputs of the second, third and fourth bits of the first counter and the output of the NOR element; first counter overflow output is connected to the inputs of the first, third and fourth OR elements; second counter overflow output is connected to the second input of the first and the fourth elements OR, input of the second inverter, its output is connected to the second inputs of the first AND element, and the third OR gate; output of the third OR gate is connected to the input of permit of counting mode of the second counter; output of the fourth OR gate is connected to the J and K inputs of the first JK-flip-flop, the first input of the fifth OR gate and the first input of the NOR element; the second input of the element NOR is connected to the inverted output of the first JK-flip-flop; direct output of the first JK-flip-flop is connected to the second input of the fifth element OR and the input of permit of synchronous parallel loading of the second counter; direct output of the second JK-flip-flop is connected to the input D of the second D-trigger output of which is connected to the input of the first OR gate; the output of the fifth OR gate is connected to the inputs J and K of the second JK-flip-flop; the clock inputs of the second D-flip-flop and JK-flip-flops are connected to the driver input; inputs of asynchronous installation to zero state of the second D-flip-flop and the JK-flip-flops are connected to the output of the second element AND.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
UAU201405299U UA93732U (en) | 2014-05-19 | 2014-05-19 | driver ofThree-pulse SINGLE CODE SERIES with programmable time parameters |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
UAU201405299U UA93732U (en) | 2014-05-19 | 2014-05-19 | driver ofThree-pulse SINGLE CODE SERIES with programmable time parameters |
Publications (1)
Publication Number | Publication Date |
---|---|
UA93732U true UA93732U (en) | 2014-10-10 |
Family
ID=56277657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
UAU201405299U UA93732U (en) | 2014-05-19 | 2014-05-19 | driver ofThree-pulse SINGLE CODE SERIES with programmable time parameters |
Country Status (1)
Country | Link |
---|---|
UA (1) | UA93732U (en) |
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2014
- 2014-05-19 UA UAU201405299U patent/UA93732U/en unknown
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