UA93723U - driver of periodic sequence of two-pulse CODE SERIES with programmable parameters - Google Patents

driver of periodic sequence of two-pulse CODE SERIES with programmable parameters

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Publication number
UA93723U
UA93723U UAU201405273U UAU201405273U UA93723U UA 93723 U UA93723 U UA 93723U UA U201405273 U UAU201405273 U UA U201405273U UA U201405273 U UAU201405273 U UA U201405273U UA 93723 U UA93723 U UA 93723U
Authority
UA
Ukraine
Prior art keywords
input
output
gate
flip
inputs
Prior art date
Application number
UAU201405273U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Микола Григорович Коробков
Олена Миколаївна Коробкова
Артем Євгенович Перепелицин
Вячеслав Сергійович Харченко
Original Assignee
Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут" filed Critical Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority to UAU201405273U priority Critical patent/UA93723U/en
Publication of UA93723U publication Critical patent/UA93723U/en

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  • Manipulation Of Pulses (AREA)

Abstract

Driver of periodic sequence of two-pulse code series with programmable parameters which comprises two reversible binary counters each of which has input for synchronization pulses, input for adjustment to the addition / subtraction mode, input for permit of synchronous parallel loading and data input, input of counting mode permit, input of asynchronous installation to zero state, the overflow output; inverter; first and second OR elements; chain of connected in series resistor and capacitor; synchronous D-flip-flop with input of asynchronous installation to zero state, the first and second two-input elements AND. Are included: third, fourth and fifth elements OR; second and third inverters; NOR element; first and second synchronous DL-triggers with inputs of asynchronous installation to zero state, and the inputs of the second OR gate connected to the outputs of the second, third and fourth bits of the first counter and the output of the element AND-NOT; first counter overflow output is connected to the first inputs of the third and fourth elements OR; second counter overflow output is connected to the second input of the fourth OR gate and the input of the second inverter, its output is connected to the second input of the third OR gate; the output of the third OR gate is connected to the permit input of the second counter counting mode; the output of the fourth OR gate is connected to the inverted inputs L of the DL flip-flops and the first input of the NOR element; the second input of OR-NOT element is connected to the output of the third inverter; direct output of the first DL-trigger is connected to the input D of the second DL-trigger and the first input of the fifth element OR; inverted output of the second DL-flip-flop is connected to the input D of the first DL-trigger; direct output of the second DL-flip-flop is connected to the second input of the fifth OR element; the output of the fifth OR gate is connected to the second input of the first OR gate and the input of permit of synchronous parallel loading of the second counter; clock inputs of DL- flip-flops are connected to the input of the driver; inputs of asynchronous installation to zero state of the DL-flip-flops are connected to the output of the second element.
UAU201405273U 2014-05-19 2014-05-19 driver of periodic sequence of two-pulse CODE SERIES with programmable parameters UA93723U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201405273U UA93723U (en) 2014-05-19 2014-05-19 driver of periodic sequence of two-pulse CODE SERIES with programmable parameters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201405273U UA93723U (en) 2014-05-19 2014-05-19 driver of periodic sequence of two-pulse CODE SERIES with programmable parameters

Publications (1)

Publication Number Publication Date
UA93723U true UA93723U (en) 2014-10-10

Family

ID=56277648

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201405273U UA93723U (en) 2014-05-19 2014-05-19 driver of periodic sequence of two-pulse CODE SERIES with programmable parameters

Country Status (1)

Country Link
UA (1) UA93723U (en)

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