UA93714U - driver of periodic sequence of two pulse CODE SERIES with programmable parameters - Google Patents

driver of periodic sequence of two pulse CODE SERIES with programmable parameters

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Publication number
UA93714U
UA93714U UAU201405242U UAU201405242U UA93714U UA 93714 U UA93714 U UA 93714U UA U201405242 U UAU201405242 U UA U201405242U UA U201405242 U UAU201405242 U UA U201405242U UA 93714 U UA93714 U UA 93714U
Authority
UA
Ukraine
Prior art keywords
input
driver
pulse code
periodic sequence
programmable parameters
Prior art date
Application number
UAU201405242U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Микола Григорович Коробков
Олена Миколаївна Коробкова
Василь Григорович Рубанов
Вячеслав Сергійович Харченко
Original Assignee
Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут" filed Critical Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority to UAU201405242U priority Critical patent/UA93714U/en
Publication of UA93714U publication Critical patent/UA93714U/en

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Abstract

Driver of periodic sequence of two pulse code series with programmable parameters comprises two reversible binary counters, each of those has an input for synchronization pulses, input of adjustment to the addition / subtraction mode, input of permit of synchronous parallel loading and data inputs, input of permit of counting mode, the input of asynchronous installation to zero state, the overflow output; inverter; first and second OR elements; circuit of connected in series resistor and capacitor; synchronous D-flip-flop with input of asynchronous installation to zero state, the first and second two-input elements AND. There are included the first and the second elements AND-NOT; a second inverter; OR-NOT element; JK-flip-flop with input of asynchronous installation to zero state.
UAU201405242U 2014-05-19 2014-05-19 driver of periodic sequence of two pulse CODE SERIES with programmable parameters UA93714U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201405242U UA93714U (en) 2014-05-19 2014-05-19 driver of periodic sequence of two pulse CODE SERIES with programmable parameters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201405242U UA93714U (en) 2014-05-19 2014-05-19 driver of periodic sequence of two pulse CODE SERIES with programmable parameters

Publications (1)

Publication Number Publication Date
UA93714U true UA93714U (en) 2014-10-10

Family

ID=56277639

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201405242U UA93714U (en) 2014-05-19 2014-05-19 driver of periodic sequence of two pulse CODE SERIES with programmable parameters

Country Status (1)

Country Link
UA (1) UA93714U (en)

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