UA93738U - driver of SINGLE two-pulse CODE SERIES with programmable time parameters - Google Patents

driver of SINGLE two-pulse CODE SERIES with programmable time parameters

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Publication number
UA93738U
UA93738U UAU201405326U UAU201405326U UA93738U UA 93738 U UA93738 U UA 93738U UA U201405326 U UAU201405326 U UA U201405326U UA U201405326 U UAU201405326 U UA U201405326U UA 93738 U UA93738 U UA 93738U
Authority
UA
Ukraine
Prior art keywords
input
inverter
output
gate
counter
Prior art date
Application number
UAU201405326U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Микола Григорович Коробков
Олена Миколаївна Коробкова
Василь Григорович Рубанов
Вячеслав Сергійович Харченко
Original Assignee
Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут" filed Critical Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority to UAU201405326U priority Critical patent/UA93738U/en
Publication of UA93738U publication Critical patent/UA93738U/en

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  • Manipulation Of Pulses (AREA)

Abstract

Driver of single two-pulse code series with programmable time parameters which includes two reversible binary counters each of which has an input of synchronization pulses, the input of adjustment to addition / subtraction mode, input of permit of synchronous parallel loading and data inputs, input of permit of counting mode, input of asynchronous installation to zero state, the overflow output; inverter; first and second OR elements; circuit comprising connected in series resistor and capacitor; synchronous D-flip-flop with an input of asynchronous installation to zero state, the first and second two-input elements AND. Are included: third and fourth OR elements; the second inverter, at that the second input of the first AND gate is connected to the output of the second inverter, the inputs of the second OR gate are connected to the outputs of the second, third and fourth bits of the first counter; second counter overflow output is connected to the input of the second inverter and the input of the third OR gate output of which is connected to the input of permit of parallel loading of the second counter; the output of the second inverter is connected to the first input of the fourth OR gate; the second inputs of the third and fourth members OR are connected to overflow output of the first counter.
UAU201405326U 2014-05-19 2014-05-19 driver of SINGLE two-pulse CODE SERIES with programmable time parameters UA93738U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201405326U UA93738U (en) 2014-05-19 2014-05-19 driver of SINGLE two-pulse CODE SERIES with programmable time parameters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201405326U UA93738U (en) 2014-05-19 2014-05-19 driver of SINGLE two-pulse CODE SERIES with programmable time parameters

Publications (1)

Publication Number Publication Date
UA93738U true UA93738U (en) 2014-10-10

Family

ID=56277663

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201405326U UA93738U (en) 2014-05-19 2014-05-19 driver of SINGLE two-pulse CODE SERIES with programmable time parameters

Country Status (1)

Country Link
UA (1) UA93738U (en)

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