UA93734U - driver of periodic sequence of two-pulse CODE SERIES with programmable parameters - Google Patents
driver of periodic sequence of two-pulse CODE SERIES with programmable parametersInfo
- Publication number
- UA93734U UA93734U UAU201405313U UAU201405313U UA93734U UA 93734 U UA93734 U UA 93734U UA U201405313 U UAU201405313 U UA U201405313U UA U201405313 U UAU201405313 U UA U201405313U UA 93734 U UA93734 U UA 93734U
- Authority
- UA
- Ukraine
- Prior art keywords
- input
- flip
- output
- flop
- gate
- Prior art date
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- Analogue/Digital Conversion (AREA)
Abstract
A driver of periodic sequence of two-pulse code series with programmable parameters which comprises two reversible binary counters each of which has an input of synchronization pulses, input for adjustment to the addition / subtraction mode, input of permit of synchronous parallel loading and data input, input of permit of counting mode, input of asynchronous installation to zero state, the overflow output; inverter; first and second OR elements; circuit of connected in series resistor and capacitor; synchronous D-flip-flop with input of asynchronous installation of zero state, the first and second two-input elements AND. Are included: third and fourth OR elements; second inverter; NOR element; the first JK-flip-flop which has two inputs J, one of which is a direct, the second inverted, connected by AND, one inverted input K and input of asynchronous installation to zero state; the second JK-flip-flop, which has two inputs K, one of which is a direct, the second inverted, and connected by AND, one inverted input J and input of asynchronous installation to zero state; at that the inverse output of the first JK-flip-flop is connected to the direct input K of the second JK- flip-flop; inverted output of the second JK-flip-flop is connected to the direct input J of the first JK-flip-flop; the inputs of second OR gate are connected to the outputs of the second, third and fourth bits of the first counter; first counter overflow output is connected to the first inputs of the third and fourth elements OR; second counter overflow output is connected to the second input of the fourth OR gate and the input of the second inverter, output of that is connected to the second input of the third OR gate; output of the third OR gate is connected to the input of permit of the second counter counting mode; output of the fourth OR gate is connected to the inverted inputs J and K of the JK-flip-flops and the first input of OR-NOT element output of which is connected to the fourth input of the second OR gate; the second input of the OR- NOT element is connected to the inverted output of the second JK-flip-flop; direct output of the second JK-flip-flop is connected to the second input of the first OR gate and the input of permit of synchronous parallel loading of the second counter; clock inputs of JK-flip-flops are connected to the input of the driver; inputs of asynchronous installation to zero state of JK-flip-flops are connected to the output of the first OR gate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
UAU201405313U UA93734U (en) | 2014-05-19 | 2014-05-19 | driver of periodic sequence of two-pulse CODE SERIES with programmable parameters |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
UAU201405313U UA93734U (en) | 2014-05-19 | 2014-05-19 | driver of periodic sequence of two-pulse CODE SERIES with programmable parameters |
Publications (1)
Publication Number | Publication Date |
---|---|
UA93734U true UA93734U (en) | 2014-10-10 |
Family
ID=56277659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
UAU201405313U UA93734U (en) | 2014-05-19 | 2014-05-19 | driver of periodic sequence of two-pulse CODE SERIES with programmable parameters |
Country Status (1)
Country | Link |
---|---|
UA (1) | UA93734U (en) |
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2014
- 2014-05-19 UA UAU201405313U patent/UA93734U/en unknown
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