UA99192U - shaper of SINGLE Double-pulse CODE SERIES with programmable time parameters - Google Patents

shaper of SINGLE Double-pulse CODE SERIES with programmable time parameters

Info

Publication number
UA99192U
UA99192U UAU201412592U UAU201412592U UA99192U UA 99192 U UA99192 U UA 99192U UA U201412592 U UAU201412592 U UA U201412592U UA U201412592 U UAU201412592 U UA U201412592U UA 99192 U UA99192 U UA 99192U
Authority
UA
Ukraine
Prior art keywords
input
shaper
pulse code
time parameters
single double
Prior art date
Application number
UAU201412592U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Микола Григорович Коробков
Олена Миколаївна Коробкова
Василь Григорович Рубанов
Вячеслав Сергійович Харченко
Original Assignee
Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут" filed Critical Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority to UAU201412592U priority Critical patent/UA99192U/en
Publication of UA99192U publication Critical patent/UA99192U/en

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Shaper of single double-pulse code series with programmable time parameters includes a reversible binary counter that is set to the subtraction mode, having an input for synchronization pulses, input of adjustment to addition / subtraction mode, input of permit of count mode, input of permit of synchronous parallel data loading and data input, input of asynchronous installation to the zero state, the overflow output; synchronous D-flip-flop with input of asynchronous installation to zero state; inverter; first and second OR elements; first and second AND gates; chain. Are included: synchronous first, second DL-triggers, and JK-trigger with inputs of asynchronous installation to zero state; third and fourth AND gates; the third element OR- AND.
UAU201412592U 2014-11-24 2014-11-24 shaper of SINGLE Double-pulse CODE SERIES with programmable time parameters UA99192U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201412592U UA99192U (en) 2014-11-24 2014-11-24 shaper of SINGLE Double-pulse CODE SERIES with programmable time parameters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201412592U UA99192U (en) 2014-11-24 2014-11-24 shaper of SINGLE Double-pulse CODE SERIES with programmable time parameters

Publications (1)

Publication Number Publication Date
UA99192U true UA99192U (en) 2015-05-25

Family

ID=53675132

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201412592U UA99192U (en) 2014-11-24 2014-11-24 shaper of SINGLE Double-pulse CODE SERIES with programmable time parameters

Country Status (1)

Country Link
UA (1) UA99192U (en)

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