UA98700U - Shaper of single packs of two three pulse code series of time-programmable parameters - Google Patents

Shaper of single packs of two three pulse code series of time-programmable parameters

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Publication number
UA98700U
UA98700U UAU201410133U UAU201410133U UA98700U UA 98700 U UA98700 U UA 98700U UA U201410133 U UAU201410133 U UA U201410133U UA U201410133 U UAU201410133 U UA U201410133U UA 98700 U UA98700 U UA 98700U
Authority
UA
Ukraine
Prior art keywords
inputs
zero state
shaper
input
asynchronous
Prior art date
Application number
UAU201410133U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Микола Григорович Коробков
Олена Миколаївна Коробкова
Василь Григорович Рубанов
Вячеслав Сергійович Харченко
Original Assignee
Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут" filed Critical Національний Аерокосмічний Університет Ім. М.Є. Жуковського "Харківський Авіаційний Інститут"
Priority to UAU201410133U priority Critical patent/UA98700U/en
Publication of UA98700U publication Critical patent/UA98700U/en

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Shaper of single packs of two three pulse code series of time-programmable parameters are multiples of the period of continuous periodic sequence of pulses applied to the input from the output of crystal oscillator contains a comparator inputs of the first group is connected to the respective outputs of binary counter that has input permission mode synchronous parallel load and load data inputs, entry permit counting mode and asynchronous input settings in the zero state. Put another binary counter, as well as first established in subtraction mode, with simultaneous parallel inputs boot entrance permit counting mode and asynchronous input settings in the zero state; binary adder; five inverters; JK-flip-flop, the first and second synchronous D-flip-flops with asynchronous inputs settings in the zero state; chotyryvhodovyy element OR-NOT; dvovhodovyy NAND element; first, second and third elements dvovhodovi I; the first and second elements OR; chain.
UAU201410133U 2014-09-15 2014-09-15 Shaper of single packs of two three pulse code series of time-programmable parameters UA98700U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201410133U UA98700U (en) 2014-09-15 2014-09-15 Shaper of single packs of two three pulse code series of time-programmable parameters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201410133U UA98700U (en) 2014-09-15 2014-09-15 Shaper of single packs of two three pulse code series of time-programmable parameters

Publications (1)

Publication Number Publication Date
UA98700U true UA98700U (en) 2015-05-12

Family

ID=53674563

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201410133U UA98700U (en) 2014-09-15 2014-09-15 Shaper of single packs of two three pulse code series of time-programmable parameters

Country Status (1)

Country Link
UA (1) UA98700U (en)

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