TWM472946U - 晶粒封裝結構 - Google Patents

晶粒封裝結構 Download PDF

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Publication number
TWM472946U
TWM472946U TW102200928U TW102200928U TWM472946U TW M472946 U TWM472946 U TW M472946U TW 102200928 U TW102200928 U TW 102200928U TW 102200928 U TW102200928 U TW 102200928U TW M472946 U TWM472946 U TW M472946U
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TW
Taiwan
Prior art keywords
die
package
package substrate
substrate
external connection
Prior art date
Application number
TW102200928U
Other languages
English (en)
Inventor
Shih-Chi Chen
Original Assignee
Standard Technology Service Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Technology Service Inc filed Critical Standard Technology Service Inc
Priority to TW102200928U priority Critical patent/TWM472946U/zh
Priority to US13/920,468 priority patent/US9299626B2/en
Publication of TWM472946U publication Critical patent/TWM472946U/zh
Priority to US15/049,587 priority patent/US9466592B2/en

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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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Description

晶粒封裝結構
本創作揭露一種晶粒封裝結構，利用晶圓級封裝製程及簡單的打線製程來形成晶粒封裝結構，特別是一種將記憶體晶粒以打線製程來形成晶粒封裝結構。
半導體技術之發展非常地快速，特別是半導體晶片(semiconductor dice)有趨於小型化之傾向。然而，半導體晶片之功能需求卻有相對多樣化之傾向。換言之，半導體晶片於較小區域中需求更多的輸入/輸出墊(pads)，所以引腳(pins)之密度也隨之快速的提高。其導致半導體晶片之封裝變得更困難且降低良率。封裝結構之主要目的在於保護晶片免受外部損傷。然而，大部份封裝技術是先將一晶圓上晶片切割成複數個單一晶片，然後再封裝與測試每一顆單一晶片。另外，一種稱為「晶圓級封裝」(wafer level package；WLP)之封裝技術，可以在分割晶片成為單一晶片之前，於晶圓上封裝晶片。晶圓級封裝技術有一些優點，例如生產週期較短、成本較低以及不需要填充物(under-fill)。
本創作的主要目的在於揭露一種晶粒封裝結構，係將封裝基板經由對準設置後固著在晶粒上，使得位於晶粒之中間區域的焊墊曝露於設置於封裝基板上之中間區域之開口，並藉由打線方式電性連接，並經由另一封裝體封裝之後曝露出封裝基板區塊上之外部連接端點，以具有基板之晶粒封裝結構。
本創作之再一目的係在於本創作所揭露之晶粒封裝結構，特別適用在大型晶片之封裝製程，例如記憶體，特別是NAND快閃記憶體晶粒(NAND Flash)、NOR快閃記憶體晶粒(NOR Flash)、通訊晶片及一些特殊應 用晶片(Application-specific Ic；ASIC)。
本創作之又一目的在於所揭露之封裝結構，其一面是曝露出多數個外部連接端點，作為對外連接之端點，而相對於外部連接端點的另一面則是晶粒的背面，故本創作之封裝結構可以達到良好的散熱效果，而此一散熱效果對於大型晶片是非常重要的。
根據以上所述之目的，本創作係提供一種晶粒封裝結構，包括：晶粒，於晶粒之主動面之中間區域上具有多數個焊墊；封裝基板，於封裝基板之中間區域配置有開口，且環繞於開口之側邊配置有多數個連接點，在封裝基板之四個側邊配置有多數個外部連接端點，多數個連接點係藉由多數條第一金屬導線與多數個外部連接端點電性連接，其中將封裝基板之背面藉由黏著層與晶粒固接，使得晶粒之中間區域上之多數個焊墊於封裝基板之開口曝露出來；多數條第二金屬導線，係將封裝基板之中間區域之多數個連接點電性連接於晶粒之中間區域之多數個焊墊；封裝體，包覆封裝基板、晶粒及多數條第二金屬導線且曝露出在封裝基板上之多數個外部連接端點；以及多數個導電元件，與多數個外部連接端點電性連接並配置在封裝結構之四個側邊上。
本創作還揭露另外一種晶粒封裝結構，包括：晶粒，於晶粒之主動面之中間區域上具有多數個焊墊；封裝基板，且於封裝基板之中間區域配置有開口，且環繞開口之側邊配置有多數個連接點，及在封裝基板之四個側邊配置有多數個外部連接端點，多數個連接點與多數個外部連接端點經由多數條第一金屬導線電性連接，其中，將封裝基板之背面藉由黏著層與晶粒固接，使得晶粒之中間區域上之多數個焊墊於封裝基板之開口中曝露出來，且封裝基板上之多數個外部連接端點向外延伸大於晶粒之側邊；多數條第二金屬導線，係將封裝基板之中間區域上之多數個連接點電性連接於晶粒之中間區域之多數個焊墊；以及封裝體，包覆封裝基板、晶粒之主動面及多數條第二金屬導線且將多數個外部連接端點曝露在封裝體之外側。
本創作之上述及其他目的與優點，不難從下述所選用實施例之詳細說明與附圖中，獲得深入了解。
當然，本創作在某些另件上，或另件之安排上容許有所不同，但所選用之實施例，則於本說明書中，予以詳細說明，並於附圖中展示其構造。
10‧‧‧晶圓
101‧‧‧晶粒
1012‧‧‧主動面
1014‧‧‧焊墊
30‧‧‧封裝基板
31‧‧‧正面
32‧‧‧背面
33‧‧‧開口
302、303‧‧‧連接點
304‧‧‧外部連接端點
306‧‧‧第一金屬導線
40‧‧‧第二金屬導線
50‧‧‧封裝體
60‧‧‧導電元件
70、80‧‧‧晶粒封裝結構
第1圖係表示在晶圓上具有多數個晶粒之俯視圖。
第2A圖係表示封裝基板之正面俯視圖。
第2B圖係表示封裝基板之背面俯視圖。
第3圖係表示在第2A圖及第2B圖之具有複數個連接點及多數條線路之封裝基板與晶粒結合之俯視圖。
第4A圖係表示在第3圖中以Y1-Y1方向截面示意圖。
第4B圖係表示於第4A圖之結構中形成封裝體之截面示意圖。
第5A圖係表示在第3圖之結構中以Y2-Y2方向之截面示意圖。
第5B圖係表示在第5A圖之結構中形成導電元件之截面示意圖。
第5C圖係表示完成電鍍製程之後之封裝基板之背面之示意圖。
第6圖係表示在第2A圖及第2B圖之具有複數個連接點及多數條線路之封裝基板與晶粒結合之俯視圖。
第7A圖係表示在第6圖之結構中以X-X方向之截面示意圖。
第7B圖係表示將第7A圖中之結構以網印製程形成封裝體之截面示意圖。
第7C圖係表示利用沖壓製程將封裝基板之多數個外部連接端形成具有內引腳及外引腳之導線架之結構之截面示意圖。
本創作在此所探討的方向為一種晶粒封裝結構，特別是利用簡單的打線製程來形成晶圓級封裝結構，故稱為一種打線晶圓級封裝 (Wire-Bonding Chip Scale Package；WBCSP)，可適用於大型晶片的封裝結構，且由於封裝結構上之結構簡單，且可以節省封裝成本。為了能徹底地瞭解本創作，將在下列的描述中提出詳盡的步驟及其組成。眾所周知的晶粒及電路基板之製作方式及詳細步驟並未描述於細節中，以避免造成本創作不必要之限制。然而，對於本創作的較佳實施例，則會詳細描述如下，然而除了這些詳細描述之外，本創作還可以廣泛地施行在其他的實施例中，且本創作的範圍不受限定，其以之後的專利範圍為準。
首先，請參考第1圖。第1圖係表示本創作之晶圓上具有多數個晶粒之俯視圖。在第1圖中，其晶圓10上具有多數個晶粒101，每一個晶粒101具有主動面1012及背面(未在圖中表示)。於晶粒101的主動面1012之一中間區域上配置有多數個焊墊1014，其中每一個焊墊1014可以選擇藉由重配置層(redistribution layer)製程來完成配置在晶粒101的主動面(未在圖中表示)之中間區域。要說明的是，在第1圖中所揭露之晶圓10上之多數個晶粒101係為已經完成製造之晶粒，這些晶粒可以是大型晶粒之封裝製程，例如記憶體晶片，特別是NAND快閃記憶體晶粒(NAND Flash)或NOR快閃記憶體晶粒(NOR Flash)、通訊晶片及一些特殊應用晶片(Application-specific Ic；ASIC)。在本創作之實施例中，將以儲存型快閃記憶體晶粒做說明，特別是以具有48個接腳之儲存型快閃記憶體(NAND Flash)晶粒來做說明，然而上述晶粒之製作過程及重配置層(redistribution layer)製程並非本創作主要的技術內容，故不在此多加描述。
接著，請參考第2A圖。第2A圖係表示本創作在封裝基板之正面俯視圖。封裝基板30具有正面31及背面32，於封裝基板30之中間區域配置有一開口33，作為在封裝基板30與晶粒101接合後(見第3圖)，可使得位於晶粒101之中間區域的多數個焊墊1014能夠經由此開口33而曝露出來，且鄰近於開口33的四個側邊配置有多數個連接點302，而於封裝基板30的四個側邊上配置有多數個外部連接端點304，而這些外部連接端點304是貫穿封裝基板30之正面及背面。在本創作中所揭露之多數個連接點302可以是一種金手指結構(golden finger)或一種金屬引線(metal trace)；當連接點302為金手指結構時，其可以藉由絕緣材料(例如塑膠)(未在圖中 表示)或是陶瓷材料(ceramic)(未在圖中表示)來隔離每一個連接點302；另外，在本創作的實施例中，封裝基板30可以是可撓性基板(flexible substrate)或是硬性基板(rigid substrate)。另外，以硬性基板而言，封裝基板30可以是單層的印刷電路板(PCB)或是多層的印刷電路板。另外，以可撓性基板而言，可以是由高分子材料與導線架(lead frame)所形成。
接著，請參考第2B圖。第2B圖係表示本創作在封裝基板之背面俯視圖。在第2B圖中，於封裝基板30之背面32上，可以看到封裝基板30的四個側邊上配置有多數個外部連接端點304。
接著，請參考第3圖。第3圖係表示本創作在第2A圖及第2B圖之具有複數個連接點及多數條線路之封裝基板與晶粒結合之俯視圖。在第3圖中，封裝基板30之正面31之中間區域配置有一開口33，且於開口33之側邊係配置有多數個連接點302。另外，在封裝基板30之四個側邊配置有多數個外部連接端點304，而這些連接點302與外部連接端點304係以多數條第一金屬導線306彼此電性連接。
接著，請再參考第3圖。在本創作的實施例中，由於封裝基板30的尺寸小於晶粒101的尺寸，因此當封裝基板30係以背面32藉由黏著層(未在圖中表示)固著在晶粒101上時，在晶粒101之中間區域的多數個焊墊1014會由位於封裝基板30之中間區域的開口33中曝露出來，且配置在封裝基板30之四個側邊的多數個外部連接端點304，其長度可大於晶粒101之側邊的長度、或是與晶粒101之側邊的長度相同。
同樣的，請繼續參考第3圖。當封裝基板30與晶粒101黏著成一體後，由於封裝基板30上的每一個連接點302與晶粒101上的焊墊1014均曝露並呈對應排列後，接著，即可利用打線製程(wire bonding process)將多數條第二金屬導線40同時形成在封裝基板30上的每一個連接點302及晶粒101的每一個焊墊1014上，使得晶粒101與所對應的封裝基板30可以彼此電性連接。
接著請參考第4A圖。第4A圖係表示在第3圖中以Y1-Y1方向截面示意圖。由第3圖中可以得到在完成打線製程之後，於Y1-Y1方向之封裝基板30配置在晶粒101上之截面示意圖。緊接著，請參考4B圖。 在第4B圖中，係於前述步驟完成打線製程之後，利用網印的方式將封裝材料形成在封裝基板30上以形成一封裝體50，且此封裝體50包覆住封裝基板30、多數條金屬導線40及晶粒101之部份主動面1012。
另外，請參考第5A圖。第5A圖係表示在第3圖中以Y2-Y2方向之截面示意圖。於第5A圖中，若在第3圖中以Y2-Y2方向截面(即由多數個外部連接端點304上之截面)，可以得到在完成打線製程之後，於Y2-Y2方向之封裝基板30上有多數個外部連接端點304之截面示意圖。在第5A圖中，於形成網印的過程中，可以選擇直接曝露出外部連接端點304(即網印材料不會覆蓋外部連接端點304)，或是先將外部連接端點304以網印材料所形成封裝體50覆蓋後，再以半導體製程將外部連接端點304再曝露出來，對此，本創作並不加以限制；此外，在本創作中，也不對網印製程所使用的材料加以限制。
接著，請繼續參考第5B圖。在完成前述的網印製程、並將多數個外部連接端點304曝露出來之後，再利用電鍍(electroplating)製程，於封裝基板30之多數個外部連接端點304上形成導電元件60，其形成的高度至少大於或等於封裝基板30加上封裝體50的總高度，此外，也可以選擇使用凸塊(bump)製程，使得導電元件60為凸塊(bump)。因此即完成封裝步驟。在此要說明的是，由於第5B圖是第3圖之Y2-Y2方向截面示意圖，因此封裝材料50係配置在封裝基板30上的每一個外部連接端點304之間，且在每一個外部連接端點304上配置有導電元件60。第5C圖係表示完成電鍍製程之後之封裝基板之背面之示意圖。在第5C圖中可以看出多數個外部連接端點304是配置於封裝結構70的側邊上，其截面示意圖則如第5B圖所示。
很明顯地，經由本創作所揭露出的封裝結構70，其一面是曝露出多數個外部連接端點304(未在圖中表示)，作為對外連接之端點，而相對於外部連接端點304的另一面則是晶粒101的背面(未在圖中表示)，故本創作之封裝結構可以達到良好的散熱效果，而此一散熱效果對於大型晶片是非常重要的。
要說明的是，在前述第1圖至第5C圖的說明過程中，雖以單一一片封裝基板30與單一一顆封裝晶粒101來做說明，而實際的應用上， 在本實施例中係可以將已設計良好(well-design)、且配置多數個封裝基板30之電路基板(未在圖中表示)配置在整個晶圓10上，因此在前述的步驟流程中，在第5C圖中利用電鍍製程將多數個導電元件60形成在封裝基板30之多數個外部連接端點304之後即完成了整個封裝結構。最後再利用切割刀(未在圖中表示)進行切割步驟，係將封裝結構切割以形成多數顆晶粒封裝結構70，且特別是指儲存型快閃記憶體晶粒封裝結構。
此外，於本創作中還揭露另一實施例，其製程步驟與前述第1圖至第5C圖相似，故在此不加以多做陳述，然而與前一實施例的差異在於，在本創作的實施例中係將第1圖中配置有多數個晶粒101的晶圓10先進行切割，以得到多數個晶粒101。同時也將配置有多數個封裝基板30之電路基板進行切割，以得到多數個封裝基板30，然後再將封裝基板30配置在晶粒101上，且使封裝基板30與晶粒101結合，因此可以得到如第6圖所示之俯視圖。在此要說明的是，於晶粒101上之元件、封裝基板30上之線路配置以及晶粒101與封裝基板30結合後之步驟流程係與前述第1圖至第5C圖相似，在此不再加以陳述。若在第6圖中係以X-X方向剖面，其可以得到如第7A圖所示之在完成打線製程之後，具有多數個外部連接端點304之封裝基板30設置在晶粒101上，其中多數個外部連接端點304的長度係大於晶粒101之側邊的長度，且由於第7A圖係為X-X方向截面示意圖，於此截面方向只能看到封裝基板30及其連接點302，而在第7A圖中虛線的部份則是晶粒101的所在位置，於此X-X截面方向是看不到晶粒101及其焊墊1014。
接著，參考第7B圖。第7B圖係表示利用網印製程以形成封裝材料以包覆封裝基板、晶粒，且將封裝基板之側邊的多數個外部連接端點曝露在外之示意圖。由於第7B圖為第6圖之X-X方向截面示意圖，因此在第7B圖中也只能顯示出已被封膠體50包覆之封裝基板30、晶粒101以及曝露於封裝體50外的多數個外部連接端點304，並無法顯示出晶粒101之多數個焊墊1014及連接封裝基板30及封裝晶粒101之多數條金屬導線40。
接著，請參考第7C圖。第7C圖係表示利用沖壓製程(stamp process)將封裝基板之多數個外部連接端形成具有內引腳及外引腳之導線架之結構。在第7C圖中，為了讓晶粒封裝結構80可與其它元件(未在圖中表示)彼此電性連接，係在封裝體50形成之後，利用沖壓製程(stamp process)，讓每一顆晶粒封裝結構80上之多數個外部連接端點304形成具有內引腳及外引腳之導線架之結構，因此本創作所揭露之晶粒封裝結構70、80可以藉由這些做為外部連接端點304之具有內引腳及外引腳之導線架與其他元件彼此電性連接。
由以上詳細說明，可使熟知本項技藝者明瞭本創作的確可達成前述目的，實已符合專利法之規定，爰提出專利申請。
惟以上所述者，僅為本創作之較佳實施例而已，當不能以此限定本創作實施之範圍；故，凡依本創作申請專利範圍及創作說明書內容所作之簡單的等效變化與修飾，皆應仍屬本創作專利涵蓋之範圍內。
101‧‧‧晶粒
1014‧‧‧焊墊
30‧‧‧封裝基板
33‧‧‧開口
302‧‧‧連接點
304‧‧‧外部連接端點
306‧‧‧第一金屬導線
40‧‧‧第二金屬導線

Claims (10)

  1. 一種晶粒封裝結構，包括：一晶粒，具有一主動面及一背面，於該晶粒之該主動面之一中間區域上具有多數個焊墊；一封裝基板，具有一正面及一背面，且於該封裝基板之一中間區域配置有一開口，且環繞於該開口之側邊配置有多數個連接點，在該封裝基板之四個側邊上配置有多數個外部連接端點，該些連接點與該些外部連接端點經由多數條第一金屬導線電性連接，其中，將該封裝基板之該背面藉由一黏著層與該晶粒固接，使得該晶粒之該中間區域上之該些焊墊於該封裝基板之該開口曝露出來；多數條第二金屬導線，係將該封裝基板之該中間區域之該些連接點電性連接於該晶粒之該中間區域之該些焊墊；一封裝體，包覆該封裝基板、該晶粒及該些第二金屬導線且曝露出在該封裝基板上之該些外部連接端點；以及多數個導電元件，與該些外部連接端點電性連接成一體並配置在該封裝結構的四個側邊上。
  2. 如申請專利範圍第1項所述之晶粒封裝結構，其中該封裝基板為一印刷電路板。
  3. 如申請專利範圍第1項所述之晶粒封裝結構，其中該封裝基板為一可撓性電路板。
  4. 如申請專利範圍第1項或第2項所述之晶粒封裝結構，其中該封裝基板之一尺寸小於該晶粒之一尺寸。
  5. 如申請專利範圍第1項所述之晶粒封裝結構，其中該些導電元件之高度係至少與該封裝基板與該封裝體之一總高度相同。
  6. 一種晶粒封裝結構，包括一晶粒，具有一主動面及一背面，於該晶粒之該主動面之一中間區域上具有多數個焊墊；一封裝基板，具有一正面及一背面，且於該封裝基板之一中間區域配置有一開口，且環繞該開口之側邊配置有多數個連接點，在該封裝基板之四個側邊上配置有多數個外部連接端點，該些連接點與該些外部連接端 點經由多數條第一金屬導線電性連接，其中，將該封裝基板之該背面藉由一黏著層與該晶粒固接，使得該晶粒之該中間區域上之該些焊墊於該封裝基板之該開口曝露出來；多數條第二金屬導線，係將該封裝基板之該中間區域上之該些連接點電性連接於該晶粒之該中間區域之該些焊墊；以及一封裝體，包覆該封裝基板、該晶粒之該主動面及該些第二金屬導線且將該些外部連接端點曝露在該封裝體之一外側。
  7. 如申請專利範圍第6項所述之晶粒封裝結構，其中該封裝基板為一印刷電路板。
  8. 如申請專利範圍第6項所述之晶粒封裝結構，其中該封裝基板為一可撓性電路板。
  9. 如申請專利範圍第7項或第8項所述之晶粒封裝結構，其中該封裝基板之一尺寸小於該晶粒之一尺寸。
  10. 如申請專利範圍第6項所述之晶粒封裝結構，其中該些外部連接端點為具有內引腳及外引腳之一導線架。
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