TWM315337U - Peak voltage detector having NMOS current source and one-sided transistor load - Google Patents

Description

M315337 VIII. New Description: [New Technology Field] This creation is related to a kind of differential amplifier with a NMOS current source and a single-sided load voltage peak detector, a charging transistor and a capacitor. Complementary MOS(s) electronic circuits with low power consumption. Voltage [Prior Art] Voltage peak detection is a kind of electronic circuit that can measure the maximum value of the _ voltage waveform, and the output of the circuit is the artificial-variable voltage signal, and the output is the maximum of the input voltage waveform. ^. In many applications, the peak value of the input voltage signal must be measured and then retained in DC mode for subsequent analysis and use. - The peak value of a burst is more useful. For example, when performing a destructive test, it is necessary to trace and maintain the peak signal, and measure the rhythm of the voltage signal on the transmission medium, analog recording The ||(趟__), the maximum approximate decoding system (maximum Hkelih00d deeoding system), and the pulse signal detecting circuit for detecting nuclear radiation also require a voltage peak detector. In the prior art, the simplest method of the voltage peak detector is to pass the input voltage signal through the diode and charge the capacitor to obtain the peak value of the input voltage waveform. As shown in the first figure, when the input voltage V(IN) is greater than the voltage of the capacitor C, the diode D is turned on, • charging is performed until the input voltage VON) reaches its maximum value, and the capacitor C cannot continue charging. The output voltage V(OUT) represents the peak value of the input voltage V(IN). Due to the presence of diode D between the output and the input, this circuit cannot accurately detect the true peak value of the input voltage V(IN). In other words, there is always an error in the diode turn-on voltage Vd between the output voltage ν(〇υτ) and the peak value of the input voltage V(IN). That is, MAX(V(OUT))=MAX(V(IN))-Vd, as shown in the second figure (this figure is the transient analysis simulation result of OrCADPSpice). For many applications, the above-mentioned diode turn-on voltage V (j error is undesired, and the voltage difference may vary due to the use of different diodes, which may cause adverse effects or unpredictable In order to be able to accurately detect the peak voltage of the input, another common prior art technique uses two operational amplifiers OP1 and OP2, two diodes D1 and D2, two resistors R1 and R2, and a M315337. The capacitor IIC is used to form the _ voltage peak detector, as shown in the third figure, and the 暂1€必烈咖的熊熊= simulation result, as shown in the fourth figure. Among them, 〇ρι is _ a precise half Wave rectifier, when the input two: iV (IN) is greater than the capacitor voltage v (c), the diode m will transmit a bias voltage to charge the capacitor ci = the capacitor voltage v (c) will be the peak voltage of the input power mv_ Quite close, the detected output ΙίΠυΤ) will also be close to the peak of the power generation (4), which is not shown in the second figure; there is a diode turn-on voltage Vd between the other end and the input. The error. When the input voltage is two (^0:J, at the capacitor voltage, the diode m will be turned on, the diode D1 will be turned off and the β-cutter C will not be charged, which causes the detected The output voltage V((五)丁) will be equal to the peak voltage of 〇. Although the voltage peak detector of the third figure can accurately detect the peak voltage, the eight-electricity has a complicated structure and a large wafer area, which is not conducive to The requirements of the integrated circuit. The technique of the No. k voltage peak detector is proposed, for example, in the U.S. Patent No. ΓΓΓΓΙ^ΤΓ46'5546027'5969545^6051998'6064238^6472861 ^ 二i绿绿号#476418 In the case of the revealer, these technologies can accurately predict the peak voltage of the three fields, but since the voltage peak detectors make (four) more than one operation, there is a complicated wafer area on the side. In addition, the electric ridge peak detector does not consider how to save power consumption. Out, (9) to the precision voltage peak detection technology of the operational amplifier W is raised% 52359? ^ Announcement No. 517161 (the main representative figure is as shown in the fifth figure The disclosures of 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Due to the combination of::, the road structure is simple, the occupied wafer area is small, and the device is beneficial to the second. These techniques do not take into account how to reduce the power consumption. Therefore, there is still room for improvement in this work. The main purpose is to propose a novel architecture of the turbulent source and voltage "detector" which can not only accurately and quickly detect the peak power of the input signal and can have lower power than the peak detector. Consumption. M315337 [New content] β This creation proposes a di-saki axis structure with a 〇8 electric lining material edge-like voltage peak detection, which is a differential amplifier (1), a charging transistor (2) and a The capacitor (8) is composed of, and the 'differential amplifier (1) is used as a comparator, and the charging transistor (2) is used as a charger to supply a charging current required for the capacitor (c), and difference The two input terminals of the amplifier (1) are divided into the input of the electric age-age electric age value detector (4) to earn the signal, and provide the appropriate charging current to the charging transistor to obtain the peak value of the input voltage waveform as the output. a voltage signal, the differential amplifier (1) is composed of a first PM〇s transistor (Mpl), a first _8 transistor (_〇, a second NMOS transistor (_2), and an nmos current source (IP) a composition, wherein the first NMOS transistor MN1 and the second NMOS transistor 2 are used as a driver, and the first PMOS transistor MP1 is used as a single-sided load transistor, and the The single-sided load transistor and the charging transistor (2) together form a current mirror, and the Radisson 8 current source (Ip) is used as a current source and is designed in the form of a diode to provide a current to the differential amplifier. (1) Use. The voltage peak detector proposed by the present invention not only accurately detects the peak voltage of the input signal, but also has the advantages of simple circuit structure, small number of transistors used, and miniaturization of the device. It can effectively reduce power consumption. [Embodiment] φ According to the above purpose, the present invention proposes a voltage peak detector with an NMOS current source and a single-sided load, as shown in the sixth figure, which is composed of a differential amplifier 1 and a charging transistor 2 And a capacitor C. The differential amplifier 1 is composed of a first PM 〇s transistor, an NMOS transistor 丨, a second NMOS transistor MN2, and an NMOS current source IP, wherein the first NMOS transistor MN1 and the first The two NMOS transistor MN2 is used as a driver. The first PMOS transistor MP1 is used as a single-sided load transistor, and the single-sided load transistor and the charging transistor 2 form a current mirror. The NMOS current source IP is composed of an NMOS transistor MN and is designed in the form of a diode and used as a current source to provide a current for the differential amplifier. The gates of the first NMOS transistor MN 1 and the second NMOS transistor MN2 respectively receive the input signal V(IN) and the output voltage feedback signal V(OUT) of the detector, and the source (source) Connected together and connected to the source of the NMOS current source IP, and the drain is connected to the drain of the first PMOS transistor M315337 and the supply voltage Vdd; the NMOS current source IP is a 〇8 transistor MN, the gate and the drain are connected together to form a diode, and connected to the source of the first _8 transistor MN1 and the second 〇8 transistor a source of MN2, and a source connected to the ground; a source of the first PMOS transistor MP1 is connected to a power supply voltage Vdd, and a gate is connected to the drain to form a diode, and is connected to the The drain of the first NMOS transistor MN1. Referring to FIG. 6 again, the charging transistor 2 is composed of a second PMOS transistor MP2. The source of the first PMOS transistor MP2 is connected to a power supply voltage vdd, and the gate and the first pmS transistor are connected. The gate of MP1 is connected to the pole of the first NM transistor MN1, and the pole is connected to the capacitor c and the gate of the NM〇S transistor MN2. The first PM〇s transistor Mp丨 and the second PMOS transistor MP2 form a current mirror configuration.

For the sake of explanation, the following derivation process describes the gold oxide semi-transistor as the simplest model in 〇rCAD Pspice (ie, the levell model), regardless of the channel length modulation effect. However, in the subsequent simulation verification, all the crystal parameters in the 〇rCA〇pspice (including the channel length modulation effect, of course) are considered. It is known from the circuit shown in FIG. 6 that when the input voltage signal V(IN) is greater than the output voltage signal v(〇UT), the no-pole current id (]V[Nl) of the first NMOS transistor MN1 is greater than the second. Stealing the drain of the jqs transistor Id (_2) 'where the current flowing into the transistor takes a positive sign, and the current flowing out of the transistor takes a negative sign, that is, the current Id (MN1) represents the current flowing into the first nm〇s The radon current of the crystal plane 丨, and _w (MP1) represents the drain current flowing out of the first PMOS transistor ^1, and

Id (MN1) + Id (MN2) = IP (1) where IP is the current supplied by the NMOS current source,

Id (MN1) = -Id (MP1) (2) Since the first PMOS transistor MP1 and the PMOS transistor teardown 2 constitute a current mirror, -Id (MP1) /(W/L)mpi= -Id (MP2) /(W/L)MP2 (3) where '(W/L) mp^(W/L)mp2 represents the effective channel width of the first pmos transistor MPi and the second pM〇S transistor MP2, respectively Therefore, the capacitor c can be charged. When the charging action reaches V(OUT) equal to the peak voltage of the input voltage signal V(IN), the current Id (MN1) /(W/L)^^ Id (MN2) /(W/L)mn2 (4) where '(^ ¥/1^)_ and (\\^) reading 2 respectively indicate the effective channel width-to-length ratio of the first nm〇s transistor and the second side (10) transistor_2, and the capacitor c is still charged at this time. action. M315337 However, according to the transfer characteristic curve of the differential amplifier, it is known that the output voltage signal ν(〇υτ) must be compared with the input peak voltage vpeak!^ over an excess voltage (〇verShoot v〇ltage abbreviated as v〇s) to be the first _ 〇 § The transistor MN1 is forced to the off state. When the first surface 〇8 transistor is turned off, the charging transistor stops charging the capacitor c. At this time, the output voltage signal ν(ουτ) is V (OUT). )=vpeak+Vos (3) Since the second: ^]\408 transistor MN2 operates in the saturation region, and the first nm〇S transistor MN1 enters the cut-off region from the saturation region, the following current equation can be used. Out VGS2&VGS1:

Id (MN2) = IP (6)

Id (MN1) - 〇 (7) Therefore, the excess voltage Vos is equal to

After Vos = VGS2-VGS1 (8), when the input voltage signal V (IN) falls down from the peak voltage vpeak, since the first nm 〇s transistor MN1 has entered the off state, the current -Id (MP1) = .ld ( MP2) =0 (9) Therefore, the charging transistor will no longer charge the capacitor c, so the output voltage signal ν(ουτ) will remain fixed at the voltage of equation (5). It is known from equation (5) that the output voltage signal ν(ουτ) is always higher than the input peak voltage Vpeak by an over-voltage Vos'. The excess voltage v〇s is shown in equation (8), if all the transistors Both have the same zero-bias threshold voltage and a permutation parameter KP (Tmnsconductance parameter), and the zero-bias threshold voltage %〇 and the mutual conductance parameter lamp are both gold-oxygen semi-transistors. One of the model parameters, equation (8) can be rewritten as

Vos = [2 · IP · 1/KP · 1/(W/L)_]1/2 n〇^ where '(W/L)mn2 represents the effective channel width-to-length ratio of the second NMOS transistor MN2, related to The derivation of the voltage Vos can be found in pages 357 to 375 of the book "Designofanalogintegrated circuits and systems" published by McGrath-Hill in conjunction with Kenneth R. Laker and Willy MC Sansen. It can be known from equation (10) that the current voltage ιρ provided by the NM〇S current source and the second NMOS transistor MN2 (W/L-2 can control the excess voltage Vos to a minimum value, The voltage peak detector with NMOS current source and unilateral load can accurately detect the peak value of the input signal M315337. The voltage is difficult to create NM〇S source and unilateral PSpice transient analysis simulation results, such as As shown in the seventh figure, the voltage peak detector of the current source and the unilateral load can accurately detect the output from the simulation result: Next, how to reduce the power consumption in this creation, first compare the fifth The figure shows the voltage peak detector of the Chinese Patent No. 5, 161 patent and the preferred embodiment of the present invention shown in the sixth figure: since in the fifth prior art, the current is supplied The gate of the NMOS transistor ΜΝ3 is connected to the power supply voltage. Therefore, the third 譲 ^ ^ 以 以 以 以 以 以 以 以 以 以 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本Current source IP is determined by a 〇s transistor

ΞΪ^Τ^Γ08 t^MN ϋ: 'This creation is used as the surface os current source IP. The sigma s electric gate ίίϊί GS (IP) absolute value is less than the third _ crystal shown in the fifth figure The 'results' of the face 3 have a lower consumption than the previous skill of the fifth rider. Reduced, for the Republic of China Announcement No. 517161 full-time voltage peak detector (the previous creation voltage peak detector 0rCADPSpiee transient, analysis simulation results, the analog junction ^ Zheng' extract of the voltage miscellaneous detector The prior art has lower current consumption. The voltage peak detector of mil can be connected in parallel with a switch at both ends of the capacitor C, which is used to discharge the charge stored on the capacitor. Conducive to the peak detection of the next input voltage signal. [Creation function] This lion's lion 〇 电 电 电 电 电 及 及 及 及 及 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值 峰值Since the voltage peak detector proposed in this creation uses only two PMOS transistors, three NMOS transistors, and one capacitor, not only the number of transistors used in the circuit frame 1 but also the number of transistors is small, and There is no need to use an operational amplifier, because it has a high degree of integration and is advantageous for miniaturization of the device; M315337 (2) Accuracy: The voltage peak detector proposed in this work is verified by simulation results. It can accurately detect the peak voltage of the input signal, so it also has the advantage of high precision; (3) Low power consumption: The voltage peak detector proposed by the author proves that the differential amplifier can effectively reduce the differential amplifier. The current consumption is therefore effective in reducing the power consumption of the voltage peak detector. Person, _ «M315337 of the present technology [Simple description of the diagram] The first figure shows the circuit diagram of the voltage peak detector in the first prior art. The second figure shows the transient analysis timing diagram of the wheel voltage signal of the voltage peak detector, such as the voltage signal, and the third diagram shows the circuit diagram of the voltage peak detector of the second prior art. The figure shows the input and cost analysis of the peak yarn H of the third figure; the fifth picture shows the circuit diagram of the special voltage peak yarn S of the number 517(6) of Zhonghuamin@公告案号; The circuit diagram of the voltage peak detector of the embodiment. The seventh diagram shows the transient analysis timing diagram of the input voltage signal and the output voltage signal of the preferred embodiment of the present invention; Transient current analysis timing diagram of voltage peak detector and voltage peak detector of the Republic of China Announcement No. 51716H. [Main component symbol description] 1 Differential amplifier D diode 2 Charging transistor D1 II Polar body

D2 Diode Id (MN3) NMOS transistor MN3 drain current operational amplifier second PMOS transistor fourth PMOS transistor second NMOS transistor NMOS transistor power supply voltage resistor output voltage signal OP1 operational amplifier OP2 MP1 first PMOS transistor MP2 MP3 third PMOS transistor MP4 MN1 first NMOS transistor MN2 MN3 third NMOS transistor MN IP NMOS current source Vdd R1 resistor R2 V (IN) input voltage signal V (OUT) c capacitor 12

Claims (1)

M315337 IX. Patent application scope: 1·-, voltage peak detector with NMOS electric surface and unilateral load, used to read and measure the input voltage peak value, which includes: 'An input terminal for providing an input voltage signal An output terminal for outputting a peak voltage of the input voltage signal; electricity, a supply voltage, a voltage supply for providing a voltage peak to detect a power supply voltage and a reference grounding; and a differential amplification of a single-sided negative 1 transistor ||(1}, for accepting and comparing the input voltage signal and the voltage signal on the capacitor, and providing a charging current signal to the charging transistor; : charging the transistor (2), using the differential amplifier (1) A current is supplied to the capacitor by the current flowing through the transistor, and a charging current is supplied to the capacitor; and one end of the electric grid (C) '5 galvanic grid is connected to the charging transistor (2) to receive the charging transistor (2) The supplied charging current, and the other end is connected to the reference ground; wherein the differential amplifier (1) with the single-sided load transistor includes: - a single-sided load transistor, which is made of a -PMOS a crystal (Μρι), The source of the first pM〇s transistor (MP1) is connected to the power supply voltage, the gate is connected to the drain, and is connected to the gate of the charging transistor (2); a first NMOS transistor (MN1), The source is connected to the source of the second _8 transistor (_2) and the drain of the NMOS transistor (MN), the gate is used to receive the input voltage signal, and the drain is connected to the charging transistor (2) a gate connected to the first PMOS transistor (Mp丨); a second NMOS transistor (MN2) having a source and a source of the first NMOS transistor (MN1) and an NMOS The drain of the crystal (MN) is connected, the gate is used to receive the voltage signal on the capacitor, and the drain is connected to the power supply voltage; and an NMOS current source (IP) is used, and the NMOS current source (IP) is composed of an NM. The 〇s transistor (MN) is composed of 'the gate and the gate are connected together to form a diode, and is connected to the source of the first NM〇s transistor (MN1) and the second NMOS transistor (_2) the source, and the source is connected to the ground. 2. The voltage peak detector with NMOS current source and unilateral load as described in the first paragraph of the patent application, The charging transistor (2) is composed of a second PMOS transistor (MP2), the source of the second PMOS transistor (MP2) is connected to a power supply voltage, and the gate is connected to the first PMOS transistor (MP1). The gate 13 M315337 is connected to the drain of the first NMOS transistor (ΜΝ1), and the drain is connected to the gate of the capacitor 山山 and the second NMOS transistor (ΜΝ2). The voltage peak detector of the NMOS current source and the unilateral load described in claim 1 further includes: #二,关, the open relationship is connected in parallel with the capacitor to provide a discharge path, In order to discharge the charge stored in the capacitor ^, the peak detection of the next input voltage signal is facilitated. m rewards the third point of the (10) electric and unilateral stalking peak detection », the eight-in-one relationship consists of a gold-oxygen semi-transistor. 4·