CN117040449A - Overcurrent protection and detection circuit suitable for class AB output stage - Google Patents

Overcurrent protection and detection circuit suitable for class AB output stage Download PDF

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Publication number
CN117040449A
CN117040449A CN202310582827.7A CN202310582827A CN117040449A CN 117040449 A CN117040449 A CN 117040449A CN 202310582827 A CN202310582827 A CN 202310582827A CN 117040449 A CN117040449 A CN 117040449A
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current
tube
pmos
nmos
electrode
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徐叶
李珂
张子同
吴叶
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CETC 58 Research Institute
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses an overcurrent protection and detection circuit suitable for class AB output stage, belonging to the field of integrated circuits and comprising a pull-current overcurrent protection module, a current-filling protection module and an overcurrent/short circuit detection module. The pull current overcurrent protection module is connected with the class AB output stage and is used for limiting the pull current of the class AB output stage and protecting the PMOS power tube of the output stage; the current-filling overcurrent protection module is connected with the class AB output stage and is used for limiting the current filling of the class AB output stage and protecting the NMOS power tube of the output stage; the overcurrent/short circuit detection module is connected with the pull current overcurrent protection module and the current filling overcurrent protection module at the same time and is used for generating an overcurrent or short circuit signal; the class AB output stage is used for the last stage of the power amplifier for driving a high current load. The invention can limit the load current in time when the circuit is over-current or short-circuited, thereby avoiding damage to the circuit and ensuring the circuit to be safer and more stable.

Description

Overcurrent protection and detection circuit suitable for class AB output stage
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an overcurrent protection and detection circuit suitable for class AB output stages.
Background
Class AB amplifiers have reduced static power consumption, improved power conversion efficiency, and less distortion than class B amplifiers. Therefore, most power amplifier output stages employ a class AB architecture. The power amplifier using class AB as output stage is commonly used in audio circuits such as earphone driver, and has the characteristic of driving large current.
Generally, the aspect ratio of the output power PMOS tube can reach 10000 times. When the amplifier output is shorted to power or ground, a current greater than 1A is generated. Such large transient currents not only cause damage to the output tube, but can even lead to breakdown of the overall circuitry, and therefore overcurrent detection and protection circuitry is critical.
The technical core of the overcurrent protection and detection circuit is induced current. Currently, there are 3 ways to induce current: 1) A resistor is connected in series on the power tube, and the current is converted into the voltage difference between two ends of the resistor; 2) A sampling MOS tube (reduced in a certain proportion) which is connected with the power tube in parallel is adopted to sense the current; 3) The output current is sensed by the combination of the current sensing resistor and the current sensing MOS tube.
However, the first way not only loses the output swing of the amplifier, but also can cause the current limit value to be influenced by the process and the temperature due to the temperature-related characteristic of the resistor; the second way is that although the output swing is not reduced, the sampling current is proportional to the load current, and the static current is obviously increased under the condition of heavy load current, especially when the ground or power supply is short-circuited; the third mode is a combination of the first mode and the third mode, and an additional parallel MOS tube is adopted to sense current, and a resistor is connected in series on the MOS tube to reduce quiescent current, but the current limit value is still inaccurate. To avoid this, an over-current protection and detection circuit is needed.
Disclosure of Invention
The invention aims to provide an overcurrent protection and detection circuit suitable for an AB class output stage, so as to solve the problems in the background technology.
In order to solve the technical problems, the invention provides an overcurrent protection and detection circuit suitable for an AB class output stage, which comprises a pull-current overcurrent protection module, a current-filling protection module and an overcurrent/short circuit detection module;
the pull current overcurrent protection module is connected with the class AB output stage and is used for limiting the pull current of the class AB output stage and protecting the PMOS power tube of the output stage;
the current-filling overcurrent protection module is connected with the class AB output stage and is used for limiting the current filling of the class AB output stage and protecting an NMOS power tube of the output stage;
the overcurrent/short circuit detection module is connected with the pull current overcurrent protection module and the current filling overcurrent protection module at the same time and is used for generating an overcurrent or short circuit signal;
the class AB output stage is used for the last stage of the power amplifier and is used for driving a high-current load.
In one embodiment, the class AB output stage includes a PMOS tube MPP and an NMOS tube MNP; wherein,
the source electrode of the PMOS tube MPP is connected with a power supply VDD, and the grid electrode and the drain electrode of the PMOS tube MPP are both connected with the pull current overcurrent protection module; the source electrode of the NMOS tube MNP is grounded, and the grid electrode and the drain electrode are both connected with the current-filling overcurrent protection module;
the drain electrode of the PMOS tube MPP is connected with the drain electrode of the NMOS tube MNP to form a VOUT output end of the class AB output stage, and the output end VOUT can be externally connected with a load capacitor and a resistor to drive large current.
In one embodiment, the pull-current overcurrent protection module includes a pull-current overcurrent limiting unit, a pull-current foldback current limiting unit, and a pull-current detecting unit;
the pull current overcurrent limiting unit is connected with the VOUT output end of the AB class output stage and the grid electrode of the PMOS tube MPP at the same time and is used for pull current monitoring and overcurrent limiting;
the pull current foldback current limiting unit is connected with the VOUT output end of the AB class output stage and the internal port of the pull current overcurrent limiting unit at the same time and is used for limiting the current of the VOUT output end short-circuited to the ground;
the pull current detection unit is connected with the internal port of the pull current overcurrent limiting unit and the internal port of the pull current foldback current limiting unit at the same time and is used for reversely amplifying an overcurrent detection signal and a short circuit to ground detection signal;
the pull current and overcurrent detection signal of the pull current and overcurrent protection module is VS1, and the short circuit to ground detection signal is VS2; the signal VS1 is high and overcurrent, and the signal VS2 is high and short-circuited.
In one embodiment, the pull current overcurrent limiting unit comprises NMOS tubes MN1 to MN5, PMOS tubes MP1 to MP5 and a PMOS sampling tube MPR;
the grid electrode of the NMOS tube MN1 is connected with the output end of the VOUT, the source electrode of the NMOS tube MN1 is connected with the source electrode of the PMOS tube MP1, and the grid electrode and the drain electrode of the PMOS tube MP1 are commonly connected with the source electrode of the NMOS tube MN 2;
the drain electrode of the PMOS tube MP2 is simultaneously connected with the drain electrode and the grid electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is connected with the drain electrode of the NMOS tube MN3,
the grid electrode of the PMOS sampling tube MPR is connected with the grid electrode of the PMOS tube MPP, the drain electrode of the PMOS sampling tube MPR is connected with the source electrode of the PMOS tube MP3, the grid electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP2, and the drain electrode of the PMOS tube MP3 is connected with the drain electrode of the NMOS tube MN 4;
the drain electrode of the PMOS tube MP4 is simultaneously connected with the grid electrode of the PMOS tube MP5 and the drain electrode of the NMOS tube MN5, and the grid electrode of the NMOS tube MN5 is simultaneously connected with the grid electrode and the drain electrode of the NMOS tube MN 4; the drain electrode of the PMOS tube MP5 is connected with the grid electrode of the PMOS tube MPP;
the drain electrode of the NMOS tube MN1, the source electrode of the PMOS tube MP2, the source electrode of the PMOS sampling tube MPR, the source electrode of the PMOS tube MP4 and the source electrode of the PMOS tube MP5 are all connected with the power supply VDD; the sources of NMOS transistors MN 3-MN 5 are all grounded.
In one embodiment, the pull-current foldback current limiting unit includes a PMOS transistor MP6, an NMOS transistor MN6, and a resistor R1; the source electrode of the PMOS tube MP6 and the first end of the resistor R1 are both connected with the power supply VDD, the drain electrode of the PMOS tube MP6 is connected with the grid electrode of the PMOS tube MPP, the grid electrode is simultaneously connected with the second end of the resistor R1 and the drain electrode of the NMOS tube MN6, the grid electrode of the NMOS tube MN6 is connected with the drain electrode of the PMOS tube MP3, and the source electrode of the NMOS tube MN6 is connected with the output end of the VOUT.
In one embodiment, the pull current detection unit includes NMOS transistors MN7 and MN8, PMOS transistors MP7 and MP8; the sources of the PMOS tubes MP7 and MP8 are connected with the power supply VDD, and the sources of the NMOS tubes MN7 and MN8 are grounded;
the grid electrode of the PMOS tube MP7 is connected with the drain electrode of the NMOS tube MN5, and the drain electrode is connected with a signal VS1; the grid electrode of the PMOS tube MP8 is connected with the drain electrode of the NMOS tube MN6, and the drain electrode is connected with a signal VS2;
the grid electrode and the drain electrode of the NMOS tube MN7 are both connected with a signal VS1; the gate and drain of NMOS transistor MN8 are both connected to signal VS2.
In one embodiment, the current-sinking protection module includes a current-sinking overcurrent limiting unit, a current-sinking foldback current limiting unit, and a current-sinking detection unit;
the current-filling and overcurrent limiting unit is connected with the VOUT output end of the AB class output stage and the grid electrode of the NMOS tube MNP at the same time and is used for current-filling monitoring and overcurrent limiting;
the current-sinking foldback current limiting unit is connected with the VOUT output end of the AB class output stage and the internal port of the current-sinking overcurrent limiting unit at the same time and is used for limiting the current of the VOUT output end short-circuited to a power supply;
the current-filling detection unit is connected with the internal port of the current-filling overcurrent limiting unit and the internal port of the current-filling foldback current limiting unit at the same time and is used for reversely amplifying the overcurrent detection and short-circuiting to a power supply detection signal;
the current-filling and current-flowing detection signal of the current-filling and current-flowing protection module is VS3, and the short circuit to power supply detection signal is VS4; the signal VS3 is short-circuited at a low level, and the signal VS4 is short-circuited at a low level.
In one embodiment, the current-filling and overcurrent limiting unit comprises NMOS tubes MN 9-MN 13, PMOS tubes MP 9-MP 13 and NMOS sampling tubes MNR;
the drain electrode of the PMOS tube MP10 is simultaneously connected with the source electrode of the PMOS tube MP11, the drain electrode of the NMOS tube MN9 and the grid electrode of the PMOS tube MP11, and the grid electrode and the drain electrode of the NMOS tube MN 10; the source electrode of the NMOS tube MN9 is connected with the source electrode of the PMOS tube MP9, and the grid electrode of the PMOS tube MP9 is connected with the OUT output end;
the grid electrode of the PMOS tube MP13 is simultaneously connected with the grid electrode and the drain electrode of the PMOS tube MP12, the drain electrode of the PMOS tube MP13 is simultaneously connected with the grid electrode of the NMOS tube MN13 and the drain electrode of the NMOS tube MN12, and the drain electrode of the NMOS tube MN13 is connected with the grid electrode of the NMOS tube MNP;
the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN11, the grid electrode of the NMOS tube MN11 is connected with the drain electrode of the NMOS tube MN10, and the source electrode of the NMOS tube MN11 is connected with the drain electrode of the NMOS sampling tube MNR; the grid electrode of the NMOS sampling tube MNR is connected with the grid electrode of the NMOS tube MNP;
the drain electrode of the PMOS tube MP9, the source electrode of the PMOS tube MP10, the source electrode of the NMOS sampling tube MNR, the source electrode of the NMOS tube MN12 and the source electrode of the NMOS tube MN13 are all grounded; the source electrode of the PMOS tube MP10, the source electrode of the PMOS tube MP12 and the source electrode of the PMOS tube MP13 are all connected with the power supply VDD.
In one embodiment, the current-sinking foldback current limiting unit includes a PMOS transistor MP14, an NMOS transistor MN14, and a resistor R2; the source electrode of the PMOS tube MP14 is connected with the OUT output end, the grid electrode is connected with the drain electrode of the NMOS tube MN11, the drain electrode is simultaneously connected with the first end of the resistor R2 and the grid electrode of the NMOS tube MN14, the second end of the resistor R2 is grounded, the drain electrode of the NMOS tube MN14 is connected with the grid electrode of the NMOS tube MNP, and the source electrode is grounded.
In one embodiment, the current-sinking detection unit includes PMOS transistors MP15 and MP16, and NMOS transistors MN15 and MN16; the sources of the PMOS tubes MP15 and MP16 are connected with the power supply VDD, and the sources of the NMOS tubes MN15 and MN16 are grounded;
the grid electrode and the drain electrode of the PMOS tube MP15 are both connected with a signal VS3, and the grid electrode and the drain electrode of the PMOS tube MP16 are both connected with a signal VS4;
the drain electrode of the NMOS tube MN15 is connected with the signal VS3, and the grid electrode is connected with the drain electrode of the PMOS tube MP 13; the drain of the NMOS transistor MN16 is connected with the signal VS4, and the gate is connected with the drain of the PMOS transistor MP 14.
In one embodiment, the over-current/short detection module includes two buffers, two inverters, and three or gates; wherein,
the inputs of the two buffers are the signals VS1 and VS2 of the pull-up current overcurrent protection module respectively, and the outputs of the two buffers are the inputs of an OR gate; the input of the two inverters is signals VS3 and VS4 of the current-filling current protection module respectively, and the output of the two inverters is the input of the other OR gate; the output of the two OR gates is the input of the third OR gate, and the relation between the output end signal VFLAG of the third OR gate and the input is as followsNamely VS1 is high or VS2 is high or VS3 is highWhen the low level or VS4 is low level, the VFLAG signal is high level, which indicates that the pull current or the sink current in the circuit flows or the circuit is short-circuited to the power supply or the ground; the user turns off the circuit by detecting the VFLAG signal.
The overcurrent protection and detection circuit suitable for the class AB output stage can limit load current in time when overcurrent or short circuit occurs in the circuit, avoid damage to the circuit and enable the circuit to be safer and more stable. Compared with the prior art, the invention has the following beneficial effects:
(1) The transient power consumption is smaller, and an MOS tube is connected in series with the drain end of the traditional MOS sampling tube parallel to the power tube, so that the excessive current is avoided when the sampling MOS tube is in transient conduction;
(2) The sampling current is more accurate, so that the drain end of the sampling MOS tube is as close to the output end of the amplifier as possible, and the channel modulation effect is further reduced;
(3) The short circuit power consumption is smaller, and a foldback current limiting circuit is added in the circuit; when the circuit is shorted to power or ground, the circuit may further limit the load current;
(4) The short-circuit limit current value is smaller than the overcurrent limit current value, which also means lower power consumption.
Drawings
Fig. 1 is a schematic block diagram of an overcurrent protection and detection circuit suitable for an AB class output stage according to the present invention.
Fig. 2 is a schematic diagram of a pull-up current over-current protection module.
FIG. 3 shows a pull-up current over-current protection module V N3 、V N2 Schematic diagram of voltage variation curve with VOUT.
Fig. 4 is a schematic diagram of a current flow protection module.
Fig. 5 is a schematic diagram of an overcurrent/short circuit detection module.
Fig. 6 is a schematic diagram of a class AB amplifier simulation setup with over-current protection and detection circuitry.
Fig. 7 is a schematic diagram of a transient simulation result of the load-connected 8Ω resistor in a simulation setting.
Fig. 8 is a schematic diagram of an overcurrent transient simulation result of the 4 Ω resistor connected to the load in the simulation setting.
Fig. 9 is a schematic diagram of a transient simulation result of VOUT to ground.
Fig. 10 is a schematic diagram of a transient simulation result of VOUT versus power supply short.
Detailed Description
The invention provides an overcurrent protection and detection circuit suitable for class AB output stage, which is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides an overcurrent protection and detection circuit which is applicable to class AB output stages, and a schematic block diagram of the overcurrent protection and detection circuit is shown in figure 1.
The AB class output stage is the last stage of the power amplifier and is used for driving large load current; the first stage, the second stage (if any) of the power amplifier may be implemented using prior art techniques. As shown in fig. 1, the class AB output stage includes a PMOS tube MPP and an NMOS tube MNP; the gate port of the PMOS tube MPP is VP1, and the gate port of the NMOS tube MNP is VN1. The drain electrode of the PMOS tube MPP is connected with the drain electrode of the NMOS tube MNP, and the drain electrodes of the PMOS tube MPP and the NMOS tube MNP are ports VOUT and externally connected with a load. In this embodiment, the aspect ratio of the PMOS tube MPP is 11294 and the aspect ratio of the nmos tube MNP is 3753.
When the circuit generates pull current or the port VOUT is short-circuited to the ground, the PMOS tube MPP is a main power tube and bears large current. Therefore, the pull-current overcurrent protection module mainly samples the current of the PMOS tube MPP, and generates an overcurrent detection signal VS1 (the high level is overcurrent) and a short-circuit-to-ground detection signal VS2 (the high level is short-circuit).
When the circuit is in current filling or the port VOUT is short-circuited to a power supply, the NMOS tube MNP is a main power tube and bears large current. Therefore, the current-sinking and current-sinking protection module mainly samples the current of the NMOS transistor MNP, and generates the over-current detection signal VS3 (low level is over-current) and the short-circuit to the power detection signal VS4 (low level is short-circuit).
The signals VS1, VS2, VS3, VS4 are used as inputs to the overcurrent/short circuit detection module, and a series of combinational logic is performed to output the final overcurrent/short circuit signal VFLAG.
Fig. 2 is a schematic structural diagram of a pull-current overcurrent protection module and an AB class output stage, where the pull-current overcurrent protection module mainly includes a pull-current overcurrent limiting unit, a pull-current foldback current limiting unit, and a pull-current detecting unit. Wherein the pull current overcurrent limiting unit comprises a PMOS sampling tube MPR which copies the MPP and the W/L of the PMOS tube in the AB class output stage in proportion MPP :(W/L) MPR =144:1, where (W/L) MPP Is the width-to-length ratio of the MPP of the PMOS tube and W/L MPR Is the aspect ratio of the MPR of the PMOS sampling tube. The grid of the PMOS sampling tube MPR is connected with the grid of the PMOS tube MPP, and the drain electrode of the PMOS sampling tube MPR is connected with the source electrode of the PMOS tube MP 3.
The NMOS transistors MN1, MN2 and MN3, and the PMOS transistors MP1, MP2 and MP3 form a pull current VOUT voltage follower circuit, see a dotted line box in FIG. 2. In order to reduce the channel length modulation effect, the copy current of the PMOS sampling tube MPR is more accurate, and the drain voltage V of the PMOS sampling tube MPR N3 The port VOUT voltage should be as close as possible. Therefore, the design of the PMOS MP3 is particularly critical in this embodiment. Drain voltage of PMOS sampling tube MPRWherein V is N1 Is the drain voltage of the PMOS tube MP2, +.>The source gate voltage of the PMOS tube MP3 is shown. The width-to-length ratio of the MP3 of the PMOS tube is designed to be larger, so thatThus->Wherein->The threshold voltage of the PMOS transistor MP3 is shown. In this embodiment, the static current of the saturation region of the PMOS MP2 is 5uA, and the static current of the saturation region of the nmos MN3 is 10uA. The gate of NMOS tube MN1 is connected with port VOUT, when the voltage of port VOUT is extremely small, NMOS tube MN1 is turned off, no current flows, NMOS tube MN3 enters a linear region, V N1 Reaching a minimum value->Wherein->The source gate voltage of NMOS transistor MN2 is shown. When (when)Wherein->Represents the threshold voltage of NMOS transistor MN1, +.>The source gate voltage of the PMOS transistor MP1 is indicated, the NMOS transistor MN1 starts to be turned on gradually, and the larger the VOUT voltage is, the larger the conduction current of the NMOS transistor MN1 is. The NMOS transistor MN3 gradually changes from the linear region to the saturation region, the quiescent current thereof is also continuously increased, and the source voltage V of the NMOS transistor MN2 N2 The potential is continuously increased, and the potential is increased> The potential also rises continuously. Thus, when-> When (when)V N1 ∝VOUT， In this embodiment design +.>Then V N3 ≈VOUT。V N3 、V N2 The voltage variation curve with VOUT is shown in fig. 3. As can be seen from FIG. 3, when VOUT voltage>1.6V，V N3 Close to VOUT. In summary, the pull-up current VOUT voltage follower circuit has the following 2 advantages: 1) When the amplifier suddenly short-circuits to the ground, the on-current of the MPR channel of the PMOS sampling tube is limited, and the transient power consumption is reduced. When the voltage is short-circuited to the ground, the voltage (i.e. VP 1) of the grid port of the PMOS tube MPP may be suddenly changed to 0, the PMOS sampling tube MPR is directly conducted, the channel current is limited after the PMOS tube MP3 is increased, and the power consumption is further reduced; 2) At-> V at the time of N3 And the voltage is approximately equal to VOUT, the channel length modulation effect is reduced, and the MPR copy current of the PMOS sampling tube is more accurate.
The pull current over-current limiting current is determined by the PMOS MP4, and its gate is connected to a current source circuit, which is not shown in this embodiment, and can be designed by a person skilled in the art according to the prior art. In this embodiment, the static current of the PMOS transistor MP4 in the saturation region is 50 μa. NMOS transistor MN4 and NMOS transistor MN5 form a group of current mirrors, and the ratio W/L of the width to length ratio of the two current mirrors is equal to the ratio W/L of the width to length of the two current mirrors MN4 :(W/L) MN5 =20:1. Therefore, the limiting current of the MPR of the PMOS sampling tube is 1mA, and the overcurrent limiting current of the MPP of the PMOS tube is 144mA (theoretical value). When the pull current is smaller, the MPR current of the sampling PMOS sampling tube is smaller than 1mA, and the MN5 copy current of the NMOS tube<50 mu A, the PMOS tube MP4 is in a linear region, and the drain electrode of the PMOS tube MP4 is electrically connectedPressure V N5 The PMOS tube MP5 is closed near the power supply voltage, and has no influence on the circuit. V (V) N5 The voltage VS1 is reversely output to the low level through the common source stage MP 7. When the pull current is larger, the MPR current of the sampling PMOS tube is close to or exceeds 1mA, the current of the NMOS tube MN5 copy is close to 50uA, the MP4 of the PMOS tube is changed from a linear region to a saturation region, V N5 The voltage is gradually reduced, the PMOS tube MP5 is gradually conducted, the voltage of VP1 is forced to rise, and the pull current is limited. V (V) N5 The reverse output VS1 is high through the common source stage MP7, meaning that the over-current protection is on.
When the port VOUT is directly shorted to ground, the circuit is not in operation, and the pull current should be limited to be lower (much lower than the overcurrent limiting current 144 mA) to reduce the power consumption. Therefore, a pull current foldback current limiting unit is added in the pull current overcurrent protection module, and the pull current short-circuited to ground is further limited. The pull-current foldback current limiting unit comprises a PMOS tube MP6, an NMOS tube MN6 and a resistor R1. When the short circuit to ground occurs, the current-pulling and overcurrent limiting unit is started, and the PMOS sampling tube MPR copies large current, so that the drain voltage V of the PMOS tube MP3 is caused N4 The voltage is raised. At the same time VOUT voltage is 0, so thatWherein->Represents the gate-source voltage, < +.>The threshold voltage of the NMOS transistor MP 6; NMOS tube MN6 is conducted, the voltage difference of resistor R1 is increased, and the grid voltage V of PMOS tube MP6 N6 The voltage drop causes the PMOS tube MP6 to be conducted, so that the grid electrode of the PMOS tube MPP is forced to rise back, and the pull current is limited. At this time, the MPR copy current of the PMOS sampling tube in the pull-up current-overcurrent limiting unit is reduced, and the short-circuit limiting current of the pull-up current-overcurrent protection module of the present embodiment becomes 18mA, which is far lower than the overcurrent limiting current 144mA (theoretical value). This means that a lower short-circuit current limit will further reduce the power consumption. Likewise, V N6 By common source stage MPThe 8 reverse output VS2 is high, meaning that the short-circuit protection is on.
Fig. 4 is a schematic structural diagram of a current-sinking and current-flowing protection module and an AB class output stage, where the current-sinking and current-flowing protection module mainly includes a current-sinking and current-flowing limiting unit, a current-sinking and current-returning limiting unit, and a current-sinking detection unit. Wherein the current-sinking through-current limiting unit comprises an NMOS sampling tube MNR. NMOS sampling tube MNR copies NMOS tube MNP (W/L) in class AB output stage in proportion MNP :(W/L) MNP ＝144:1，(W/L) MNP Is the width-to-length ratio (W/L) of NMOS tube MNP MNP Is the aspect ratio of the NMOS sampling tube MNR. The gate of the NMOS sampling tube MNR is connected with the gate of the NMOS tube MNP, and the drain of the NMOS sampling tube MNR is connected with the source of the NMOS tube MN 11.
The PMOS transistors MP9, MP10, MP11, and the NMOS transistors MN9, MN10, MN11 constitute a current VOUT voltage follower circuit, see the dashed box in fig. 4. The principle of the current-sinking VOUT voltage follower is similar to that of the current-sinking circuit, and will not be described in detail. When (when) Source voltage of NMOS transistor MN11When-> Designed in the present embodimentThen V N7 And VOUT. Wherein (1)>Respectively representing threshold voltages of the PMOS tube MP9 and the NMOS tube MN11, < >>Represents the gate-source voltage, < +.>The source gate voltage of the PMOS transistor MP11 is shown.
The current sink over-current limiting current is determined by the NMOS transistor MN12, the gate of which is connected to a current source circuit, which is not shown in this embodiment, and can be designed by a person skilled in the art according to the prior art. In this embodiment, the quiescent current of the NMOS transistor MN12 in the saturation region is 60 μa. The PMOS tube MP13 and the PMOS tube MP12 form a group of current mirrors, and the ratio (W/L) of the width to length ratio of the two MP12 :(W/L) MP13 =20:1. Therefore, the limiting current of the NMOS sampling tube MNR is 1.2mA, and the overcurrent limiting current of the NMOS tube MNP is 173mA (theoretical value). The principle is similar to the principle of limiting the pull current and is not repeated. The VS3 low level indicates that the current sinking overcurrent protection is on.
Similarly, the current-sinking protection module comprises a current-sinking foldback current limiting unit for further limiting the pull current short-circuited to the power supply. The current-sinking foldback current limiting unit comprises a PMOS tube MP14, an NMOS tube MN14 and a resistor R2. The principle is similar to the principle of the pull-current foldback current limitation, and a description thereof will be omitted. The short-circuit limiting current of the current-carrying current protection module of this embodiment becomes 39mA, which is far lower than 173mA (theoretical value) of the current-carrying limiting current. VS4 is low, meaning that the power supply short circuit protection is on.
Fig. 5 is a schematic diagram of an overcurrent/short circuit detection module, which mainly includes two buffers, two inverters, and three or gates. The VFLAG and input relation formula is The meaning is as follows: when VS1 is high level, VS2 is high level, VS3 is low level, or VS4 is low level, the VFLAG output is high level, which indicates that pull current or current filling flow in the circuit or that the circuit is short-circuited to power supply or ground; the user may turn off the circuit by detecting the VFLAG signal.
This embodiment is described in further detail by using a simulation method.
Fig. 6 shows a simulation setup diagram of a class AB amplifier with an over-current protection and detection circuit, comprising a class AB amplifier, two matching resistors R4 and R5, a load capacitor C1 and a load resistor R3. Wherein the resistances of the resistors R4 and R5 are the same, providing a unity gain. The capacitance value of the load capacitor C1 is 47uF, and the load resistor R3 simulates the earphone resistor and can be set to 8Ω, 16Ω, 32Ω, and the like.
The transient simulation result of the load-to-8Ω resistor in the simulation set of fig. 6 is shown in fig. 7. As can be seen from fig. 7, VOUT output is normal, and the peak-to-peak value vpp=2v. In the figure I MPP Is the static current of the MPP of the PMOS tube in the class AB output stage, I MNP Is the quiescent current of NMOS transistor MNP in the class AB output stage. In fig. 7, the peak current of the pull current is 114.8mA, the peak current of the sink current is 115.7mA, and the overcurrent limit value is not exceeded.
The transient overcurrent simulation result of the 4 omega resistor connected with the load under the simulation setting of fig. 6 is shown in fig. 8. As can be seen from fig. 8, VOUT voltage is significantly distorted, and peak-to-peak vpp=2v. The pull current was limited to 137mA and the sink current to 164mA. Therefore, the pull current overcurrent limiting value of the actual circuit is 137mA, and the pull current overcurrent limiting value is not much different from the theoretical analysis value of 144 mA; the limiting value of the overcurrent of the current is 164mA, which is not much different from the theoretical analysis value 173 mA. Meanwhile, when the pull current reaches an overcurrent limit value, VS1 presents a high level; when the sink current reaches the overcurrent limit, VS3 assumes a low level.
The transient simulation results of VOUT to ground shorts are shown in fig. 9. As can be seen from fig. 9, VOUT is shorted to ground between 100 μs and 103 μs, and the pull current is changed from 135mA, which is originally limited by the overcurrent, to 18mA, the sink current is small, and at the same time, VS1 is changed from high to low, VS2 is changed from low to high, which means that the circuit is shorted to ground.
The transient simulation results of VOUT versus ground are shown in fig. 10. As can be seen from fig. 10, VOUT is shorted to the power supply at 100 μs-103 μs, at which time the sink current is changed from 157mA, which is originally limited by the overcurrent, to 39mA, the pull current is small, and at the same time, VS3 is changed from low to high, VS4 is changed from high to low, meaning that the circuit is shorted to the power supply.
According to the invention, the MOS tube parallel to the power tube is adopted to induce current, and the drain end of the MOS sampling tube is connected in series with one MOS tube, so that the excessive current is avoided when the sampling MOS tube is in transient conduction; meanwhile, the drain end of the MOS sampling tube is enabled to follow VOUT, so that channel modulation effect is reduced, and sampling current is enabled to be more accurate. Second, a foldback current limiting unit is added to the circuit that further limits the load current when the circuit is shorted to power or ground. The short-circuit limiting current value is smaller than the overcurrent limiting current value, which also means lower power consumption, and provides a safe and stable working environment for the circuit.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (11)

1. The overcurrent protection and detection circuit suitable for the class AB output stage is characterized by comprising a pull-current overcurrent protection module, a current-filling protection module and an overcurrent/short circuit detection module;
the pull current overcurrent protection module is connected with the class AB output stage and is used for limiting the pull current of the class AB output stage and protecting the PMOS power tube of the output stage;
the current-filling overcurrent protection module is connected with the class AB output stage and is used for limiting the current filling of the class AB output stage and protecting an NMOS power tube of the output stage;
the overcurrent/short circuit detection module is connected with the pull current overcurrent protection module and the current filling overcurrent protection module at the same time and is used for generating an overcurrent or short circuit signal;
the class AB output stage is used for the last stage of the power amplifier and is used for driving a high-current load.
2. The overcurrent protection and detection circuit for class AB output stage of claim 1, wherein said class AB output stage comprises PMOS tube MPP and NMOS tube MNP; wherein,
the source electrode of the PMOS tube MPP is connected with a power supply VDD, and the grid electrode and the drain electrode of the PMOS tube MPP are both connected with the pull current overcurrent protection module; the source electrode of the NMOS tube MNP is grounded, and the grid electrode and the drain electrode are both connected with the current-filling overcurrent protection module;
the drain electrode of the PMOS tube MPP is connected with the drain electrode of the NMOS tube MNP to form a VOUT output end of the class AB output stage, and the output end VOUT can be externally connected with a load capacitor and a resistor to drive large current.
3. The overcurrent protection and detection circuit for class AB output stage of claim 2 wherein said pull-up current overcurrent protection module comprises a pull-up current overcurrent limiting unit, a pull-up current foldback current limiting unit, and a pull-up current detection unit;
the pull current overcurrent limiting unit is connected with the VOUT output end of the AB class output stage and the grid electrode of the PMOS tube MPP at the same time and is used for pull current monitoring and overcurrent limiting;
the pull current foldback current limiting unit is connected with the VOUT output end of the AB class output stage and the internal port of the pull current overcurrent limiting unit at the same time and is used for limiting the current of the VOUT output end short-circuited to the ground;
the pull current detection unit is connected with the internal port of the pull current overcurrent limiting unit and the internal port of the pull current foldback current limiting unit at the same time and is used for reversely amplifying an overcurrent detection signal and a short circuit to ground detection signal;
the pull current and overcurrent detection signal of the pull current and overcurrent protection module is VS1, and the short circuit to ground detection signal is VS2; the signal VS1 is high and overcurrent, and the signal VS2 is high and short-circuited.
4. The overcurrent protection and detection circuit applicable to the class AB output stage as set forth in claim 3, wherein the pull-current overcurrent limiting unit comprises NMOS transistors MN 1-MN 5, PMOS transistors MP 1-MP 5 and PMOS sampling tubes MPR;
the grid electrode of the NMOS tube MN1 is connected with the output end of the VOUT, the source electrode of the NMOS tube MN1 is connected with the source electrode of the PMOS tube MP1, and the grid electrode and the drain electrode of the PMOS tube MP1 are commonly connected with the source electrode of the NMOS tube MN 2;
the drain electrode of the PMOS tube MP2 is simultaneously connected with the drain electrode and the grid electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is connected with the drain electrode of the NMOS tube MN3,
the grid electrode of the PMOS sampling tube MPR is connected with the grid electrode of the PMOS tube MPP, the drain electrode of the PMOS sampling tube MPR is connected with the source electrode of the PMOS tube MP3, the grid electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP2, and the drain electrode of the PMOS tube MP3 is connected with the drain electrode of the NMOS tube MN 4;
the drain electrode of the PMOS tube MP4 is simultaneously connected with the grid electrode of the PMOS tube MP5 and the drain electrode of the NMOS tube MN5, and the grid electrode of the NMOS tube MN5 is simultaneously connected with the grid electrode and the drain electrode of the NMOS tube MN 4; the drain electrode of the PMOS tube MP5 is connected with the grid electrode of the PMOS tube MPP;
the drain electrode of the NMOS tube MN1, the source electrode of the PMOS tube MP2, the source electrode of the PMOS sampling tube MPR, the source electrode of the PMOS tube MP4 and the source electrode of the PMOS tube MP5 are all connected with the power supply VDD; the sources of NMOS transistors MN 3-MN 5 are all grounded.
5. The overcurrent protection and detection circuit for class AB output stage of claim 4 wherein said pull-up foldback current limiting unit comprises a PMOS tube MP6, an NMOS tube MN6 and a resistor R1; the source electrode of the PMOS tube MP6 and the first end of the resistor R1 are both connected with the power supply VDD, the drain electrode of the PMOS tube MP6 is connected with the grid electrode of the PMOS tube MPP, the grid electrode is simultaneously connected with the second end of the resistor R1 and the drain electrode of the NMOS tube MN6, the grid electrode of the NMOS tube MN6 is connected with the drain electrode of the PMOS tube MP3, and the source electrode of the NMOS tube MN6 is connected with the output end of the VOUT.
6. The overcurrent protection and detection circuit for class AB output stage of claim 5, wherein said pull-current detection unit comprises NMOS transistors MN7 and MN8, PMOS transistors MP7 and MP8; the sources of the PMOS tubes MP7 and MP8 are connected with the power supply VDD, and the sources of the NMOS tubes MN7 and MN8 are grounded;
the grid electrode of the PMOS tube MP7 is connected with the drain electrode of the NMOS tube MN5, and the drain electrode is connected with a signal VS1; the grid electrode of the PMOS tube MP8 is connected with the drain electrode of the NMOS tube MN6, and the drain electrode is connected with a signal VS2;
the grid electrode and the drain electrode of the NMOS tube MN7 are both connected with a signal VS1; the gate and drain of NMOS transistor MN8 are both connected to signal VS2.
7. The overcurrent protection and detection circuit for class AB output stage of claim 6 wherein said current sinking protection module comprises a current sinking overcurrent limiting unit, a current sinking foldback limiting unit, and a current sinking detection unit;
the current-filling and overcurrent limiting unit is connected with the VOUT output end of the AB class output stage and the grid electrode of the NMOS tube MNP at the same time and is used for current-filling monitoring and overcurrent limiting;
the current-sinking foldback current limiting unit is connected with the VOUT output end of the AB class output stage and the internal port of the current-sinking overcurrent limiting unit at the same time and is used for limiting the current of the VOUT output end short-circuited to a power supply;
the current-filling detection unit is connected with the internal port of the current-filling overcurrent limiting unit and the internal port of the current-filling foldback current limiting unit at the same time and is used for reversely amplifying the overcurrent detection and short-circuiting to a power supply detection signal;
the current-filling and current-flowing detection signal of the current-filling and current-flowing protection module is VS3, and the short circuit to power supply detection signal is VS4; the signal VS3 is short-circuited at a low level, and the signal VS4 is short-circuited at a low level.
8. The overcurrent protection and detection circuit applicable to the class AB output stage according to claim 7, wherein the current-filling overcurrent limiting unit comprises NMOS transistors MN 9-MN 13, PMOS transistors MP 9-MP 13 and NMOS sampling tubes MNR;
the drain electrode of the PMOS tube MP10 is simultaneously connected with the source electrode of the PMOS tube MP11, the drain electrode of the NMOS tube MN9 and the grid electrode of the PMOS tube MP11, and the grid electrode and the drain electrode of the NMOS tube MN 10; the source electrode of the NMOS tube MN9 is connected with the source electrode of the PMOS tube MP9, and the grid electrode of the PMOS tube MP9 is connected with the OUT output end;
the grid electrode of the PMOS tube MP13 is simultaneously connected with the grid electrode and the drain electrode of the PMOS tube MP12, the drain electrode of the PMOS tube MP13 is simultaneously connected with the grid electrode of the NMOS tube MN13 and the drain electrode of the NMOS tube MN12, and the drain electrode of the NMOS tube MN13 is connected with the grid electrode of the NMOS tube MNP;
the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN11, the grid electrode of the NMOS tube MN11 is connected with the drain electrode of the NMOS tube MN10, and the source electrode of the NMOS tube MN11 is connected with the drain electrode of the NMOS sampling tube MNR; the grid electrode of the NMOS sampling tube MNR is connected with the grid electrode of the NMOS tube MNP;
the drain electrode of the PMOS tube MP9, the source electrode of the PMOS tube MP10, the source electrode of the NMOS sampling tube MNR, the source electrode of the NMOS tube MN12 and the source electrode of the NMOS tube MN13 are all grounded; the source electrode of the PMOS tube MP10, the source electrode of the PMOS tube MP12 and the source electrode of the PMOS tube MP13 are all connected with the power supply VDD.
9. The overcurrent protection and detection circuit applicable to class AB output stage as set forth in claim 8, wherein said current sinking foldback current limiting unit comprises a PMOS tube MP14, an NMOS tube MN14 and a resistor R2; the source electrode of the PMOS tube MP14 is connected with the OUT output end, the grid electrode is connected with the drain electrode of the NMOS tube MN11, the drain electrode is simultaneously connected with the first end of the resistor R2 and the grid electrode of the NMOS tube MN14, the second end of the resistor R2 is grounded, the drain electrode of the NMOS tube MN14 is connected with the grid electrode of the NMOS tube MNP, and the source electrode is grounded.
10. The overcurrent protection and detection circuit for class AB output stage of claim 9, wherein said current sinking detection unit comprises PMOS transistors MP15 and MP16, NMOS transistors MN15 and MN16; the sources of the PMOS tubes MP15 and MP16 are connected with the power supply VDD, and the sources of the NMOS tubes MN15 and MN16 are grounded;
the grid electrode and the drain electrode of the PMOS tube MP15 are both connected with a signal VS3, and the grid electrode and the drain electrode of the PMOS tube MP16 are both connected with a signal VS4;
the drain electrode of the NMOS tube MN15 is connected with the signal VS3, and the grid electrode is connected with the drain electrode of the PMOS tube MP 13; the drain of the NMOS transistor MN16 is connected with the signal VS4, and the gate is connected with the drain of the PMOS transistor MP 14.
11. The overcurrent protection and detection circuit for a class AB output stage of claim 10 wherein the overcurrent/short circuit detection module comprises two buffers, two inverters, and three or gates; wherein,
the inputs of the two buffers are the signals VS1 and VS2 of the pull-up current overcurrent protection module respectively, and the outputs of the two buffers are the inputs of an OR gate; the input of the two inverters is signals VS3 and VS4 of the current-filling current protection module respectively, and the output of the two inverters is the input of the other OR gate; the output of the two or gates is the input of a third or gate, and the relation formula between the output end signal VFLAG of the third or gate and the input is vflag=vs1|vs2|vs3|vs4, namely when VS1 is high level or VS2 is low level or VS3 is low level or VS4 is low level, the VFLAG signal is high level, which indicates that the circuit has pull current or current flowing through or the circuit has short circuit to power supply or ground; the user turns off the circuit by detecting the VFLAG signal.
CN202310582827.7A 2023-05-23 2023-05-23 Overcurrent protection and detection circuit suitable for class AB output stage Pending CN117040449A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117707280A (en) * 2024-02-05 2024-03-15 江苏润石科技有限公司 Output stage control circuit with short-circuit current feedback limitation and application thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117707280A (en) * 2024-02-05 2024-03-15 江苏润石科技有限公司 Output stage control circuit with short-circuit current feedback limitation and application thereof
CN117707280B (en) * 2024-02-05 2024-04-23 江苏润石科技有限公司 Output stage control circuit with short-circuit current feedback limitation and application thereof

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