TWM311888U - Peak voltage detector having PMOS current source with dual charging paths - Google Patents

Description

M311888 VIII, new description: [New technology field] Voltage peak detector, especially Liben creative system butterfly - a dual charging circuit with PMQS electric surface search differential amplifier, a current mirror, a diode II #,LV 孩一 φ^ w The peak value and the complement of the gold and oxygen to obtain accurate electric [previous technology] ... electric (four) value detector is an electronic circuit, can measure the maximum value of a voltage waveform § The input of the circuit is a varying voltage signal, and the 1st round, σ slave output is the maximum value of the input voltage waveform. In the end of the day application, the peak value of the input voltage signal must be measured and then left to be left for subsequent analysis and use. - The peak value of a burst is often more useful than its average. The destructive job time is necessary to trace and protect the scale value signal, and the extension of the transmission medium & _ to the new conversion The voltage peak detector is also required for the device (趟_咖), the maximum approximate decoding ^ ΪΓΓ h00d decoding system, and the pulse for detecting nuclear radiation. In the prior art, the simplest method of the voltage peak detector is to pass the input voltage signal through the diode and charge the capacitor to obtain the peak value of the input voltage waveform. As shown in the first figure, when the input voltage V(IN) is greater than the voltage of the capacitor c, the diode is turned on, and the charging is performed until the input voltage V(IN) reaches its maximum value, and the capacitor C can no longer continue charging. At this time, the output voltage ν(ουτ) represents the peak value of the input voltage V(IN). Due to the presence of diode D between the output and the input, this circuit cannot accurately detect the true peak value of the input voltage V(IN). In other words, there is always an error in the diode turn-on voltage Vd between the output voltage ν(〇υτ) and the peak value of the input voltage V(IN). That is, MAx(V(0UT))=MAX(v(IN))_Vd, as shown in the second figure (this figure is a transient analysis simulation result of OrCADPSpice). For many applications, the above-mentioned error in the diode turn-on voltage Vd is undesired, and the voltage difference may vary due to the use of different diodes, which may cause adverse effects or unpredictable consequences. In order to accurately detect the peak voltage of the input, another commonly used prior art technique consists of two operational amplifiers OP1 and OP2, two diodes D1 and D2, two resistors R1 and phantom, and a M311888. The voltage peak detector is shown in the fourth diagram of the OrCADPSpiee transient as shown in the third figure. Among them, 0P1 is an accurate half-wave rectifier. When the input voltage is 4 voltage V(C), the second auxiliary D1 will transmit the bias voltage to charge the capacitor SCI, and also the input voltage and the peak of the output. When the peak value of the output V(IN) is close, there will be no error between the polarity of the electrode (W). When the input voltage capacitance % ϋ ^ ¥ (〇, , > diode m will be turned on, the diode di will be cut off and no longer operate on electricity, which makes the detected output voltage yeah It is equal to the input voltage 's. Although the voltage peak detector of the second picture of 5 can accurately detect the value voltage, but its circuit structure, it takes up the requirement of "_A, the actual non-observing circuit. So far, there are many voltage peaks. The technology of the detector is proposed in _9, 5502746, touch 27, 5969545, 嶋98, ^ t = Min ^ Patent Case No. 476418, all of which are capable of accurately measuring: The peak voltage of the input signal 'but because the voltage peak detectors use more than one of the amplifiers', there is a lack of circuit structure, large wafer area on the side, etc.; in addition, the voltage peak detection ϋ There is no consideration of how to save power consumption. Recently, several techniques have been proposed that do not require the use of precision voltage peak detectors for operational amplifiers, such as the Republic of China Patent Case No. Claw (6)? Tiger, No. 523592 Number (the main representative As disclosed in the fifth picture of the younger brother, the 122nd serial number, the 1223rd 79th, the 1223_th and the 22nd surface code, these techniques are proposed by the person in charge of the towel, which is The combination of a dynamic amplifier and a current mirror replaces the operational amplifier, and since it does not make an operational amplifier, it has a circuit, a simple structure, a small wafer area, and a small effect of miniaturization of the device. The technology does not consider how to reduce the power miscellaneous problem, so there is still room for improvement. In view of this, the main purpose of this creation is to propose a novel architecture voltage peak detector, which can not only accurately and quickly make A The peak voltage of the input is lower, and it can have lower power consumption than the first device. [New content] This creation proposes a dual charging path voltage peak detector with PM0S current source, which is driven by a difference M311888. The amplifier (1), a current mirror (2), a diode (3) and a capacitor n (6) are used. The differential amplifier (1) is used as a comparator, and the two input terminals respectively receive input signals. V(IN) and the detection output voltage feedback signal ν_), and provide the charging current to the current mirror (2), so as to obtain the peak value of the input signal V(IN) as the output voltage signal, and the current mirror (2) is used as a charger to provide a first charging current required for the capacitor (6), the differential amplifier (1) is composed of a first PMOS transistor (MP1), a second pm 〇S transistor (MP2), An NM〇s transistor (MN1), a second NMOS transistor (MN2), and a 臓 current source (IP), wherein the first _s transistor 匪 and the second _s transistor are used as drivers (driver) is used, the first germanium transistor MP1 and the first: PM〇S transistor MP2 are used as an active load, and the BIOS current source (IP) is used as a current source and is designed. In the form of a diode, a current is supplied to the differential amplifier (1) for use. The current mirror (2) in this creation is used as a first charger to provide a first charging current required for the capacitor, and the diode (3) is used as a second charger to provide a second required capacitor. The charging current, by virtue of the structure of the dual charging path, accurately and quickly knows the peak voltage of the input voltage waveform. The voltage peak detector proposed by the present invention not only accurately detects the peak voltage of the input signal, but also effectively reduces power consumption. [Embodiment]

According to the above purpose, the present invention proposes a peak detector with a current source of PM〇s, as shown in the sixth figure, which is composed of a differential amplifier, a current mirror 2, a diode 3 and a capacitor. The composition of c. Φ The differential amplifier 1 is composed of a first pMOS transistor MP: a PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor_2, and a PMOS current source IP, wherein the first NMOS The transistor MN1 and the second area 〇8 transistor MN2 are used as drivers, and the first PMOS transistor MP1 and the PMOS transistor MP2 are used as active loads, and the PMOS is used. The current source IP is composed of a PMOS transistor and is designed in the form of a diode to provide a current for the differential amplifier 1. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively receive the input signal V(IN) and the output voltage feedback signal V(〇UT) of the detector, and the source ( Source) connected together and connected to the source of the PMOS current source IP, and the poles thereof are respectively connected to the drains of the first PMOS transistor MP1 and the second PMOS transistor MP2; the PMOS current source The IP system consists of a PM〇s M311888 transistor whose gate is connected to the drain to form a diode and is connected to ground, and the source is connected to the first NM〇s transistor. And the source of the second die 8 transistor face 2, the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the power supply voltage Vdd, and the gates are connected together, and the first The gate of the second transistor 8 transistor Mp2 is connected to the drain line to form a current mirror configuration. Referring again to the sixth figure, the current mirror 2 is composed of a sPM0s transistor and a wpM〇s transistor MP4. Wherein, the third rigid (7) transistor and the source of the fourth pM〇s transistor are connected to the power supply voltage Vdd, and the gates are connected together and connected to the first surface 电8 transistor. a pole, and the gate of the third PMOS transistor MP3 is connected to the drain line to form a current mirror configuration; further, the drain of the PM0S transistor MP4 is connected to one end of the capacitor c, and the The electric climber presses the output of the peak detector, and the other end of the capacitor is grounded. The current mirror is used as a first charger to provide the first charging current required by the capacitor. As for the diode 3, it is composed of the NM〇S crystal face 3. Wherein, the 〇8 transistor _3 ^ 汲 and the gate are connected at - and connected to the input power (four), and the source is connected to the output. The two-pole system is used as a second charging port to provide a second charging current for the capacitor ride. For the sake of explanation, the following derivation process describes the simplest model of CAD PSpice, and does not consider the channel length modulation (Blood (10) η) effect. However, in the subsequent simulation verification, all the transistor parameters in PSpice (including, of course, the channel length modulation effect) are considered. _ 纟 / / ® circuit shows that 'capacitor II charging process can be divided into two stages, the first stage is to pull the output voltage ν (ο υ τ) to the input voltage V (four) of the sound value deduction Vt voltage level (where vt represents the threshold voltage of the NMOS transistor MN3) 'The second stage is to increase the output voltage Μν(〇υτ) from the peak decompression level of the output voltage to the input age (four) peak value Level. In the first stage, the structure has a dual charging path, i.e., the charging operation is performed with the first and second charging currents at the same time, so that the time required for the first stage can be effectively shortened. In the second phase, since the diode 3 is turned off, the capacitor is subsequently charged only with the first charging current. Here, in order to quickly complete the charging operation of the capacitor, the first charging current is designed to be larger than the second charging current. In the "Hai Ps# again, in terms of the first charging current, since the input voltage is zero ^) is greater than the capacitance, so the electric thin (MN!) will be greater than _Id (MP2), where the inflow The current of the crystal takes the positive sign of M311888, while the current flowing out of the transistor takes a negative sign, that is, the current I(i(MNl) represents the drain current flowing into the first nm〇S transistor MN1, and -Id (MP2) Then represents the drain current flowing out of the second PMOS transistor MP2. Again (1) (2) (3) - Id (MP1) = _Id (MP2) - Id (MP3) = Id (MN1) - [-Id (MP1)] So - Id (MP3) > PMOS PMOS transistor MP3, MP4 is also a current mirror configuration composed of pm 〇 S transistor, when -Id (MP3) > ,, current (MP4) will be equal to _ Id (MP3), so the capacitor c can be charged (the current -Id (MP3) is the first charging current mentioned above). Again, in terms of the second charging current, the input voltage V(IN) The voltage level of the peak deduction vt is greater than the capacitor voltage v(c), and the current 'current Id_3' also charges the capacitor c (the current Id (MN3) is the second charging current described above). In this second phase, 'the voltage level of the deducted vt due to the peak value of the input voltage V(4) is less than the capacitance voltage V(C) 'so the diode 3 is turned off, that is, the second charging current I d (MN3) = 〇(4) Differential: When the output voltage is at the peak of the turn-in signal, since (5) -Id (MP1) = 4d (MP2) = id (MN〇, current (6) - Id (MP3) = -id (MP4) = 〇 峰 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入-Id (MP3) = -Id (MP4) = q Therefore, the capacitor H will not be charged, so it will remain at the peak of the input signal IN). (4) _ MV (OUT) is still shown in the q-pSpice transient analysis simulation of the voltage peak detector proposed by the author. The simulation result can be used. The voltage proposed by the author self-tests the peak voltage of the input signal. . The shirt heart b is exactly 4 Huan. Next, how to reduce the power consumption of this creation. First, compare the case number No. 523· of the case number shown in the fifth figure to the peak value of the detector.

Because of the prior art towel shown in FIG. 5, (4) the NMOS transistor _3 used to supply the _ current to the differential illuminator 1 is connected to the power supply voltage, and therefore, the third ray is deleted from the source. The voltage is always equal to the power supply voltage blue. In contrast, the PMOS current source (4) used by the generator to provide an electric/difference amplifier 1 is composed of a p-brain crystal and is designed in the form of a polar body, which is also to be used as a PMOS current source IP. The gate of the PM〇s transistor is connected to the drain and connected to the ground. Therefore, the absolute value of the pM〇s transistor gate voltage Vc^ used as the PM〇s current source Ip is used. The value is constant less than the source voltage of the third (10) transistor shown in the fifth figure; riding, the invasive side reads the m to the difference, and the pM〇s current source IP is made of -PMOS. The crystal consists of the '(4) and the fifth figure shown in the previous figure. The third NMOS transistor MN3 used for the differential amplifier 1 is composed of a _8 transistor.

(7) The transconductance parameter of the PMOS electric solar field is usually smaller than the mutual conductance parameter of the njvjos transistor (the mutual conductance parameter KP represents the parameter of the gold-oxygen semi-transistor model in OrCAD Pspice), so it is used to supply current. In the case where the transistor used for the differential amplifier has the same effective channel width/length ratio, the present writing has a lower power consumption than the prior art shown in the fifth figure. The eighth figure shows the 峰值rCADPSpice transient analysis simulation result of the voltage peak detector (previous skill) of the Republic of China Bulletin No. 523592 and the artificial voltage peak detector, which can be proved by the simulation result. The voltage peak detector of the present invention has a lower current consumption than the prior art. The eighth figure is simulated with the level 3 model and using the 〇·25 micron CMOS process parameters (the zero-substrate bias voltage values ντο of the PM0S transistor and the NMOS transistor are -〇.5V and 〇.5V, respectively). Among them, the channel width to length ratio of PMOS transistors ΜΡ1, ΜΡ2, MP3, and MP4 are (W/L)=(2 · 0.25μηι/0.25μηι), and the channel width to length ratio of NMOS transistors ΜΝbΜΝ2 and ΜΝ3 are both (w/L)=(0.25pm/0.25Mm), the channel width to length ratio of NMOS transistor MN3 is (W/L)=(〇.25pm/8 · 0·25μιη), as a power supply 10 M311888 flow is provided PM〇Sf used by the differential amplifier 1: the channel width-to-length ratio of the current source_pM〇s transistor is (W/L)=(0.25pm/8 · 〇.25μιη), and the capacitance value of the capacitor C is _ . The peak voltage detection of this creation! In use, the _ switch can be connected in parallel across the capacitor c. The open relationship (4) provides a -discharge path, and (10) detects the peak value of the residual red charge input voltage signal. Next, [Creation Function], the voltage peak detector proposed by the author has the following effects: (1) Miniaturization: Since the voltage peak detector proposed by this creation only makes Xinlai Lai, Jian Zheng and 1 Capacitor 11, therefore, not only the circuit frame power * because =: the device confirmed by the simulation results 'definitely reduce the voltage peak value of the differential amplifier. 11 read by the simulation result, it can be effectively consumed. Motor / Xiao consumption, so it can effectively reduce the power consumption of the voltage peak detector. Although this book is specially designed for the public, anyone can understand any form of the way to describe the best embodiment selected, but familiar with the technology. Therefore, all relevant technical norms 4 = possible changes are not divorced from the spirit and scope of this creation. Changes in & π are included in the scope of the patent application of this creation. M311888 [Simple diagram of the diagram] The first diagram shows the circuit diagram of the voltage peak detector in the first prior art; the second diagram shows the transient analysis of the input voltage signal and the output voltage signal of the voltage peak detector of the first diagram. a timing diagram; a third diagram showing a circuit diagram of a voltage peak detector in a second prior art; and a fourth diagram showing a transient analysis timing diagram of an input voltage signal and an output voltage signal of the voltage peak detector of the third diagram; The fifth figure shows the circuit diagram of the voltage peak detector of the Patent No. 523592 of the Republic of China; the sixth figure shows the circuit diagram of the voltage peak detector of the preferred embodiment; the seventh figure shows the creation The transient analysis timing diagram of the input voltage signal and the output voltage signal of the preferred embodiment; the eighth figure compares the transient state of the peak voltage detector of the present invention with the voltage peak detector of the Patent No. 523592 of the Republic of China Current analysis timing diagram. [Main component symbol description] 1 Differential amplifier 2 Current mirror 3 Diode C Capacitor D Diode D1 Diode D2 Diode Id (MN3) NMOS transistor MN3 drain current 0P1 Operational amplifier OP2 Operational amplifier MP1 First PMOS transistor MP2 second PMOS transistor MP3 third PMOS transistor MP4 fourth PMOS transistor MN1 first NMOS transistor MN2 second NMOS transistor IP PMOS current source Vdd power supply voltage R1 resistor R2 resistor V ( IN) Input voltage signal V (OUT) Output voltage signal

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Claims (1)

M311888 IX. Application for Patent Park: 1. A voltage peak detector with dual charging paths, comprising: an input terminal for providing an input voltage signal; and an output terminal for outputting a peak value of the input voltage signal Voltage; - power supply, used to provide the voltage and reference ground required by the voltage peak detector; - differential amplification H, the rib is more than the input voltage and the input (four) is a charging current to the current mirror, And the wire amplifier has a PMOS current source (IP) for providing an electric differential, and the PM0 current source (Ip) is composed of a PMOS transistor connected in the form of a diode. The gate of the pM〇s transistor is connected with the immersion pole; • The electric keeper 'noisy listens to the charging current provided by the magnifying lining, and provides the first charging current to the capacitor; - the polar body, the polar body - The end is connected to the input end, and the other end is connected to the capacitor for providing a second charging current to the capacitor; and the electric grid is connected to the reference ground and the other end is connected to the current mirror With the diode, Receiving the current mirror and the first and second charging currents supplied by the diode. 2. The voltage peak detector having a dual charging path as described in claim 1 further comprising: a switch, a delta-open relationship connected in parallel with the capacitor for providing a discharge path for the capacitor to be mounted The stored charge is discharged, which is beneficial to the peak detection of the next input voltage signal. • 3. A voltage peak detector having a dual charging path as described in claim 2, wherein the open relationship consists of a MOS transistor. 4. The voltage peak detector having a dual charging path as described in claim 1, wherein the differential amplifier comprises: a first PMOS transistor (ΜΡ1) whose source is connected to a power supply voltage (Vdd) The gate is connected to the gate of the PM0S, the body (MP2), and the drain is connected to the current mirror and the drain of the first NM〇s transistor (_丨); a second PMOS The transistor (MP2) has a source connected to the supply voltage (Vdd), a gate connected to the drain and connected to the gate of the first PMOS transistor (MP1), and the drain is connected to the second MN 08. a drain connection of the transistor (face 2); a first NMOS transistor (MN1) whose source is the source of the :NM〇S transistor (MN2) and is used as a 13 M311888 PMOS current source (IP) The source of the PMOS transistor is connected, the gate is for receiving the input voltage signal, and the drain is connected to the current mirror and the first PMOS transistor (MP1) i; a second NMOS transistor ( MN2), the source is connected to the source of the first NMOS transistor (MN1) and the source of the PMOS transistor used as the PMOS current source (IP), and the gate is used for connection The output voltage of the output terminal is fed back, and the drain is connected to the drain of the second PMOS transistor (MP2); and a PMOS current source (IP) is connected by a pM connected in the form of a diode. The s transistor is composed of a gate of the PMOS transistor connected to the drain and connected to the reference ground, and the source is connected to the source of the first and the second NMOS transistors (_1 and _2) The pole phase is connected to the PMOS transistor system used by the current source (IP) to provide a current for the differential amplifier. 5. The voltage peak detector having a dual charging path according to claim 4, wherein the current mirror comprises: a third PMOS transistor (MP3) whose source is connected to a power supply voltage (vdd), The gate is connected to the drain and connected to the drain of the first NMOS transistor read ;; and an izg PMOS transistor (MP4) whose source is connected to the power supply voltage (vdd), the gate and the third pM The gate of the 〇s transistor (MP3) is connected, and the drain is connected to the capacitor (c) and the second 〇8 transistor (the phantom gate). 6. As described in claim 1 A voltage peak detector having a dual charging path, wherein the two-pole system is composed of a MOS transistor.