TWI288239B - Peak voltage detector having lower current consumption - Google Patents

Abstract

A peak voltage detector having lower current consumption includes a differential amplifier (1), a current mirror (2) and a capacitor (C). Among them, the differential amplifier serves as a comparator, receiving both the input signal V (IN) and the output feedback signal V (OUT), and the current mirror supplies the capacitor with needed charge current. The different amplifier consists of the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1), the second NMOS transistor (MN2) and the third NMOS transistor (MN3). Within which, the NMOS transistors MN1 and MN2 work as drivers while the PMOS transistor MP 1 acts as the load transistor, and the NMOS transistor MN3 configured as a diode form provides a reference current to the differential amplifier. The peak voltage detector can both accurately measure the peak voltage of input signal and efficiently lessen the power dissipation.

Description

1288239 IX. Description of the Invention: [Technical Field] The present invention relates to a voltage peak detector, in particular to a differential amplifier, a control transistor, and a capacitor. ^ 二 = Power consumption of mutual contribution of gold and oxygen (CMOS). $4 value and low [Prior Art] ▲ Voltage peak detector system - a kind of electronic circuit, can get the maximum value of the voltage waveform

1. The input of the circuit is a variable-varying voltage signal, and its input_ is the maximum value of the input voltage waveform. In many applications, the peak value of the input voltage signal is measured and then stored in a DC mode. The tip of the _ _ _ peak is often more useful than its average value ' For example, when performing destructive testing, it is necessary to trace and maintain the peak signal, and the voltage of the tree is more difficult to slash, difficult to _ A voltage peak detector is also required for fine (鸠_赠), maximum approximate decoding system (dirty imum likelihood decoding system), and pulse signal detection circuit for detecting nuclear shot. In the prior art (_* art), the simplest method of the voltage peak detector is to pass the input voltage signal through the diode and charge the capacitor to obtain the peak value of the input voltage waveform. As shown in the first figure, when the input voltage V(IN) is greater than the voltage of the capacitor C, the diode 〇 turns on and performs charging until the input voltage V(IN) reaches its maximum value, and the capacitor c can no longer continue charging. At this time, the output voltage V(0UT) represents the peak value of the input voltage V(IN). a Due to the presence of diode D between the output and the input, this circuit cannot accurately detect the true peak value of the input voltage V(IN). In other words, there is always an error in the diode turn-on voltage vd between the output voltage ν(〇υτ) and the peak value of the input voltage V(IN). That is, MAX(V(〇UT))=MAX(V(IN))-Vd, as shown in the second figure (the figure is “the result of his transient analysis simulation”). For many applications, the error of the above-mentioned diode turn-on voltage vd is undesired, and the voltage difference may vary due to the use of different diodes, which may cause adverse effects or unpredictable consequences. . 5 1288239 'In order to accurately detect the peak voltage of the input, the other is composed of two operational amplifiers OP1 and (10), two techniques, and a capacitor c. - Power plant scale and PSpice transient Analyze the simulation results as shown in the fourth figure. Among them, t map — - not 'its: 〇 rCAD wave rectifier, when the input voltage V (IN) is greater than the capacitance 疋 her true half capacitance is charged, the most (four) capacity transmission unicorn, peak _ can "detect Scale value, but its circuit junction; large area, is not conducive to the requirements of integrated circuits. ', Spoon 曰曰 so far, there are many voltage peak detector technology by the brain _9, 5502746, 55 raise 7, 5% 9545, 6 〇 5i998, j ^ and the Republic of China patent case number 476418 minus θ σ 472861 accurately detects the peak value of the input signal in the 'the temple technology can lose this ί there is a circuit structure is complex, occupying a large area of the wafer, etc. recently 'here lost (four) fine == Yan Yan) 517161 ί t ^«1 ^ 1 78 ^ 1223079 ^ 1223080 ^ ^3〇δ! The road revealed by the 疋 疋 'transfer technology is proposed by the applicant, the fine-current mirror shun into the replacement of the operation Α | |, because of the material = 'occupied ^ area is small and is conducive to the device, etc.;!;,;:: The power consumption of the earth-density voltage therapy detector, the applicant has proposed the Republic of China ...,, 7_ 5 tiger "Phase detection device with low power consumption", the main case of 1288239 is used to connect to the input signal V(IN) and as a current source for the M, - current difference. The use of the dynamic amplifier 丨 between the transistors between the poles of the emperor: the voltage level, and dynamic control For the current - the second cry, the main purpose of the Ming is to propose a novel structure of the electrical surface value detection control transistor 'and can accurately and quickly detect the input peak voltage of the secondary, the same day, the village is less than the first The invention provides a voltage peak detector with low power consumption, which is composed of a differential amplification crying and a capacitor c, wherein the differential amplifier 1 is ^ ', the two input terminals respectively receive the input signal V (IN) and the output voltage of the detector feedback U Hu ν (ουτ) ' and provide the appropriate charging current to the current mirror 2 to obtain the input signal v (10)) 2 The value is used as an output voltage signal, and the current mirror 2 is used as a charger to provide a charging current required for the electric valley. The differential amplifier i is deleted by the first pM〇s transistor, and the first PMOf The transistor MP2, the first-NM〇s transistor ^^, the second transistor 3 transistor, and the second NMOS transistor MN3, wherein the first transistor 8 is an NMOS transistor The MN MN2 is used as a driver, the first pM 〇§ The crystal MP1 and the first PMOS transistor MP2 are used as an active load, and the third NMOS transistor MN3 is used as a current source and is designed in the form of a diode to provide a current to the difference. The motor amplifier 1 is used. The voltage peak detector proposed by the invention can not only accurately detect the hybrid signal of the input signal, but also effectively reduce the power consumption. [Embodiment] According to the purpose of the present invention, the present invention provides a voltage peak detector with low power consumption, as shown in the seventh figure, which is composed of a differential amplifier, a current mirror 2, and a capacitor. Composed of. The differential amplifier 1 is composed of a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NM〇s transistor mn2, and a third _8 transistor _3 1288239. The first NMOS transistor MN1 and the second MN8 transistor 2 are used as drivers, and the first PMOS transistor MP1 and the second PMOS transistor MP2 are used as active devices. The active load is used, and the third NMOS transistor MN3 is used as a current source and is designed in the form of a diode to provide a current for the differential amplifier 1. • The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively receive the input signal V(IN) and the output voltage feedback signal of the detector (〇111), the source (3) 〇ι^) connected together and connected to the drain of the third NMOS transistor MN3, and the drain thereof is connected to the drains of the first PMOS transistor MP1 and the second PMOS transistor MP2, respectively; The gate of the second NMOS transistor MN3 is connected to the gate to form a diode, and the source: then = φ; the source of the first PMOS transistor 1 and the second PMOS transistor MP2 Connected to the power supply voltage vdd, and connected together, and the first: PM0S transistor is connected to the poleless pole to form a current mirror configuration.

Referring again to the seventh figure, the current mirror 2 is composed of a third PMOS transistor and a fourth PM〇S transistor MP4. Wherein, the source of the sPM 〇s transistor Mp3 and the fourth 〇8 transistor are connected to the power supply voltage Vdd, and the gates are connected together and connected to the first 〇 电 transistor MN1 a pole, and the gate of the SPM〇s transistor Mp3 is connected to the drain line to form a current mirror configuration; further, the fourth gate 8 transistor 4 and the capacitor C One end is connected and the output of the voltage peak detector is formed, and the other two of the capacitors are grounded.

® In order to make the thief clear, the derivation process of the town, the gold oxide half f crystal is 单rCAD PSpice (4) single mode bribe, and the effect of the length of the road (ehannd ^ her m-lation) effect. However, in the subsequent simulation verification, all the electro-crystal parameters (including the channel length modulation effect) are considered. It is known from the circuit shown in the seventh figure that when the input signal V(IN) is greater than the capacitor voltage V(C), the current

Id (MN1) will be greater than (MP2), in which the current flowing into the transistor takes a positive sign, and the current flowing out of the transistor takes a negative sign, that is, the current Id (face) represents the flow into the first 〇 电 transistor MN1 And / the extreme electric level 'and - Id (MP2) represents the second pole of the second PM 〇 S transistor Mp2. Also (1) -Id (MP1) = -id (MP2) 8 !288239 (2) Therefore -Id (MP3) > 电流 and the third PMOS transistor MP3, the fourth a (3) crystal consists of the current mirror configuration, so the t_Id body MP±4 is also - is PMOS-electrically equal to -Id (MP3), so it can be used for capacitors. The current-Id (MP4) will be V(Q) equal to the peak value of the input money v(10). (OUT) (that is, when the charging action reaches _UT) is equal to the role of the input signal simplifier, when the current 冤 value is pressed, due to the differential (4) - Id (MPl) - Id (MP2) = ld (MNl) Therefore, the current (5) output voltage V(OUT) will be -Id (MP3) = -Id (MP4) = 〇: the capacitor is no longer charged, so the detected S-th is the peak value of the input signal V(IN). Voltage. Finally, when the input signal V(IN) is smaller than the output voltage v in the cut-off region, the current C: pM〇S transistor MP3 will have -Id (MP3) = -ld (MP4) = 〇 (6) so the capacitor will not be charged. V(_ will still maintain the peak voltage of the input signal V(IN). The output of the measured electric star is verified by the voltage peak detector of the present invention. In fact, the present invention proposes to accurately detect the peak voltage of the input signal. 杈A 时月 b Announcement ^=明^=^ Less power consumption, first compare the Republic of China electric age value detector shown in the fifth figure The invention is better than the seventh embodiment: Ι*Γ4Τ:Γ;^Γ———- 8-1 is used by the second transistor _3 is designed as 1288239 transistor face 3 is connected to it Bungee, because of the power supply m, the result of the invention can reduce the power consumption. The voltage of the Republic of China Announcement No. M2762 专利 patent case shown in the peak fresh six figure = use the figure ^ difference example, Since the third NMOS transistor MN3 used in the previous ^, charter, and 6 differential amplification 所示1 shown in FIG. 6 is turned on to the output terminal of the control transistor 3 The control transistor 3 is calculated as a diode (the type is connected between the input terminal of the voltage axis detector and the third electrode of the third transistor), and the dipole current flows through the differential body. Therefore, the side voltage Vg side between the third _s transistor surface used to provide - current feed amplification to 1 is equal to D (control transistor;)

'G3 (Fig. 6) = V(IN) - V # indicates the threshold voltage of the control transistor 3 (9) - during the charging process of the second capacitor, since the third cis 0s transistor surface 3 is connected ίί The three gates of the 0S transistor Gu 3 gate voltage v - the gates of the v body to delete the source voltage 'that is, the third ship 0S transistor coffee gate voltage ν 〇 3 (the invention) can be written

G3(^m) — V(IN)-VT(MN1)- [2 · Id (MNl ) · L/(KP · W)] 1/2 (8) where 'Vtxmn^ denotes the threshold voltage of the first transistor, % and l: The effective channel width and the effective channel length of the first NMOS transistor, and it is difficult to show one of the parameters of the metal oxide semi-transistor in OrCADPspice. Comparing equations (7) and (8) can be inferred

Vg3 (Fig. 6) > VG3 (this issue) (9) Therefore, the invention can be compared with the voltage peak of the Republic of China Announcement No. Μ". Patent No. 1288239 'Jie has a small current consumption. -σ The ninth figure shows the 峰值rCAD state analysis simulation result of the voltage peak detector (previous skill) of the Republic of China Announcement No. M276200 and the voltage peak detector of the present invention, which can be confirmed by the simulation result. The voltage peak detector of the present invention can have more power consumption than the prior art. The ninth figure is simulated with a level 3 model and using a 〇·25 micron CMOS process parameter (its PMOS transistor and NM〇s) The zero-substrate bias voltage value Vt〇 of the transistor is _5V and 〇·5ν, respectively, wherein the channel width length of the PMOS transistors MP1, MP2, MP3, and MP4 is (W/L)=( 2 · 0.25μΓη/〇.25μιη), then the channel length ratio of the 眺 眺 议 2 和 2 and surface 4 is (W / LH 〇 ^ m / 0.25 _, Gu 〇 8 transistor should be 3 channel width and length The ratio is Φ (W/L) gas 〇 · 25μηι / 8 · 0.25 (four), and the capacitance value of the capacitor C is 8 PF. The voltage peak detector of the present invention can be used when A switch is connected in parallel to both ends of the container c for providing a -discharge path for discharging the charge stored on the capacitor for peak detection of the next input voltage signal. [Effect of the invention] The voltage peak proposed by the present invention The detector has the following effects: (1) High integration degree and miniaturization of the device: Since the dragon peak detection proposed by the present invention does not need to add a control transistor, and only 4 Gangqiao 8 electron crystals are used. Milk, p NM〇S transistor and a capacitor, so not only the circuit structure is novel, the number of simple ECG crystals is small, and because it does not need to use an operational amplifier, it is beneficial to the miniaturization of the device; eight preparations have one (2) accuracy. The electrical identification test of the present invention can accurately detect the peak electric power S of the input signal, and therefore has high accuracy, and the worry value is 1 ^ ^ solution value, the power of the lion, the power consumption, Effectively reducing the voltage edge value detection = the selected preferred embodiment, but all the related techniques of the technology are all included in the patent application of the present invention, Fan Shenwei ^ 11 12 88239 [Simple diagram of the diagram] The first diagram shows the circuit diagram of the voltage peak detector in the previous technique; the second diagram of the voltage, Zhizhi shows the input voltage signal of the first graph voltage peak detector in the state analysis Timing diagram; 】 The third diagram shows the circuit diagram of the voltage peak detector in the second prior art; the fourth diagram shows the input voltage signal and state analysis timing diagram of the voltage peak detector of the third diagram; The five-figure diagram of the chain shows the circuit diagram of the voltage peak detector in the previous prior art;

FIG. 6 is a circuit diagram showing a voltage peak detector in a fourth prior art; FIG. 7 is a circuit diagram showing a voltage peak detector according to a preferred embodiment of the present invention; and FIG. 8 is a view showing a preferred embodiment of the present invention. The timing diagram of the input voltage signal and the output voltage signal; ^ (three) state current bifurcation timing ninth diagram is compared with the voltage peak detector of the present invention and the fourth prior art transient diagram 0 [main component symbol description] 1 differential amplifier D diode D2 diode 0P1 operational amplifier 2 current mirror D1 diode

Id(MN3) NMOS transistor MN3 drain current 0P2 operational amplifier JW1 first PMOS transistor MP2 second PMOS transistor MP3 third PMOS transistor MP4 fourth PMOS transistor first NMOS transistor MN2 second NMOS transistor Third NMOS transistor Vdd power supply voltage

Rl resistor R2 resistor V(IN) wheeled voltage signal ν(〇υτ) output voltage signal c capacitor 12

Claims (1)

1288239 IX. Patent application scope: 1. A voltage peak detector, comprising: an input terminal for providing an input voltage signal; and an output for outputting the learned value of the input voltage signal; Money L provides the light peak detection of the rider's ride (side) and reference connection ^m1) 'paste_input voltage signal and the output voltage feedback signal of the output, sub & charge current signal to the current mirror (2 ), the differential amplifier (1) has a method , and: supply - current to the differential amplifier (1) using the third (10) transistor (office) = brother two MOS transistor _3) is designed in the form of a diode, that is, the third (MN3) gate The pole is connected to the drain pole; the 电流^-current mirror (2) is configured to provide a charging current to the capacitor (〇; and ', private ball) according to the charging current signal provided by the differential amplifier (1) One end of the capacitor is connected to the current mirror (7) to receive the charging current supplied by the current mirror, and the other end is connected to the reference ground. ^ 2. The voltage peak detector according to claim 1, which further comprises: The switch is connected in parallel with the capacitor ||, and the rib provides a discharge path for discharging the charge stored on the capacitor for the peak detection of the next input voltage signal. 3. The voltage peak detector of claim 2, wherein the open relationship consists of a metal oxide semi-electric crystal. 4. The voltage peak detector according to claim 1, wherein the differential amplifier (1) comprises: a first PMOS transistor (MP1) whose source is connected to a power supply voltage (Vdd), and a gate The gate of the second pM〇s transistor (MP2) is connected, and the drain is connected to the drain of the current mirror (7) and the first NM〇s transistor (MN1); a second PMOS transistor (MP2) ), the source is connected to the power supply voltage (vdd" the gate is connected to the drain and connected to the gate of the first PMOS transistor (MP1), and the drain is also connected to the :NM〇s transistor (MN2) a drain connection; a first NMOS transistor (MN1) whose source is connected to the source of the second NM〇s transistor (_2) and the drain of the second NMOS transistor (MN3), the gate For receiving the input voltage signal, 13 1288239 is infinitely connected to the current mirror (2) and the first PMOS transistor (MP1), and a second NMOS transistor (_2), the source is The source of the first NMOS transistor (_丨) and the tNMOS transistor (dirty 3); and the pole phase connection, the interpole is used to receive the output voltage feedback signal of the output terminal, and the drain electrode and the first a drain of the 3M0S transistor (MP2) is connected; and a third NMOS transistor (_3) having a source connected to the reference ground, the gate connected to the drain, and the first and second NMOS transistors The source of (_丨 and _2) is connected, and the third NMOS transistor (MN3) is used as a current source and is used to provide a current for differential amplification. 叩5·申申= patent scope item 4 The voltage peak detector, wherein the current mirror (2) comprises: - a JMOS transistor (MP3) having a source connected to the supply voltage network, a dummy pole connected to the drain, and connected to the drain of the first NMOS transistor _丨; and - a fourth PMOS transistor (MP4) ), the source is connected to the power supply voltage (vdd), and the pole is connected to the gate, and the pole is connected to the gate of the second (10) (MN2). % Bg m 14