TWM335097U - Peak voltage detector having controllable NMOS current source and output stage - Google Patents

Description

M335097 VIII. New description: [New technical field] This is a voltage peak detector with controllable NM〇S current source and output stage, especially using differential amplifier, charging transistor, The output stage, the control circuit, and a capacitor are composed of a tree (4) that has a peak value and has a low power, and a closed-end CMOS (cm 〇 s) electronic 'circuit. [Prior Art] A voltage peak detector is an electronic circuit capable of measuring the maximum value of a voltage waveform. In other words, the input of the circuit is a varying voltage signal, and the output is the waveform of the input voltage. Maximum value. In many applications, the peak value of the input voltage signal must be measured and then retained in a DC mode for subsequent analysis and use. The peak value of a burst is often more useful than its average value. For example, when performing a destructive test, it is necessary to trace and maintain the peak signal, and measure the attenuation of the voltage signal on the transmission medium, analog to digital. A voltage peak detector is also required for a converter (A/D converter), a maximum likelihood decoding system, and a pulse signal detecting circuit for detecting nuclear radiation. In the prior art, the simplest method of the voltage peak detector is to pass the input voltage signal through the diode and charge the capacitor to obtain the peak value of the input voltage waveform. φ As shown in Fig. 1, when the input voltage V(IN) is greater than the voltage of the capacitor C, the diode D is turned on, charging is performed until the input voltage V(IN) reaches its maximum value, and the capacitor c can no longer continue charging. At this time, the output voltage V(OUT) represents the peak value of the input voltage ν(ΙΝ). ' Due to the presence of diode D between the output and the input, this circuit cannot accurately detect the true peak value of the input voltage • V(IN). In other words, there is always an error in the diode turn-on voltage Vd between the output voltage V (〇UT) and the peak value of the input voltage V(in). That is, MAX(V(OUT))=MAX(V(IN))-Vd, as shown in Fig. 2 (the graph is a transient analysis simulation result of 〇rCADPSpice). For many applications, the above-mentioned error in the diode turn-on voltage Vd is undesired, and the voltage difference may vary due to the use of different diodes, which may cause adverse effects or unpredictable consequences. In order to accurately detect the peak voltage of the input, another common prior art technique uses two 5 M335097 operational amplifiers OP1 and OP2, two diodes D1 and D2, two resistors R1 and R2, and a capacitor. C to form a voltage peak detector, as shown in Figure 3, the transient analysis results of OrCADPSpice, as shown in Figure 4. Where 〇Pi is a precise half-wave rectifier, when the input voltage V(IN) is greater than the capacitor voltage, the diode charges the capacitor C1 with a transfer bias, and finally the capacitor power > 1V(C) will The peak voltage of the input voltage V(IN) is quite close, and the detected output voltage V((^UT) is also close to the peak voltage of the input voltage V(IN), and will not be output as shown in Fig. 2. There is a difference between the diode and the input terminal, and when the input voltage V(IN) is lower than the capacitor voltage V(C), the diode D2 will be turned on, and the diode D1 will be turned off. The capacitor c is no longer charged, which causes the detected output voltage 卩(〇171) to be equal to the peak voltage of the input voltage ν(ιΝ). Although the voltage peak detector of Fig. 3 can accurately detect The peak voltage, but its complicated circuit structure and large occupied wafer area, is not conducive to the requirements of integrated circuits. So far, many techniques for voltage peak detectors have been proposed, for example, in U.S. Patent Nos. 5,304,939, 5,502,746, 5,546,027, 5969545, 6051998, 6064238 and 6472861 And the Chinese Guardian (4) Announcement No. 476. The cap reveals that the technique can accurately detect the peak voltage of the input signal, but since the voltage peak detectors use more than one operational amplifier, There are missing circuit structures and large occupied wafer areas; in addition, these voltage peak detectors do not consider how to save power consumption. Recently, there are several types of precision voltage peak detection that do not require the use of operational amplifiers. The technology of the device is proposed, for example, the Republic of China Patent Case No. 517161, No. 523592, No. 1223〇78, No. 1223079, No. 1223080, No. 1222881 (the main representative figure is shown in Figure 5 According to the disclosures of °, Μ276Θ9, M311888, M315336, M315337 and M315338, these techniques are proposed by the present applicant, which is a circuit composed of a differential amplifier and a current mirror. Oh, since the operational amplifier is not turned off, it has a simple circuit structure, a small area of the chip, and a miniaturization effect of the device. However, these technologies are not Only in certain conditions (the lining _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In view of this, the main purpose of this creation is to propose a new structure with controllable sinus current source and output stage voltage mismatch detection n, which can not only accurately and quickly detect the value voltage New Zealand has a more apologetic consumption than the previous Laifeng recorder. 4 Peak M335097 The second objective of this creation is to propose a novel architecture with a controllable current source and output stage voltage peak detector. Considering the mechanism that enables the voltage peak detector only in certain situations, thus reducing power consumption. [New content] • This paper proposes a novel architecture with controllable NMOS current source and output stage voltage peak detector, which is composed of a differential amplifier (1), a charging transistor (2), and a capacitor. (C), an output stage (3), a control circuit (4) and a capacitor (c), wherein the differential amplifier (1) is used as a comparator, and the charging transistor (2) is Used as a charger to supply the charging current required by the capacitor (C), and the output stage (3) is used to adjust the spring voltage signal V(C) on the capacitor (c) to accurately output the The peak voltage of the input signal. The differential amplifier includes a first PMOS transistor (MP1), a first nm 〇S transistor (MN1), a second NMOS transistor (MN2), and a current composed of a NMOS transistor (MN). Source (ip), wherein 'the first NMOS transistor (MN1) and the second _08 transistor (MN2) are used as a driver, and the first PMOS transistor (MP1) is used as a single The side load transistor is used, and the single-sided load transistor and the charging transistor (2) together form a current mirror, and the current source (IP) composed of the transistor (_) is controlled by the control circuit (4) To control the conduction (〇n) or off (〇ff) state, when the current source (ip) composed of the NM0S transistor is in an on state, a current can be supplied to the differential amplifier (1), and when When the current source (Ip) composed of the NM〇S transistor is in the off-state φ state, the differential amplifier (1) is disabled to effectively reduce power consumption. The voltage peak detector of the controllable NM0S current source and output stage proposed by the present invention not only accurately detects the peak voltage of the input signal, but also has a simple circuit structure and a small number of transistors used. It is beneficial to multiple functions such as miniaturization of the device, and can also effectively reduce power consumption. [Embodiment] According to the above object, the present invention proposes a voltage peak detector with a controllable current source and an output stage, as shown in Fig. 6, which is composed of a differential amplifier and a charging battery. The crystal (2), a capacitor (C), an output stage (3), a control circuit (4) and a capacitor (c) are formed. The differential amplifier (1) includes a first PMOS transistor (MP1), a first _8 transistor 7, M335097 • j (MN1), a second NMOS transistor (MN2), and a NM〇s A current source (IP) composed of a transistor (MN), wherein the first NMOS transistor (MN1) and the second read 08 transistor (MN2) are used as a driver, the first PMOS transistor (MP1) is used as a single-sided load transistor, and the single-sided load transistor and the charging transistor (2) together constitute a current mirror, and the current source composed of the NMOS transistor (MN) IP) for providing a current for the differential amplifier, the gate of the _8 transistor (MN) is connected to the output of the control circuit (4), and is controlled by the control circuit (4) • to control the conduction ((5)) or off (off) state, when the nmos transistor (MN) is in the on state, a current can be supplied to the differential amplifier (1), and when the NMOS transistor ( When MN) is in the off state, the differential amplifier (1) is disabled. The gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) respectively receive an input signal (ν(ΪΝ)) and an output voltage feedback signal of the detector (V(OUT) )), the source is connected together 'and connected to the drain of the NMOS transistor (MN), and the pole is respectively connected to the drain of the first PMOS transistor (MP1) and the supply voltage (vdd) is connected; a gate of the NMOS transistor (MN) is connected to an output of the control circuit (4), and a pole is connected to the first nmos transistor (_〇 and the second NMOS) The source of the transistor (MN2), and the source is connected to the ground; the source of the first PMOS transistor (MP1) is connected to the power supply voltage (vdd), and the gate is connected to the drain to form a a diode connected to the drain of the first NMOS transistor (MN1). Referring again to FIG. 6, the charging transistor (2) is composed of a second PMOS transistor (MP2), the second The source of the transistor (MP2) is connected to the power supply voltage (vdd), and the gate is connected to the gate of the first PMOS transistor (^1) and the drain of the first NMOS transistor (MN1). Connected, while the bungee is connected to the electric climbing container (C) And the gate of the second NMOS transistor (MN2) is connected, wherein the first PMOS transistor (MP1) and the first PMOS transistor (MP2) form a current mirror configuration; further, the second The drain of the PMOS' crystal (MP2) is connected to one end of the capacitor, and the other end of the capacitor (c) is grounded; in addition, the output stage (3) is composed of an NMOS transistor (MN4) and a resistor (R). And composed of, connected between the power supply voltage (Vdd) and the ground. The control circuit (4) is composed of a first CMOS inverter (INV1) and a second CMOS inverter (INV2) connected in series. And receiving an input signal (V(IN)), and outputting a control signal for controlling whether the NMOS transistor (MN) is turned on or not, wherein the first CMOS inverter (INV1) is connected to the power supply voltage (Vdd) to drive, and the second CM 〇s inverter (_2) is stepped down by the first diode (D1) and the second diode (D2) connected in series by the power supply voltage (Vdd) Drive, it is worth noting here that 8 M335097 the number of diodes for step-down can be adjusted according to actual needs. When the NM〇S transistor (MN) is in the on state, a current can be supplied. Used by the differential amplifier (1), the differential amplifier 〇) and the voltage peak detector are both enabled; and when the NMOS transistor (MN) is off, the ban is disabled. The differential amplifier (1) and the voltage peak detector can be disabled, so that power consumption can be further reduced. For the sake of explanation, the following derivation process describes the gold oxide semi-transistor as the simplest model in 〇rCAD Pspice (ie, the levell model), regardless of the channel length modulation effect. However, in the subsequent simulation verification, all the crystal parameters in the 0rCADPspice (including the channel length modulation effect, of course) are considered. It is known from the circuit shown in FIG. 6 that when the input voltage signal v(IN) is greater than the output voltage signal v(〇UT) and the voltage peak detector is in an enable state, the first NMOS transistor (MN1) The drain current Id (MN1) is greater than the drain Id (_2) of the second NMOS transistor (MN2), wherein the current flowing into the transistor takes a positive sign, and the current flowing out of the transistor takes a negative sign, that is, , current Id (MN1) represents the no-pole current flowing into the first NMOS transistor (MN1), and _Id (MP1) represents the drain current flowing out of the first pm〇S transistor (MP1), and

Id (MN1) + Id (MN2) = IP (1) where IP is the current supplied by the NMOS transistor (MN),

Id (MN1) = -Id (MP1) (2) Since the first PMOS transistor (MP1) and the second PMOS transistor (Mp2) constitute a current mirror,

Id (MP1) /(^/1^) Delete = -Id (MP2) /(W/L)mp2 (3) where (W/L) mp^(W/L)MP2 represents the first PMOS transistor (MPi) and the effective channel length to length ratio of the second pmos transistor (MP2), so that the capacitor (c) can be charged. When the charging action reaches V(OUT) equal to the peak voltage of the input voltage signal (v(lN)), the current Id (MN1) / (wei) cis = Id (MN2) / (W / L) mn2 (4) where (W/L) circle and (wei) dirty respectively indicate the effective channel width-to-length ratio of the first os transistor (sho) and the second 〇8 transistor (MN2), and still the capacitor (c) Perform the charging action. However, according to the transfer characteristic curve of the differential amplifier, it is known that the output voltage signal ν(〇υτ) must be higher than the input peak voltage (ν_) over the -stitch voltage (〇vefSh(10) Cailin-Li〇8 transistor (MN1) forced When the first side of the 电8 transistor (MN1) is in the stopped state, the charging transistor stops charging the battery (c), and the output voltage signal ν(〇υτ) is M335097 (5). V(〇UT) = Vpeak + Vos Since the second NMOS transistor (MN2) operates in the saturation region at this time, and the first NMOS transistor (MN1) enters the cut-off region just from the saturation region, the following currents can be used. Equation for V〇S2 and VGS1: Id (MN2) = IP (6)

Id (MN1) = 〇 (7), so the excess voltage (Vos) is equal to

Vos = VGS2-VGS1 (8) VGS2 and VGS1 represent the gate-source voltages of the first NM〇S transistor (MN1) and the second NM〇s transistor (MN2), respectively. Thereafter, when the input voltage signal v (IN) falls down from the peak voltage (Vpeak), since the first NMOS transistor (MN1) has entered the off state, the current -Id (MP1) = -Id (MP2) =0 (9) Therefore, the charging transistor will no longer charge the capacitor (C), so the output voltage signal (V(OUT)) will remain fixed at the voltage of equation (5). It is known from equation (5) that the output voltage signal V(0UT) is always higher than the input peak voltage (Vpeak) by an excess voltage (Vos), and the excess voltage (Vos) is shown in equation (8). All _〇8 transistors have the same Zero-bias threshold voltage and the Tmnsconductance parameter, which is the zero-bias threshold voltage (ντο) and mutual conductance. The parameter (κρ) is a model parameter of the MOS semi-transistor, then the equation (8) can be rewritten as

Vos =[2·ΙΡ·1/ΚΡ-1/(W/L)mn2]1/2 (ίο) θ where (W/L)_2 represents the effective channel width of the second _8 transistor (MN2) For a long time, the derivation of the super 1 voltage Vos can be found in pages 357 to 375 of "Design of analog integrated circuits and systems" published by McGraw-Hill and by Willy R. Laker and Willy MC Sansen.再Refer to Fig. 6, the voltage v(c) on the capacitor is applied to the source voltage VGS4 between the surface of a transistor 8 and becomes the output voltage of the voltage peak detector (〇111). That is, V(OUT) = V(C) - VGS4 (11) Next, it is known from equations (5) and (11) that VGS4 = Vos is required to make the output voltage ν(〇υτ) equal to the input peak voltage Vpeak ' ^ (12) Finally, since the drain current Id (MN4) of the NMOS transistor (MN4) is the drain voltage 4 M335097 and the VD vertical function of the source, the output stage (3) is the successor. The channel width-to-length ratio (W/L) of the s transistor (mn4) and the resistance value of the resistor (R) must satisfy the following equation: (Vdd - VDS4) / r = Id(MN4) 》 by equation (10) ), (12) and (13) can easily design a voltage peak detector. (13) Next, how to reduce the power consumption of this creation, first compare the voltage peak detector of the Republic of China Announcement No. 1223081 shown in Figure 5 and the preferred implementation of the creation shown in Figure 6. For example, in the green technology of the fifth embodiment, the gate of the NMOS transistor _3 used to supply the current to the differential amplifier is connected to the power supply (Vdd), therefore, the MN间8 transistor_3) The source-source electric ship is equal to the power supply voltage (Vdd). In contrast, the NMOS transistor used to provide a current to the differential amplifier (1) is connected to the control circuit (4). The output of the control circuit (4) is provided with a diode (10) for bucking, and therefore, in the case where the transistor for supplying current to the differential amplifier (1) has the same effective channel width/length ratio. The function is to provide current to the 放大器8 transistor used by the differential amplifier (1) (the closed source voltage of Li^ is consistently provided in the prior art shown in Figure 5). The current is used by the differential amplifier (1) = 〇s The crystal _3) is very low, and the miscellaneous mine has a lower level than the fifth The lower power consumption of the previous technology, · Again, this creation considers that the electrical age value can be detected only when the specific conditions (such as the input voltage signal V ON) exceed the - county input voltage level) The mechanism, while the prior art of Figure 5 does not have a mechanism to enable the voltage peak detector only in certain situations, so this creation can further reduce power consumption. The simulation results of the voltage peak detector 2〇rCADpSpice proposed by Chunben Creation, such as the second, can be verified by the simulation results, and the controllable Lishao 8 current source and output proposed by the author The voltage peak detector of the stage can accurately detect the input signal - the control current source and output stage proposed by the author are only in the gorge condition (for example, the input county signal V (IN) The voltage peak detector is enabled when the input voltage signal (v(10)) is less than the predetermined input voltage level, and the voltage peak detector is disabled when the input voltage signal (v(10)) is less than the predetermined input voltage level. , wherein the predetermined input voltage level is mainly adjusted by the control circuit (4). Figure 8 shows the CADrCAD PSpice transient analysis simulation results of the voltage peak detector (previous skill) of the Republic of China Bulletin No. 1223081 and the present voltage peak detector, which can be confirmed by the simulation results. The pick-up value of the electric clerk is known to have a lower current consumption than the predecessor. 11 ^33$〇97 Switch value detection 11 in the (4) can be connected to the electricity c _ parallel connection - _, the peak of the wheel voltage signal, in order to discharge the charge stored on the electric grid 'for the next time [Sword effect] The following effects 7 kg proposed * controllable Li (10) current source and output, level voltage peak detector, with the use of 1 miscellaneous miniaturization: due to the voltage peak detection proposed by the creation The device does not need (2) high (four) Γ *, so it has the advantages of high integration and miniaturization of the device; ^ 度 · · The voltage peak detector proposed by this creation is confirmed by simulation results, it can be accurate Ground (3) is the input signal? The peak voltage of the tiger, so it also has the advantage of high precision; 氐 Power consumption·· The voltage peak detector proposed by this creation has voltage peak detection only when it has only certain conditions. The mechanism of enabling the device can effectively reduce the power consumption of the voltage peak detector. While the present invention has been particularly described and described, it is to be understood by those skilled in the art that the present invention may be modified in any form or detail without departing from the spirit and scope of the present invention. Therefore, all changes in the relevant technical scope are included in the scope of the patent application of this creation.

12 M335097 [Simple diagram of the diagram] The first diagram shows the circuit diagram of the voltage peak detector of the _ previous technique towel; the second diagram shows the input voltage signal and the output voltage signal of the voltage peak detector of the first diagram. State analysis timing diagram; Figure 3 shows the circuit diagram of the voltage peak detector in the second prior art; Figure 4 shows the transient analysis timing of the input voltage signal and the output voltage signal of the voltage peak detector in Fig. 3 Figure 5; Figure 5 shows the circuit diagram of the voltage peak detector of the rib coffee patent case in the Republic of China Announcement Case No., and Figure 6 shows the circuit diagram of the peak detection and subtraction of the embodiment of the creation book;

Example of the transient voltage analysis of the input voltage and output voltage; Figure 8 compares the transients of the voltage peak detector of the author and the voltage peak detector of the mth nickname patent case of the Republic of China Current analysis timing diagram. [Main component symbol description] 1 Differential amplifier 2 Charging transistor 3 Output stage 4 Control circuit D Diode D1 Diode D2 Diode ID (MN3) NMOS transistor MN3 drain current 0P1 Operational amplifier OP2 Operational amplifier MP1 first PMOS transistor MP2 second PMOS transistor MP3 third PMOS transistor MP4 fourth PMOS transistor MN1 first NMOS transistor MN2 second NMOS transistor MN3 third NMOS transistor MN NMOS transistor IP current source Vdd Power supply voltage R1 Resistor R2 Resistor V(IN) Input voltage signal V(OUT) Output voltage signal INV1 First CMOS inverter INV2 Second CMOS inverter C Capacitor ID (MN) NMOS transistor MN's drain current 13

Claims (1)

M335097 IX. Patent application scope: 1. A voltage peak detector with controllable _8 current source and output stage for detecting the peak value of the input signal, comprising: an input terminal for providing an input voltage a signal outputting a peak voltage of the input voltage signal; a power supply voltage (Vdd) for supplying a power supply voltage and a reference ground required by the voltage peak detector; a difference between the unilateral load transistors The dynamic amplifier (1) is configured to receive and compare the input voltage signal and the voltage signal on the capacitor, and provide a charging current signal to the charging transistor; a charging transistor (2) for using the differential amplifier (1) The amount of current flowing through the unilateral load transistor provides a charging current to the capacitor; 'an output stage (3) is connected between one of the terminals of the capacitor and the output of the voltage peak detector to adjust the capacitor ( C) a voltage signal for accurately outputting a peak voltage of the input voltage signal; a control circuit (4) for receiving the input voltage signal and controlling the differential amplifier (丨) system An on or off state; and a capacitor (C), one end of the capacitor is connected to the charging transistor (2) to receive the charging current supplied by the charging transistor (2), and the other end Then connected to the reference ground; wherein the differential amplifier (1) with a single-sided load transistor further comprises: a single-sided load transistor, which is composed of a first PMOS transistor (MP1), the first pm The source of the 〇S transistor (MP1) is connected to the power supply voltage (Vdd), the gate is connected to the drain, and is connected to the gate of the charging transistor (2); a first NMOS transistor (MN1), The source is connected to the source of the second _08 transistor (MN2), the gate is for receiving the input voltage signal, and the drain is connected to the gate of the charging transistor (2) and the first PMOS transistor ( The drain of the MP1) is connected; a second facet 8 transistor (MN2) whose source is connected to the source of the first nm〇s transistor (MN1), and the gate is used to receive the voltage signal on the capacitor. The drain is connected to a power supply voltage (vd(j); and a current source (IP), which is composed of an NMOS transistor (MN). a gate is connected to an output of the control circuit (4), and a gate is connected to the first N]y [the source of the Qs transistor and the source of the second NMOS transistor (MN2), and the source is The control circuit (4) further includes a first CMOS inverter (INV1) and a second CMOS inverted M335097 (INY2), the first CMOS inverter (INV1) and the second CMOS inverter The device (INV2) is connected in series, and the first CMOS inverter (INV1) is driven by the power supply voltage (Vdd), and the second CMOS inverter (INV2) is connected to the power supply voltage (Vdd). After a series of diodes (D2) in series, the voltage is driven down. 2. A voltage peak detector having a controllable NMOS current source and an output stage as described in claim 1, wherein the charging transistor (2) is composed of a second PMOS transistor (MP2). The source of the second PMOS transistor (MP2) is connected to the power supply voltage (Vdd), and the gate is connected to the gate of the first PMOS transistor (MP1) and the drain of the first NMOS transistor (MN1). The drain is connected to one end of the capacitor and the gate of the second NM〇S transistor (MN2). 3. The voltage peak of the controllable NM〇S current source and output stage as described in claim 1 of the patent application, the detector further includes: a switch, the open relationship is connected in parallel with the capacitor, A discharge path is provided to discharge the remaining charge on the battery, facilitating the detection of the value of the next input voltage signal. 4. A voltage peak detector having a controllable nM〇s current source and an output stage as described in claim 3, wherein the open relationship consists of a MOS transistor. 15