TW517161B - Voltage peak detector - Google Patents

Abstract

The present invention proposes a kind of voltage peak detector that is composed of a differential amplifier, a current mirror and a capacitor. Both input terminals of the differential amplifier receive input voltage signal and output voltage feedback signal of the detector, respectively, and provide appropriate charging current for the current mirror to obtain peak value of the input voltage waveform for use as the output voltage signal. The differential amplifier is used as a comparator and the current mirror is used as a charger. The voltage peak detector proposed by the invention has not only new and simple circuit scheme, but also can precisely detect the peak value of the input voltage waveform.

Description

517161 V. Description of the invention (l) [Field of the invention] The present invention relates to a voltage peak detector 'especially by using a differential ampl if ier and a current mirror to Complementary metal-oxide-semiconductor (CMOS) electronic circuits for obtaining accurate voltage values. [Background of the Invention] The voltage peak detector is an electronic circuit that can measure the maximum value of a voltage waveform. In other words, the input of the circuit is a variable voltage signal and its output is the maximum of the input voltage waveform. value. Reference In many applications, the peak value of the input voltage signal must be measured, and then it is retained as a direct current type for subsequent analysis and use. The burst peak of a pulse train is often more useful than its average value. For example, when performing a destructive test, it is necessary to track down and maintain the peak signal, and the spectrum and mass spectrometer are also used. Voltage peak detector. In the prior art, the simplest method of the voltage peak detector is to pass the input voltage signal through the diode and charge the capacitor to obtain the peak value of the input voltage waveform. As shown in the first figure, when the input voltage V (IN) is greater than the voltage _ of the capacitor C, the diode D is turned on, and the charging function is performed until the input voltage V (IN) reaches its maximum value, and the capacitor C cannot continue to charge. At this time, the output voltage ν (ουτ) represents the peak value of the wheel-in voltage ν (ΙΝ). Because of the diode [) between the output and input, this circuit cannot

517161 V. Description of the invention (2) The true peak value of the input voltage V (IN) is accurately detected. In other words, there will always be an error between the diode turn-on voltage Vd between the output voltage V (OUT) and the peak of the input voltage v (IN). That is, MAX (v (〇UT)) = MAX (v (iN))-Vcl, as shown in the second figure (this figure is the simulation result of OrCAD PSpice transient analysis). For many applications, the above-mentioned error in the diode on-voltage Vd is undesirable, and the voltage difference may be different due to the use of different diodes, which may cause adverse effects or unpredictable consequences. In order to be able to accurately detect the value of the input voltage, another commonly used prior art system uses two operational amplifiers 〇ρι and 〇132, two diodes D1 and D2, two resistors R1 and ^, and A capacitor ^ is used to form a voltage peak detector, as shown in the third figure, and its OrCAD PSpice temporary I, knife analysis simulation results are shown in the fourth figure. Among them, OP 1 is an accurate half-wave rectifier. When the input voltage V (丨 N) is greater than the capacitor voltage y (C), the diode D1 will charge the capacitor C1 with the transmission bias voltage, and finally the capacitor voltage V (C) Will be quite close to the peak voltage of the input voltage V (IN), and the output voltage v (OUT) of the detected 2 will also be close to the peak voltage of the input voltage V (IN). It will no longer be as shown in the second figure. There is an error between the diode-on voltage Vd between the output terminal and the input terminal. And when the input voltage eight IN) is less than the capacitor voltage V (C), the diode]) 2 will be turned on, and the diode 〇1 will be cut off_ The action of charging the capacitor C will make the detected output The voltage ν (ουτ) will be equal to the peak voltage of the input voltage V (IN). Although the voltage peak detector in the third figure can accurately detect the peak voltage, the complex circuit structure and the large chip area occupied are not conducive to the integration of integrated circuits.

Page 5 517161 V. Description of the invention (3) One 'one' ~-one request. ^ His known voltage peak detectors, such as those disclosed in U.S. Patent Nos. 5,304,939,554602Y and 5,969,545, all make = op amps likewise have complex circuit structures and large chip areas. In view of this, the main object of the present invention is to propose a novel voltage peak detector, which can not only accurately detect the peak voltage, but also has multiple functions such as simple circuit structure and small chip area. ,

[Explanation of the embodiment of the invention] According to the above purpose, the present invention proposes a novel voltage peak detector, as shown in the fifth figure, which is composed of a differential amplifier i, a current mirror 2 and a capacitor C. . The two input terminals of the differential amplifier i respectively receive the input voltage signal V (IN) and the output voltage feedback signal v (OUT) of the detector and provide an appropriate charging current to the current mirror 2 in order to obtain the input voltage waveform. The peak value is used as the output voltage signal. Among them, the differential amplifier is used as a comparator, and the current mirror is used as a charger.

Referring to the fifth figure, the differential amplifier 1 is composed of PMMOS transistors MP1 and MP2, and NMOS transistors MN1, MN2, and MN3. Among them, the NMOS transistor MN1 and MN2 are used as drivers, the PMMOS transistor MP1 and MP2 are used as active loads, and the NMOS transistor MN3 provides a reference current. Give this differential amplifier! use. The gates of the NM0S transistors MN1 and MN2 respectively receive the input voltage signal V (IN) and the output voltage feedback signal ν (〇υτ) of the detector.

Page 6 517161 V. Description of the invention (4) (source) is connected together and connected to the drain of NM0S transistor MN3, and its drain is connected to the drains of pMOS transistors MP1 and Mp2 respectively ; The gate of the NM0S transistor MN3 is connected to the power supply voltage vdd 'and the source is grounded; the source of the PM0S transistor MP1 and MP2 are connected to the power supply voltage Vdd' and the gates are connected together, and the ? The gate of the transistor MP2 and the drain of || are connected together to form a current mirror configuration. Please refer to the fifth figure again, the current mirror system is composed of pM0S transistor MP3 and MFM. Among them, the PU0S transistor MP3 and secret? The source of 4 is connected to the power supply voltage Vdd, and the gates are connected together and connected to the drain of the NM0s transistor _body MN1, and the gate and drain of the p || 0s transistor Mp3 The poles are connected together 'to form a current mirror configuration; furthermore, the drain of the PM0s transistor Mp4 is connected to one end of the capacitor c and forms an output, and the other end of the capacitor [is connected to ground . ^ According to the circuit shown in the fifth figure, when the input voltage V (IN) is greater than the capacitor 2 voltage V (c), the current Id (MN1) will be greater than -I (i (MP2), where ^ the current into the transistor Take a positive sign, and the current flowing out of the transistor is negative. 5 Here, the current Id (MN1) represents the current flowing into the drain of the Guantong transistor, and -Id (MP2) represents the drain flowing out of the PM0S transistor MP2. Current of the pole. And g-Id (MP1) = Η (MP2) ⑴ so-Id (MP3) = Id (MN1)-[-Id (MP1)] (2) (3) -Id (MP3) > 〇

517161 V. Description of the invention (5) And the transistors MP3 and MP4 are also rabbits. _ Is a thunder made of PMOS transistors; = 'Two terminals 1d (MP3)> 0, the current is specialized to -d (MPJ ), So the capacitor c is charged until VCOUT (that is, v (c)) is equal to the peak voltage of the wheel-in voltage V (IN). When the charging action reaches v (0UT) equal to the input voltage V (I voltage, due to the role of the differential amplifier, the current beeps -Id (MP1) = -id (MP2) = Id (MN1 so the current ^; -Id ( MP3) = -Id (MP4) = 〇⑸ So no longer charge the capacitor, so the vcout) will be equal to the peak voltage of the input voltage V (IN). When the output voltage is less than the input voltage v (IN), When the capacitor voltage is v (c), the transistor MP3 will be in the cut-off region, and the current 'Id (MP3) = -Id (MP4) = 〇 (6) Therefore, the capacitor will not be charged, so the detected output The voltage V (OUT) will still be maintained at the peak voltage of the input voltage v (IN). The 0rcAD pspice transient analysis simulation result of the voltage peak detector proposed by the present invention is shown in the sixth figure. It can be accurate and effective The peak voltage of the input voltage waveform is detected. The voltage peak detector of the present invention can be connected in parallel with a switch at both ends of the capacitor when in use. The open relationship is used to provide a discharge path in order to store The discharge of electric charge is conducive to the peak detection of the next input voltage signal. 7161 Description of the invention (6) [Effect of the invention] The voltage peak detector proposed by the present invention uses only 4 pM0s electric solar cells = 3 NMOS transistors and 1 capacitor, which not only has a novel circuit architecture, It is simple, uses a small number of transistors, and occupies a small area of the chip. Ϊ́ t can accurately detect the peak value of the input voltage waveform; at the same time, because this voltage peak detection 11 does not use an operational amplifier, it also has ~ Miniaturization of the device. Ju Fanlu described the preferred embodiment selected, but the changes did not make clear what form or details within the scope of possible changes ^ God and the garden. Therefore, all relevant technical documents are It is included in the scope of patent of the present invention. 517161 Brief description of the diagram The first diagram shows the circuit diagram of the voltage peak detector in the first prior art; the second diagram shows the input voltage of the voltage peak detector in the first diagram Signal and output voltage signal transient analysis timing diagram; the third diagram shows the circuit diagram of the voltage peak detector in the second prior art; the fourth diagram shows the third diagram of the voltage peak detector Timing chart of transient analysis of input voltage signal and output voltage signal; the fifth diagram is a circuit diagram showing a voltage peak detector of the preferred embodiment of the present invention, and the sixth diagram is an input voltage signal of the voltage peak detector of the present invention And transient analysis timing diagram of output voltage signal. MN3 NMOS transistor

Page 10 [Description of Symbols] 1 Differential Amplifier 2 Current Mirror C Capacitor D Diode D1 Diode D2 Diode R1 Resistor R2 Resistor OP1 Operational Amplifier OP2 Operational Amplifier MP1 PMOS Transistor MP2 PMOS Transistor MP3 PMOS transistor MP4 PMOS transistor MN1 NMOS transistor MN2 NMOS transistor

A

Claims (1)

M7161 VI. Patent application scope '^-1 · A voltage peak detector for detecting the peak of an input voltage signal includes: an input terminal for providing an input voltage signal;-a wheel-out terminal' for a wheel-out The peak voltage of the input voltage signal; The power supply voltage is used to provide the electrical voltage and reference ground required by the voltage peak detector; a differential amplifier is used to receive the wheel-in voltage signal and the output t-pressure signal at the output 'And provide a charging current signal to the current mirror; ^ a current mirror' is used to provide a charging current to the capacitor according to the charging current signal provided by the differential amplifier; and a valley device 'one end of the capacitor is connected to a reference ground, The other end is connected to the current mirror to receive the charging current supplied by the current mirror. 2 · The voltage peak detector as described in item 丨 of the patent application scope, which further includes: ^ a switch, the open relationship is connected in parallel with the capacitor to provide an electrical path to charge stored in the capacitor Discharge, peak detection of the input voltage signal. Bu The voltage-on relationship as described in item 2 of the patent application scope is composed of a metal-oxide semiconductor transistor. The voltage differential amplifier as described in item 1 of the patent application scope includes: a peak detector, a peak detector, wherein, Where the Gates of the first PMOS transistor and the second PMOS transistor MP2 ::: to: source voltage 'gate current mirror and the first NMOS transistor MN1, and 炻 2 * The drain is connected to the electric and electrode ; 517161 Sixth, the scope of patent application ~~~ One ~--The second rigid transistor MP2, whose source is connected to the power supply voltage = connected together, and connected to the first 'electrode' gate of the first EEG crystal, and The drain is also 篦 -M. &-^ -NMOS t .¾ ^ MNl 1 ^ ^ ^ ^ ^ 1 The source and the second NM 0 S transistor 髀 mw 9 — the source and the third _transistor MN3 electricity = 2 of = input voltage Signal, and the drain is connected to the drain of the electric / mirror connection and the transistor MP1. The source of Le FM0S and the drain of the second NMOS transistor MN3 are connected. The gate accepts the output voltage of the output terminal 0 to The pole of the PM0S transistor MP2: the serial number, and the drain is connected to the second: ί: Ν = | Body: 3, its source is connected to the reference ground, and the gate MM is connected to the source The pole is connected with the first and second transistor 5. The lightning current mirror according to item 1 of the scope of patent application includes: a voltage peak detector of this, wherein the third PM0S transistor MP3 is a straight source. ", Φ 枝" is connected to the drain and connected to a fourth PM0S transistor MP4, the source of which is to amplify the β output, and the gate of the third PM0S transistor MP3 is connected to the power supply voltage. t σ ^ is connected to the idler pole, while the drain is connected to the capacitor and the gate of the second NMOS transistor dark 2 ...,