1301894 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種電壓峰值檢知器，尤指利用一差動放大器、一電流 鏡、一控制電晶體、以及一電容器所組成以求獲得精確電壓峰值且具有低 功率消耗之互補式金氧半（CMOS)電子電路。 【先前技術】 電G峰值核知器係一種電子電路，能夠測得一電壓波形之最大值，質 a之，邊電路之輸入為一變動之電壓信號，而其輸出則是該輸入電壓波 之最大值。 在弁多應用中，輸入電壓信號之峰值必須被測出，然後將之以直流電 型悲保留住以便後續分析、使用。一個脈衝串之尖峰值常比它的平均值要 ^有用’例如當執行破壞性測試時，就有必要追尋出並保持峰健號，而 ，測電壓錢在傳輸齡上之衰減量、類比錄位轉換別趟⑺·^)、 最大近似解碼祕(maximum likdihGGd deeQding辦㈣以及用以檢測核輕 射之脈衝信號檢測電路等也需要用到電壓峰值檢知器。 …先前技藝(prior art)中，電壓峰值檢知器之最簡單作法係令輸入電壓信 號通過二極體，而對電容充電，以便取得該輸人電壓波形之峰值。 、如第一圖所示，當輸人電壓V(IN)大於電容器C之電壓時，二極體D導 通，遂行充電作用’直到輸入賴v㈣到達其最大值，電容凯不能 再繼績充電，此時輸出電壓V(〇UT)即表示輸人tMv(lN)之蜂值。 由於輸出端與輸入端之間存在二極體D，此電路無法精確地檢得輸入電 [V(IN)之真正峰值。換吕之，輪出電壓ν(〇υτ)與輸人電塵V(IN)之聲值 間永遠存在二極體導通電壓Vd之誤差。亦即 之 ’如第二_示咖係隐d 暫態分析模擬結果）。 並且^，上述二極體導通電壓Vd之誤差係不欲見到的， 以電£^因為使用不同之二極體而有所差異，可 或不可預測之後果。 〜曰 1301894 為了能夠精雜檢職人之雜，另—種相之先 了由二個運算放大器〇P1和嫩、二個二極體m邱2、二個電‘f用 R2'以及-個電容HC來構成-電壓峰值檢知器，如第三騎示，& = PSpice之暫態分析模擬結果，如第四騎示。其中，〇ρι是—赚 波整流器，當輸入電壓_)大於電容電壓v(c)時，二極體⑽傳^偏= 電容器α進彳了充電，最後電容賴v(c)將會與輸人輯V(IN)之峰 相當接近’所檢測出的輸出電壓ν(ουτ)也會與輸人電壓卿) = 當接近’不會再有如第二圖所示於輸出端與輸入端之間存在一二極體^ 電壓Vd之誤差。而當輸人賴ν㈣小於電容電 ^ = 會導通，二極體轉會截止而不再對電容器c 行充2；^= θ 檢測出的輸出電壓ν(ουτ)會等於輸人電壓V(IN)之峰值電壓。雖戈第 電壓峰值檢知II能精確地檢測峰值輕，但其電路結構複雜= 片面積大，實不利於積體電路之要求。 用的曰曰 迄今’有許多電壓峰值檢知器之技術被提出，例如 US5304939 ^ 5502746 ^ 5546027 ^ 5969545 ^ 6051998 ^ 6064238 ,： 64^28^Γ , 以及中華民國專利案公告案號第476418號 ^ 5儿 精確地檢職人錢之餐龍，但，技術均能 :以=運算放大器，因此存在有電路結構複雜^ 提出，例如中華民_案公支術被 示）、第號、第助_、第_9 ==五圖所 -電流鏡所組成的電路來取代運曾^ 2出、係以一差動放大器和 因此，具備電路結構簡單、二於並不使用到運算放大器， 多重功效。然而，該等技術綠▲、、以及有利於裝置之小型化等 有改良空間存在。 ，、思5如何減少功率消耗之問題，因此仍 為了減少精密電壓峰值檢知器之功 、， 公告案號第M276200號厂呈低功率、—j耗，本申❻人曹提出中華民國 /、-力率肩耗之電壓峰值檢知器」專利案，主要 1301894 • 代表圖如第六圖所示，其係藉由連接在輸入信號V(IN)以及作為一電流源且 • 用2提供一電流給差動放大器1使用之MOS電晶體(MN3)之閘極間的控制 電曰曰體3，以便隨著輸入信號V(IN)之電壓位準，而動態控制該作為一電流 • 源使用之M0S電晶體之汲極電流，俾減少功率消耗。然而，該技術須增$ 一控制電晶體3，因此仍有改良空間存在。 的有鑑於此，本發明之主要目的係提出一種新穎架構之電壓峰值檢知 器，其不但不需增設一控制電晶體，並且能精確且快速地檢測出輸入信號 之峰值電壓，同時可較先前之電壓峰值檢知器具有更低之功率消耗。 % 【發明内容】 本發明提出一種具PM〇s電流源之峰值檢知器，其係由一差動放大器1、 :電流鏡2、以及一電容器c所組成，其中，該差動放大器丨係做為比較 的使用其兩輪入端係分別接受輸入信號v(in)及檢知器之輸出電壓回授信 说ν(ουτ) ’並提供適當之充電電流給電流鏡2，以便取得輸入信號v(in) =峰值做為輸出電壓信號，而該電流鏡2係作為充電器使用，用以提供電 各°°匚所品之充電電流’該差動放大器1係由第一 pm〇S電晶體MP1、第 一 PMOS電晶體MP2、第一 NMOS電晶體MN卜第二NM〇s電晶體MN2 以及PMOS電流源ip所組成，其中，該第一 電晶體^丨和第二 魯 NMOS電阳體MN2係做為驅動器(driver)使用，該第一 pm〇s電晶體MP1 和第一 PMOS電晶體MP2係做為主動負載(active load)使用，而該PMOS 電飢源IP則作為一電流源使用且設計成二極體形式，以便提供一電流給該 差動放大器1使用。本發明所提出之電壓峰值檢知器，不但能精確地檢測 出輸入信號之峰值電壓，並且也能有效地減少功率消耗。 【實施方式】 根據上述之目的，本發明提出一種具pM〇s電流源之峰值檢知器，如第 七圖所不，其係由一差動放大器1、一電流鏡2、以及一電容器c所組成。該 差動放大器1係由第一PM0S電晶體^^?1、第二pM〇s電晶體Mp2、第一 NM0S電晶體MNi、第二電晶體mn2以及pM〇s電流源Ip所組成，其 1301894 • 中，該第—NM0S電晶體MNl和第二NMOS電晶體MN2係做為驅動器(driver) - 使用’该第一PM0S電晶體MP1和第二PMOS電晶體MP2係做為主動負載 •_^1(^)使用，而該刚〇8電流源1]?係由一讀〇3電晶體所組成且設計成 • 二極體形式，以便提供一電流給該差動放大器1使用。 該第一NMOS電晶體MN1和第二丽08電晶體丽2之閘極(gate)係分別 接文輸入信號V(IN)及檢知器之輸出電壓回授信號ν(〇υτ)，源極(s〇urce)連 接在一起，並連接至PMOS電流源IP之源極(s〇urce)，而其汲極則分別與第一 PM0S電晶體MP1和第二舰08電晶體碰此及極相連接；該pM〇s電流源 IP係由一PMOS電晶體所組成，其閘極與汲極連接在一起以形成一二極體， Φ 並連接至接地，而源極則連接至該第一NM0S電晶體MN1和該第二_〇3 電晶體MN2之源極；言亥第—PM〇s電晶體刪和第二pM〇s電晶體跑之源 極均連接至電源電壓Vdd，而閘極則連接在一起，且該第二PM〇S電晶體嫩2 之閘極與汲極係連接在一起，以形成一電流鏡組態。1301894 IX. Description of the Invention: [Technical Field] The present invention relates to a voltage peak detector, and more particularly to a precision amplifier, a current mirror, a control transistor, and a capacitor for obtaining accuracy Complementary metal oxide half (CMOS) electronic circuits with voltage peaks and low power consumption. [Prior Art] An electric G peak nucleus is an electronic circuit capable of measuring the maximum value of a voltage waveform. The input of the side circuit is a varying voltage signal, and the output is the input voltage wave. Maximum value. In many applications, the peak value of the input voltage signal must be measured and then retained in DC mode for subsequent analysis and use. The peak value of a burst is often more useful than its average value. For example, when performing a destructive test, it is necessary to trace and maintain the peak health, and measure the attenuation of voltage on the transmission age, analogy Bit conversion (趟)(^)·^), maximum approximate decoding secret (maximum likdihGGd deeQding (4), and pulse signal detection circuit for detecting nuclear light shots, etc. also need to use voltage peak detector. ... prior art (prior art) The simplest method of the voltage peak detector is to pass the input voltage signal through the diode and charge the capacitor to obtain the peak value of the input voltage waveform. As shown in the first figure, when the input voltage V (IN) When the voltage is higher than the voltage of the capacitor C, the diode D is turned on, and the charging function is performed until the input 赖v(4) reaches its maximum value, and the capacitor kai can no longer be charged. At this time, the output voltage V(〇UT) indicates that the input is tMv ( lN) The value of the bee. Since there is a diode D between the output and the input, this circuit cannot accurately detect the true peak value of the input [V(IN). For Lu, the voltage ν(〇υτ) Forever with the sound value of the input electric dust V (IN) In the diode conduction voltage Vd of the error. The i.e. '_ The second line shows coffee d implicit transient analysis simulation results). And ^, the error of the above-mentioned diode on-voltage Vd is undesired, and it may be different or not unpredictable because of the difference in the use of different diodes. ~曰1301894 In order to be able to miscellaneous inspectors, another kind of phase first consists of two operational amplifiers 〇P1 and tender, two diodes m 2, two electric 'f with R2' and a capacitor HC is used to form a voltage peak detector, such as the third rider, & = PSpice transient analysis simulation results, such as the fourth ride. Where 〇ρι is - earning wave rectifier, when the input voltage _) is greater than the capacitor voltage v(c), the diode (10) transmits the bias = the capacitor α enters the charging, and finally the capacitor depends on v(c) The peak of V(IN) is quite close to 'the detected output voltage ν(ουτ) will also be the same as the input voltage =) When it is close to 'there will no longer be between the output and the input as shown in the second figure. There is an error of a diode ^ voltage Vd. When the input 赖ν(4) is smaller than the capacitance ^^ will turn on, the diode transfer will be cut off and the capacitor c will not be charged 2; ^= θ The detected output voltage ν(ουτ) will be equal to the input voltage V(IN) The peak voltage of ). Although the Gaudí Peak Voltage Detection II can accurately detect the peak value, its circuit structure is complicated = the chip area is large, which is not conducive to the requirements of the integrated circuit. The technique used by ' so far has been proposed, for example, US 5304939 ^ 5502746 ^ 5546027 ^ 5969545 ^ 6051998 ^ 6064238 , : 64^28^Γ , and the Republic of China Patent Case No. 476418 ^ 5 children accurately inspect the money of the food dragon, but the technology can: = operational amplifier, so there is a complex circuit structure ^ proposed, for example, the Chinese people _ case public surgery is shown), the number, the first aid _, The _9 == five maps - the circuit composed of the current mirror to replace the Yun 2 ^, with a differential amplifier and therefore, with a simple circuit structure, two without using an operational amplifier, multiple functions. However, there is an improved space for such technologies, green, and miniaturization of devices. , , think 5 how to reduce the problem of power consumption, so in order to reduce the power of the precision voltage peak detector, the bulletin No. M276200 plant has low power, -j consumption, the applicant Shen Cao proposed the Republic of China /, - The voltage peak detector for power shoulder consumption" patent case, main 1301894 • The representative figure is shown in the sixth figure, which is connected by the input signal V(IN) and as a current source and The current is supplied to the control electrode 3 between the gates of the MOS transistor (MN3) used by the differential amplifier 1 to dynamically control the use as a current source according to the voltage level of the input signal V(IN). The drain current of the MOS transistor reduces power consumption. However, this technique requires an increase of $1 to control the transistor 3, so there is still room for improvement. In view of this, the main object of the present invention is to provide a novel structure voltage peak detector which not only does not need to add a control transistor, but also can accurately and quickly detect the peak voltage of the input signal, and can be compared with the previous one. The voltage peak detector has lower power consumption. [Invention] The present invention provides a peak detector with a PM〇s current source, which is composed of a differential amplifier 1, a current mirror 2, and a capacitor c, wherein the differential amplifier is For comparison, the two-input terminal receives the input signal v(in) and the output voltage of the detector, respectively, and returns the current to the current mirror 2 to obtain the input signal v. (in) = the peak value is used as the output voltage signal, and the current mirror 2 is used as a charger to supply the charging current of the electric product. The differential amplifier 1 is composed of the first pm 〇S transistor. The MP1, the first PMOS transistor MP2, the first NMOS transistor MN, the second NM〇s transistor MN2, and the PMOS current source ip, wherein the first transistor and the second NMOS transistor MN2 Used as a driver, the first pm〇s transistor MP1 and the first PMOS transistor MP2 are used as active loads, and the PMOS electrical source IP is used as a current source. Designed in the form of a diode to provide a current to the differential amplifier 1 use. The voltage peak detector proposed by the present invention not only accurately detects the peak voltage of the input signal, but also effectively reduces power consumption. [Embodiment] According to the above object, the present invention provides a peak detector with a current source of pM〇s, as shown in the seventh figure, which is composed of a differential amplifier 1, a current mirror 2, and a capacitor c. Composed of. The differential amplifier 1 is composed of a first PMOS transistor, a second pM 〇s transistor Mp2, a first NMOS transistor MNi, a second transistor mn2, and a pM 〇s current source Ip, which is 1301894 • In the middle, the first-NM0S transistor MN1 and the second NMOS transistor MN2 are used as drivers - using the first PMOS transistor MP1 and the second PMOS transistor MP2 as active loads • _^1 (^) is used, and the 〇8 current source 1] is composed of a read 〇3 transistor and is designed in the form of a diode to provide a current for the differential amplifier 1. The gates of the first NMOS transistor MN1 and the second NMOS transistor 2 are respectively connected to the input signal V(IN) and the output voltage feedback signal ν(〇υτ) of the detector, the source (s〇urce) are connected together and connected to the source of the PMOS current source IP (s〇urce), and the drains thereof are respectively in contact with the first PM0S transistor MP1 and the second ship 08 transistor. The pM〇s current source IP is composed of a PMOS transistor, the gate is connected to the drain to form a diode, Φ is connected to the ground, and the source is connected to the first NM0S The source of the transistor MN1 and the second _3 transistor MN2; the source of the MIMO-PM〇s transistor and the source of the second pM〇s transistor are connected to the power supply voltage Vdd, and the gate is Connected together, and the gate of the second PM〇S transistor is connected to the drain to form a current mirror configuration.
• ,晴再芩考第七圖，該電流鏡2係由第三PMOS電晶體MP3和第四PMOS • f晶體MP4所組成。其中，該第SPMOS電晶體MP3和第四PMOS電晶體MP4 之源極均連接至電源電壓Vdd，而閘極則連接在―起，並連接至第―副^ 電晶體MN1之沒極，且該第三PM〇S電晶體Mp3之間極與没極係連接在一 起’以形成-電流鏡組態；再者，第四刚〇8電晶體·4之没極係與電容器 C之-端連接，並形成該電壓峰值檢知器之輸出端，而該電容器。之另一端 攀則接地。 為了便於制起見’町之推導棘，均將金氧半電晶體以〇rCAD PSpice中之最簡單_來贿，且科慮通道長度輕(ehannd㈣h m〇dulation)效應。但於後續之模擬驗證時，貝恃慮了吻以中之所有電晶 體參數(當然包括通道長度調變效應）。 由第七圖所示電路得知，當輸入信號V(IN)大於電容電壓V(C)時，電流 Id (MN1)會大於-id (MP2)，其中，流入電晶體之電流取正號，而流出 電晶體之電流則取負號，亦即，電流Id(MN1)代表流入第一難⑽電晶體 MN1之;及極i抓，而-Id(MP2)則代表流出帛二PM〇s電晶體Mp2之汲極電 1301894 (1) ⑵ (3) -Id ( MP1 ) = -Id ( MP2 ) 所以 -Id (MP3) = Id (MNl) _[_id (MP1) -Id (MP3) > 0 曰而第三PMOS電晶體MP3、第四PM〇s電晶體綱也係為一由雨⑽ =體所組成的電流鏡組態，所吟Id (Mp3) > ◦時，電流(Mp4)會 ^\(ΜΡ3) ^而可對電容器C進行充電動作，直到V(〇UT)(也就是 ())專於輸入#號V(IN)的峰值電壓為止。 動作達到ν(〇υτ)等於輸二號聊的峰值電壓時，由於差動放 大為之作用，電流 ⑷ -Id (MP1) =-Id (MP2) = id (MN1) 所以電流 ⑸ -Id (MP3) =-Id (MP4) =〇 會等=====作，所爾__ _賴 處於=輸：細)小於輪幢v(c)時’第三咖電晶_將 -Id(MP3)=-Id(MP4)=〇 ⑹ 精確地檢_輸人信號之峰值龍。"本W所Μ之龍峰值檢知器能 接下來說明本發明如何減少功率消耗，首先比較 公告案號第517161號專利案之電屢峰值檢知器盘第:中華民國 實施例’由於在第五圖所示之先前技藝中，用以接:法不之本發明較佳 使用之第三NM〇S電晶體議3之_恆連接至電源電 1301894 第二NMOS電晶體MN3的閘源極電壓怪等於電源電壓vdd，反觀本發明 - 用以提供一電流給差動放大器1使用之PMOS電流源ip係由一 PM0S電晶 體所組成且設計成二極體形式，亦即將作為PM〇s電流源Ip使用之該 . PM0S電晶體的閘極與沒極連接在-起，並連接至接地，因此，本發明作 為PMOS電流源IP使用之該PM0S電晶體閘源極電壓％啊的絕對值怪小 於第五圖所枕該第三NMOS電晶體刪__霞；再者，本發明 用以提供-電流給差動放大器1使用之PM〇s電流源lp係由一 pM〇s電晶 體所組成，而第五騎示絲技藝用以提供—電流給差減大器丨使用之 第三NMOS電晶體MN3係由- NM〇s電晶體所組成，由於pM〇s電晶體 • 之互導參數呵transconductance Parameter)通常小於nm〇s電晶體之互導 參數(互導參數KP表示OrCAD pspice中之一金氧半電晶體模型參數），因 此在用以提供電流給差動放大g丨使狀電晶體具有侧的有效通道寬度/ 長度比值的情況下，本發日雅較第五圖所示之先前技藝具有更低之功率消 • 耗。 • 接著比較第六圖所示之中華民國公告案號第助62〇〇號專利案之電壓 峰值檢知ϋ與第七®所示之本發明較佳實施例，由於在第六圖所示之先前 技藝中:用以提供-電流給差動放大器i使用之第三觀〇8電晶體咖 之閘極係連接至控制電晶體3之輸出端，該控制電晶體3係設計成二極體 ^式·1*連接在電壓峰值檢知器輸人端·與第三NMQS電晶體MN3閘極之 間，由於該控制電晶體3並沒有汲極電流流過，@此，用以提供一電流仏 差動放大器i使用之第三顺0S電晶體刪之間源極電壓Vgs(_)係等;; VGS3(_3)二 V(IN) - ντ(控制糖） ⑺ ^其中Vt(㈣電係表示控制電晶體3之臨界電壓(threshold voltage)。反 觀’本發明於電容器充電過程中’由於㈣提供—電流給差動放大器i使 用之PMOS電流源ΠΜ系由-PM0S電晶體所組成且設計成二極體形式，因 此該mos電晶體之閘源極電壓Vg啊的絕對值係等於第一 nm〇s電曰 體MN1之源極電壓，亦即 _ 10 1301894 I VGS(iP) I = V(IN)-VT(MNir [2 · Id (MN1 ) · L/(KP · W)]1/2 ⑻ 其中’ Vtxmnd表示第一 電晶體μμ之臨限電壓，w和l分別表 示該第一 NM0S電晶體麵之有效通道寬度及有效通道長度，而KP則表 不OrCADPspce中之一金氧半電晶體模型參數。比較方程式(乃與(8)可推知• In the seventh picture, the current mirror 2 is composed of a third PMOS transistor MP3 and a fourth PMOS•f crystal MP4. The source of the SPMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the power supply voltage Vdd, and the gate is connected to the gate, and is connected to the pole of the first-side transistor MN1, and the gate The third PM〇S transistor Mp3 is connected to the poleless pole to form a current mirror configuration; further, the fourth rigid tantalum 8 transistor 4 has a junction with the capacitor C And forming the output of the voltage peak detector, and the capacitor. The other end of the climb is grounded. In order to facilitate the discovery of the thorns of the 'machi, the gold-oxygen semi-transistor is the simplest of the 〇rCAD PSpice, and the length of the channel is light (ehannd (four) h m〇dulation) effect. However, in the subsequent simulation verification, Bellows considered all the crystal crystal parameters in the kiss (including, of course, the channel length modulation effect). It is known from the circuit shown in FIG. 7 that when the input signal V(IN) is greater than the capacitor voltage V(C), the current Id (MN1) is greater than -id (MP2), wherein the current flowing into the transistor takes a positive sign. The current flowing out of the transistor is taken as a negative sign, that is, the current Id(MN1) represents the first difficult (10) transistor MN1; and the Id (MP2) represents the outgoing PM2s. M 130 130 1301894 (1) (2) (3) -Id ( MP1 ) = -Id ( MP2 ) So -Id (MP3) = Id (MNl) _[_id (MP1) -Id (MP3) > 0 The third PMOS transistor MP3 and the fourth PM 〇s transistor are also configured as a current mirror composed of rain (10) = body, and 吟 (Mp3) > ◦, current (Mp4) ^\(ΜΡ3) ^ Capacitor C can be charged until V(〇UT) (that is, ()) is dedicated to the peak voltage of ##V(IN). When the action reaches ν(〇υτ) equal to the peak voltage of the second number, because the differential amplification works, the current (4) -Id (MP1) = -Id (MP2) = id (MN1), so the current (5) -Id (MP3) ) =-Id (MP4) = 〇 will wait =====, __ _ _ _ is in = lose: fine) less than the round building v (c) 'third coffee crystal _ will - Id (MP3 )=-Id(MP4)=〇(6) Accurately check the peak of the input signal. "This W's Dragon Peak Detector can explain how the invention reduces power consumption. First, compare the electric power peak-to-peak detector disk of the Patent No. 517161: China's Republic of China's example In the prior art shown in FIG. 5, the third NM〇S transistor used in the present invention is connected to the source of the power supply 1301894 and the gate of the second NMOS transistor MN3. The voltage blame is equal to the power supply voltage vdd. In contrast, the PMOS current source ip used to provide a current to the differential amplifier 1 is composed of a PM0S transistor and is designed in the form of a diode, which is also intended as a current of PM〇s. The source Ip is used. The gate of the PM0S transistor is connected to the gate and connected to the ground. Therefore, the absolute value of the source voltage of the PM0S transistor gate used as the PMOS current source IP is strange. The third NMOS transistor is smaller than the fifth figure, and the PM s current source lp used to provide the current to the differential amplifier 1 is composed of a pM 〇s transistor. And the fifth riding silk technique is used to provide - current subtraction The third NMOS transistor MN3 used by the device is composed of -NM〇s transistors, and the transconductance parameter of the pM〇s transistor is usually smaller than the mutual conductance parameter of the nm〇s transistor (transconductance). The parameter KP represents a MOS semi-transistor model parameter in OrCAD pspice), so in the case of providing current to the differential amplifier, the transistor has a side effective channel width/length ratio, It has lower power consumption than the previous technique shown in Figure 5. • Next, compare the voltage peak detection 之中 of the Republic of China Announcement No. 62 专利 专利 ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ 第七 第七 第七 第七 第七 第七 第七 第七 第七 第七 第七 第七In the prior art, the gate of the third transistor 8 used to supply the current to the differential amplifier i is connected to the output terminal of the control transistor 3, which is designed as a diode ^ Equation 1* is connected between the input terminal of the voltage peak detector and the gate of the third NMQS transistor MN3. Since the control transistor 3 does not have a drain current flowing, @ this is used to provide a current 仏The differential amplifier i uses the third cis-transistor to cut the source voltage Vgs(_), etc.; VGS3(_3) two V(IN) - ντ(control sugar) (7) ^ where Vt((4) is the electric system Controlling the threshold voltage of the transistor 3. In contrast, the present invention is provided in the charging process of the capacitor. (IV) The current is supplied to the differential amplifier i. The PMOS current source is composed of a -PM0S transistor and is designed into two. In the form of a polar body, the absolute value of the gate-source voltage Vg of the MOS transistor is equal to the first nm 〇s The source voltage of the electric body MN1, that is, _ 10 1301894 I VGS(iP) I = V(IN)-VT(MNir [2 · Id (MN1 ) · L/(KP · W)] 1/2 (8) 'Vtxmnd denotes the threshold voltage of the first transistor μμ, w and l respectively represent the effective channel width and effective channel length of the first NM0S transistor surface, and KP represents one of the gold oxide semi-transistor model parameters in OrCADPspce Comparing equations (and (8) can be inferred
Vgs3((mn3) > | VGS(IP) I (9) /再者，本發明用以提供一電流給差動放大器i使用之ρΜ〇§電流源正 係由-fMOS電晶體所域，而第六_示先前技藝用以提供—電流給差 動放大器1使用之第三NM〇s電晶體順3係由一丽〇8電晶體所組成， 由於PMOS電晶體之互導參數κρ通常小於丽〇3電晶體之互導來數，因 此在用以提供電流給差動放大器丨使用之電晶體具有相同的有效通道寬产/ 長度比值的情況下’本發赚較第六圖所示之先前技藝具有更低之功率^肖 耗0 。。第^L®所示為巾華關公告錄第赌咖號專利案之電壓峰值檢知 盜(先W技藝)與本發明電壓峰值檢知器之〇rCA〇 pSpice暫態分析模擬姓 果，由該_結果可証實，本發明之電壓峰值檢知器可較先前技藝具^ 低之電流消耗。第九圖係以level 3模型且使觸綠咖则製程參數加以 模擬(其PM0S電曰曰曰體和NM〇S電晶體之零基底偏壓臨限電壓值％ -0.5V和〇.5V) ’其中，PM〇s電晶體_、_、Mp3、Mp4之通道寬長比 ^為_)=(2 · 0.25一.25卿），NM〇S電晶體匪、讀和娜之通道 寬長比均為(W/L)=(0.25pm/0.25pm)，nmos電晶體應3之通道寬 ^=(α25μιη/8 · G.25_ ’作為提供—電流給聽放大鞭 電k源IPWMOS電晶體之通道寬長比為(魏)=(〇25μηι/8 ·㈣㈣，至於 電容器C之電容值則為8pF。 、 本發明之電壓峰值檢知器在使用時可於電容器c兩端並聯連接一開 1301894 :利用:，供-放電路徑，以便將電容器上所儲存之電荷放電， 俾利於下次輸人電壓信號之峰值檢測。 的敌兒 【發明功效】 ，發明所提出之賴峰值檢知器，具有如下功效： 1)=積度及有裝置之小魏：由於本發日靖提出之電壓峰值檢知哭 增設—控制電晶體，並且僅使用了 5個·S電晶體、2^ 币日電晶體以及1個電容器，因此不但電路架構新穎、簡單、丑使用的 电曰曰脰數量較少，並且因不需使用運算放大器 财利於裝置之小型鱗優點； ”備“細貝度 ()呵知確度·本發明所提出之電壓峰值檢知器經模擬結果註實 確地檢測出輸人信號之峰值電壓，因此也具有高精確度之優點；貝㈣ 低功率消耗：本發明所提出之電壓峰值檢知器經模擬結果註實，確實能 有放卜低差動放大裔1之電流消耗，因此可有效降低電壓峰值檢知器之 功率消耗。 口口 2本發明特職紐描述了所選之最佳實施例，但舉凡麵本技術之人 可明瞭任何形式或是細紅可能賴化均未雌本發明的精神與範圍。 此，所有相關技術範疇内之改變都包括在本發明之申請專利範圍内。 12 1301894 【圖式簡单說明】 第一圖係顯不第一先前技藝中電壓峰值檢知器之電路圖· 第一圖係顯示第一圖電壓峰值檢知器之輸入電 態分析時序圖； 電壓信號之暫 第二圖係顯示第二先前技藝中電壓峰值檢知器之電路圖； 第四圖係顯示第三圖電壓峰值檢知器之輸入電壓信號 態分析時序圖； 1氣壓^號之暫 弟五圖係顯示苐二先前技藝中電壓峰值檢知器之電路圖；Vgs3((mn3) > | VGS(IP) I (9) / Furthermore, the present invention is used to provide a current to the differential amplifier i. The current source is positively represented by the -fMOS transistor. The sixth method shows that the third NM〇s transistor used in the differential amplifier 1 is composed of a Lie 8 transistor, since the mutual conductance parameter κρ of the PMOS transistor is usually smaller than that of the PMOS transistor. 〇3 The number of mutual conductances of the transistors, so in the case where the transistors used to supply current to the differential amplifier have the same effective channel wide/length ratio, 'this is earned as shown in the sixth figure. The skill has a lower power, and the power consumption is 0. The ^L® shows the voltage peak detection of the Tobacco Wag. The 〇rCA〇pSpice transient analysis simulates the surname, and the _ result confirms that the voltage peak detector of the present invention can consume less current than the prior art. The ninth figure is a level 3 model and makes the green coffee Then the process parameters are simulated (the zero base bias voltage value of the PM0S electric body and the NM〇S transistor) % -0.5V and 〇.5V) ' Among them, the channel width-to-length ratio of PM〇s transistors _, _, Mp3, Mp4 is _) = (2 · 0.25 - 1.25 qing), NM 〇 S transistor 匪The width-to-length ratio of the channel and the read channel are both (W/L)=(0.25pm/0.25pm), and the nmos transistor should have a channel width of 3^(α25μιη/8 · G.25_ ' as a supply - current to listen The channel width-to-length ratio of the amplified whip source IPWMOS transistor is (Wei) = (〇25μηι/8 · (4) (4), and the capacitance value of the capacitor C is 8pF. The voltage peak detector of the present invention can be used when The two ends of the capacitor c are connected in parallel to open 1301894: using: the supply-discharge path to discharge the charge stored on the capacitor, which is beneficial to the peak detection of the next input voltage signal. The enemy [inventive effect], the invention office The proposed peak detector has the following effects: 1) = Accumulation and small device with device: Due to the peak value of the voltage proposed by the Japanese, the crying is added to the control transistor, and only 5 · S is used. A transistor, a 2^ coin crystal, and a capacitor, so the circuit structure is novel, simple, and the number of ugly devices is small. And because there is no need to use an operational amplifier to benefit from the small scale advantages of the device; "Preparation of fine Bayesian () knowing the accuracy. The voltage peak detector proposed by the present invention accurately detects the peak value of the input signal through the simulation result. The voltage, therefore, also has the advantage of high precision; Bei (4) Low power consumption: The voltage peak detector proposed by the invention is verified by the simulation result, and can indeed have the current consumption of the low differential differential amplification 1 Effectively reduce the power consumption of the voltage peak detector. Port 2 The invention has described the best embodiment selected, but those skilled in the art can understand any form or fine red may not be female. The spirit and scope of the present invention. Therefore, all changes in the related art are included in the scope of the patent application of the present invention. 12 1301894 [Simple description of the diagram] The first diagram shows the circuit diagram of the voltage peak detector in the first prior art. The first diagram shows the input voltage analysis timing diagram of the voltage peak detector of the first diagram; The second diagram of the signal shows the circuit diagram of the voltage peak detector in the second prior art; the fourth diagram shows the timing diagram of the input voltage signal state analysis of the voltage peak detector of the third diagram; The fifth diagram shows the circuit diagram of the voltage peak detector in the prior art of the second embodiment;
第六圖係顯示第四先前技藝中電壓峰值檢知器之電路圖； 第七圖係顯示本發明較佳實施例之電壓峰值檢知器之電路圖； 第八圖係顯示本發明較佳實施例之輸入電壓信號及輪出電壓俨號 〜^ 析時序圖； 第九圖係比較本發明電壓峰值檢知器與第四先前技藝之暫態電流分析時序 圖0 【主要元件符號說明】 差動放大器 2 電流鏡 •—極體 D1 二極體 02 二極體 Id(MN3) NMOS電晶體MN3之汲極電流 OP1 運算放大器 〇P2 運算放大器 MP1 第一 PMOS電晶體MP2 第二PMOS電晶體 MP3 第三PMOS電晶體MP4 第四PMOS電晶體 第一 NMOS電晶體MN2 第二NMOS電晶體 IP PMOS電流源 Vdd 電源電壓 R1 電阻器 R2 電阻器 V(IN)輸入電壓信號 V(OUT)輸出電壓信號 c 電容器 136 is a circuit diagram showing a voltage peak detector in a fourth prior art; FIG. 7 is a circuit diagram showing a voltage peak detector according to a preferred embodiment of the present invention; and FIG. 8 is a view showing a preferred embodiment of the present invention. The input voltage signal and the output voltage 俨 〜 ^ 时序 时序 ; ; ; ; ; ; ; ; ; ; 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九 第九Current mirror • Polar body D1 diode 02 Diode Id (MN3) NMOS transistor MN3 drain current OP1 Operational amplifier 〇 P2 Operational amplifier MP1 First PMOS transistor MP2 Second PMOS transistor MP3 Third PMOS Crystal MP4 Fourth PMOS transistor First NMOS transistor MN2 Second NMOS transistor IP PMOS current source Vdd Power supply voltage R1 Resistor R2 Resistor V(IN) Input voltage signal V(OUT) Output voltage signal c Capacitor 13