TWI836000B - 包括橋接晶粒的半導體封裝件 - Google Patents
包括橋接晶粒的半導體封裝件 Download PDFInfo
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- TWI836000B TWI836000B TW109103862A TW109103862A TWI836000B TW I836000 B TWI836000 B TW I836000B TW 109103862 A TW109103862 A TW 109103862A TW 109103862 A TW109103862 A TW 109103862A TW I836000 B TWI836000 B TW I836000B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 325
- 239000003990 capacitor Substances 0.000 claims abstract description 54
- 239000010410 layer Substances 0.000 claims description 87
- 239000000565 sealant Substances 0.000 claims description 12
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 239000002210 silicon-based material Substances 0.000 claims description 5
- 239000008393 encapsulating agent Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 143
- 241000723873 Tobacco mosaic virus Species 0.000 description 16
- 238000000465 moulding Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000012812 sealant material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229920006336 epoxy molding compound Polymers 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/5381—Crossover interconnections, e.g. bridge stepovers
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Abstract
一種半導體封裝件包括外部再分配線(RDL)結構、設置在外部RDL結構上的第一半導體晶片、層疊在第一半導體晶片上的層疊模組以及層疊在外部RDL結構上的橋接晶粒。層疊模組的一部分從第一半導體晶片的側表面橫向突出。橋接晶粒支撐層疊模組的突出部。層疊模組包括內部RDL結構、設置在內部RDL結構上的第二半導體晶片、設置在內部RDL結構上的電容器晶粒以及內部密封劑。電容器晶粒用作第二半導體晶片的去耦電容器。
Description
本公開涉及半導體封裝技術,更具體地,涉及一種包括橋接晶粒的半導體封裝件。
相關申請的交叉引用
本申請是2019年10月28日提交的美國專利申請No. 16/665970的部分繼續申請,並且主張於2019年2月22日提交的韓國專利申請No.10-2019-0021453的優先權,以及於2020年2月4日提交的韓國專利申請No.10-2020-0013339的優先權。
近來,已經將許多努力付諸於將多個半導體晶片整合到單個半導體封裝件中。也就是說,已經嘗試了增加封裝件整合密度來實現通過多功能操作來高速處理大量資料的高性能半導體封裝件。例如,系統級封裝(system-in-package, SiP)技術可以被認為是用於實現高性能半導體封裝的有吸引力的候選。每個SiP中包括的多個半導體晶片並排設置。然而,這可能導致難以減小SiP的寬度。因此,已經提出了用於將多個半導體晶片設置在SiP封裝件中的各種技術來減小SiP的尺寸。
根據一個實施方式,一種半導體封裝件包括:外部再分配線(redistributed line, RDL)結構;第一半導體晶片,該第一半導體晶片設置在外部RDL結構上;層疊模組,該層疊模組層疊在第一半導體晶片上,使得在平面圖中層疊模組的一部分從第一半導體晶片的側表面橫向突出;以及橋接晶粒,該橋接晶粒層疊在外部RDL結構上以支撐層疊模組的突出部,並且被配置為包括將層疊模組電連接到外部RDL結構的導電通孔。層疊模組包括:內部RDL結構;第二半導體晶片,該第二半導體晶片設置在內部RDL結構上,使得第二半導體晶片的晶片焊盤電連接到內部RDL結構;電容器晶粒,該電容器晶粒與第二半導體晶片間隔開地設置在內部RDL結構上,並且被配置為包括通過內部RDL結構電連接至晶片焊盤的電容器;以及內部密封劑,該內部密封劑形成在內部RDL結構上,以覆蓋第二半導體晶片和所述電容器晶粒。
本文所使用的術語可以對應於考慮到它們在實施方式中的功能而選擇的詞,並且根據實施方式所屬領域的普通技術人員,術語的含義可以被解釋為不同。如果進行了詳細定義,則可以根據定義來解釋術語。除非另有定義,否則本文所使用的術語(包括技術術語和科學術語)具有與實施方式所屬領域的普通技術人員通常所理解的含義相同的含義。
將理解的是,儘管在本文中可以使用術語“第一”、“第二”、“第三”等來描述各種元件,但是這些元件不應受到這些術語的限制。這些術語僅用於將一個元件與另一個元件區分開,而不用於僅限定元件本身或者表示特定順序。
還應理解,當元件或層被稱為在另一元件或層“上”、“上方”、“下方”、“下麵”或“外部”時,該元件或層可以與另一元件或層直接接觸,或者可以存在中間元件或層。用於描述元件或層之間的關係的其它詞語(例如,“在…之間”與“直接在…之間”或“與…相鄰”與“與…直接相鄰”)應該以類似的方式來解釋。
可以使用諸如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”、“頂部”、“底部”之類的空間相對術語來描述元件和/或特徵與另一元件和/或特徵的關係,例如,如附圖中示出的。將理解的是,除了附圖中描繪的方向性之外,空間相對術語還旨在涵蓋裝置在使用和/或操作中的不同方向。例如,當附圖中的裝置被翻轉時,被描述為在其它元件或特徵下方和/或之下的元件將被定向為在其它元件或特徵上方。裝置可以以其它方式(旋轉90度或其它方向)來定向,並據此解釋本文使用的空間相對描述語。
系統級封裝件(SiP)可以對應於半導體封裝件,並且半導體封裝件可以包括諸如半導體晶片或半導體晶片之類的電子裝置。半導體晶片或半導體晶片可以通過使用晶片鋸切製程將諸如晶圓的半導體基板分成多片來獲得。半導體晶片可以對應於記憶體晶片、邏輯晶片、特殊應用積體電路(ASIC)晶片、應用處理器(AP)、圖形處理單元(GPU)、中央處理單元(CPU)或系統上晶片(silicon-on-chip, SoC)。記憶體晶片可以包括整合在半導體基板上的動態隨機存取記憶體(DRAM)電路、靜態隨機存取記憶體(SRAM)電路、NAND型快閃記憶體電路、NOR型快閃記憶體電路、磁隨機存取記憶體(MRAM)電路、電阻隨機存取記憶體(ReRAM)電路、鐵電隨機存取記憶體(FeRAM)電路或相變隨機存取記憶體(PcRAM)電路。邏輯晶片可以包括整合在半導體基板上的邏輯電路。半導體封裝件可用於諸如行動電話、與生物技術或醫療保健相關聯的電子系統或可穿戴電子系統之類的通信系統中。半導體封裝件可以適用於物聯網(IoT)。
在整個說明書中,相同的附圖標記代表相同的元件。即使參照一附圖未提及或描述一附圖標記,也會參照另一附圖提及或描述該附圖標記。另外,即使在附圖中未示出一附圖標記,也會參照另一附圖來提及或描述附圖標記。
圖1是例示了根據一個實施方式的系統級封裝件(SiP)10的截面圖。
參照圖1,SiP 10可以被配置為包括再分配線(RDL)結構100、第一半導體晶片300、第二半導體晶片400和橋接晶粒500。
第一半導體晶片300可以設置在RDL結構100上。第二半導體晶片400可以層疊在第一半導體晶片300的與RDL結構100相對的表面上,以與第一半導體晶片300交疊。第二半導體晶片400可以層疊在第一半導體晶片300上,以具有與懸突部相對應的突出部435,所述懸突部從與第一半導體晶片300的側表面對齊的垂直線起橫向突出。橋接晶粒500可以設置在RDL結構100上以支撐第二半導體晶片400的突出部435。橋接晶粒500可以設置在第二半導體晶片400的突出部435與RDL結構100之間,並且可以設置成在與突出部435相同的方向上與第一半導體晶片300橫向間隔開。
SiP 10還可以包括形成在RDL結構100上的模製層700。模製層700可以形成為覆蓋第一半導體晶片300和橋接晶粒500。模製層700可以延伸以覆蓋第二半導體晶片400。模製層700可以形成為圍繞並保護第二半導體晶片400,並露出第二半導體晶片400的與第一半導體晶片300相對的第二表面402。在模製層700被形成為使第二半導體晶片400的第二表面402露出的情況下,通過SiP 10的操作產生的來自第二半導體晶片400和第一半導體晶片300的熱可以通過第二半導體晶片400的第二表面402更容易地散發到外部空間。模製層700可以由各種模製材料或封裝材料中的任何一種形成。例如,模製層700可以由環氧模塑膠(EMC)材料形成。
圖2是例示了圖1的一部分(包括橋接晶粒500)的放大截面圖。
參照圖1和圖2,RDL結構100可以包括第一RDL圖案120。第一RDL圖案120可以是具有與第一半導體晶片300的一部分交疊的第一端和與橋接晶粒500的一部分交疊的第二端的導電圖案。
第一半導體晶片300可以包括第一組晶片焊盤310。第一半導體晶片300可以設置在RDL結構100上,使得第一半導體晶片300的第一晶片焊盤312電連接到第一RDL圖案120的第一端。第一晶片焊盤312可以是第一組晶片焊盤310中的任何一個。第一半導體晶片300可以以倒裝晶片形式安裝在RDL結構100上,使得第一半導體晶片300的第一組晶片焊盤310面對RDL結構100。
第一組內部連接器610可以設置在第一半導體晶片300和RDL結構100之間,以將第一半導體晶片300電連接到RDL結構100。第一組內部連接器610可以是導電凸塊或焊料凸塊。第五內部連接器612可以接合到第一RDL圖案120的一部分,以將第一晶片焊盤312電連接到第一RDL圖案120。第五內部連接器612可以是第一組內部連接器610中的任何一個。
第二半導體晶片400可以包括設置在第二半導體晶片400的突出部435上的第二組晶片焊盤410。第二半導體晶片400可以以倒裝晶片的形式安裝在第一半導體晶片300上。因此,設置在突出部435上的第二晶片焊盤412可以面對RDL結構100。因為第二晶片焊盤412被設置在突出部435上,所以第二晶片焊盤412不可能與第一半導體晶片300垂直交疊,從而暴露於第一半導體晶片300的外部區域中。第二晶片焊盤412可以是第二組晶片焊盤410中的任何一個。
橋接晶粒500可以設置在RDL結構100上以與第二半導體晶片400的突出部435交疊。橋接晶粒500可以被配置為包括主體510和貫穿主體510的多個通孔520。雖然在附圖中未示出,但是絕緣層可以附加地設置在主體510與每個通孔520之間,以使通孔520與主體510電絕緣。第一通孔522可以被設置為與第二半導體晶片400的第二晶片焊盤412交疊並且可以電連接到第二晶片焊盤412。第一通孔522可以是通孔520中的任何一個。第一通孔522可以設置為與第一RDL圖案120的第二端交疊,並且可以電連接到與第一通孔522交疊的第一RDL圖案120。第一通孔522可以設置為在垂直方向上將第二晶片焊盤412電連接到第一RDL圖案120。
橋接晶粒500還可以包括多個柱狀凸塊530。第一柱狀凸塊532可以設置在主體510上以從主體510的頂表面突出。第一柱狀凸塊532可以連接至第一通孔522的頂部。第一柱狀凸塊532可以是柱狀凸塊530中的任何一個。
第三組內部連接器630可以設置在橋接晶粒500與第二半導體晶片400之間,以將橋接晶粒500電連接至第二半導體晶片400。橋接晶粒500可以通過第三組內部連接器630接合至第二半導體晶片400,並且可以通過第三組內部連接器630電連接到第二半導體晶片400。第二內部連接器632可以將第二晶片焊盤412電連接到第一柱狀凸塊532。第二內部連接器632可以是第三組內部連接器630中的任何一個。橋接晶粒500還可以包括設置在主體510的底表面上的過孔焊盤540。第一過孔焊盤542可以連接至第一通孔522的底部。第一過孔焊盤542可以是過孔焊盤540中的任何一個。
第二組內部連接器620可以設置在橋接晶粒500和RDL結構100之間,以將橋接晶粒500電連接到RDL結構100。橋接晶粒500可以通過第二組內部連接器620接合到RDL結構100,並且可以通過第二組內部連接器620電連接到RDL結構100。第一內部連接器622可以接合並電聯接到第一過孔焊盤542。第一內部連接器622可以是第二組內部連接器620的任何一個。第一內部連接器622可以接合到第一RDL圖案120的一部分,以將第一過孔焊盤542電連接到第一RDL圖案120。
圖3是例示了圖2所示的將第一半導體晶片300和第二半導體晶片400彼此電連接的第一電路徑P1的立體圖。
參照圖2和圖3,橋接晶粒500在結構上支撐第二半導體晶片400的突出部435,並且還提供將第二半導體晶片400電連接至第一半導體晶片300的第一電路徑P1的一部分。第一電路徑P1可以被配置為包括第二半導體晶片400的第二晶片焊盤412、第二內部連接器632、第一柱狀凸塊532、第一通孔522、第一過孔焊盤542、第一內部連接器622、第一RDL圖案120、第五內部連接器612和第一半導體晶片300的第一晶片焊盤312。
第一半導體晶片300可以是執行資料的邏輯操作的處理器。例如,第一半導體晶片300可以包括諸如執行邏輯操作的應用處理器之類的系統上晶片(SoC)。第二半導體晶片400可以是儲存資料的記憶體半導體晶片。記憶體半導體晶片可以用作臨時儲存並提供在SoC的邏輯操作中使用的資料的快取記憶體晶片。第二半導體晶片400可以被配置為包括DRAM裝置。
如圖3所示,第一半導體晶片300的第一組晶片焊盤310可以均勻地設置在第一半導體晶片300的第一表面301的整個區域上。第二半導體晶片400的第二組晶片焊盤410可以設置在第二半導體晶片400的突出部435上。第二半導體晶片400的第二組晶片焊盤410可以設置在第二半導體晶片400的懸突出第一半導體晶片300(未與第一半導體晶片300交疊)的一部分(即,突出部435)上。第二半導體晶片400的第二組晶片焊盤410可以設置在第二半導體晶片400的週邊區域430上。其上設置有第二組晶片焊盤410的週邊區域430可以位於第二半導體晶片400的突出部435的第一表面401上。
第二半導體晶片400可以與第一半導體晶片300部分地交疊。第二半導體晶片400的除了突出部435之外的其它區域可以與第一半導體晶片300交疊。第二半導體晶片400的其它區域可以被第一半導體晶片300遮蓋。因此,第二半導體晶片400的第二組晶片焊盤410不可以設置在第二半導體晶片400的其它區域上。
第一晶片焊盤312可以通過第一電路徑P1電連接到第二半導體晶片400的第二晶片焊盤412。第一晶片焊盤312可以是第一組晶片焊盤310中的一個。儘管圖3將第一電路徑P1例示為單個路徑,但是SiP 10可以包括多個第一電路徑P1。在這種情況下,第一組晶片焊盤310可以分別通過多個第一電路徑P1電連接到第二組晶片焊盤410。在實施方式中,多個第一電路徑P1中的每一個可以被配置為包括第二半導體晶片400的第二組晶片焊盤410中的一個、第三組內部連接器630中的一個、柱狀凸塊530中的一個、通孔520中的一個、過孔焊盤540中的一個、第二組內部連接器620中的一個、第一RDL圖案120中的一個、第一組內部連接器610中的一個以及第一半導體晶片300的第一組晶片焊盤310中的一個。因為第二半導體晶片400通過多個第一電路徑P1電連接至第一半導體晶片300,因此可以在第一半導體晶片300和第二半導體晶片400之間設置多個輸入/輸出(I/O)路徑。也就是說,因為相鄰的兩個半導體晶片通過與I/O路徑相對應的多個短信號路徑彼此電連接,所以可以在兩個相鄰的半導體晶片之間通過多條路徑而不是通過單條路徑同時發送相對多的資料。因此,可以使用並行路徑以給定的速度從第一半導體晶片300向第二半導體晶片400傳輸更大量的資料,反之亦然。如果第一半導體晶片300是邏輯晶片(例如,處理器晶片),並且第二半導體晶片400是記憶體晶片,則第一半導體晶片300可以與用作高性能高速緩衝記憶體的第二半導體晶片400一起操作。因此,可以提高包括第一半導體晶片300和第二半導體晶片400的SiP 10的操作速度和性能。
再次參照圖2,第二半導體晶片400還可以包括在突出部435上與第二晶片焊盤412間隔開地設置的第三晶片焊盤411。橋接晶粒500還可以包括設置為與第三晶片焊盤411基本交疊的第二柱狀凸塊531。橋接晶粒500還可以包括第二通孔521,第二通孔521電連接到第二柱狀凸塊531並且被設置為與第一通孔522間隔開。橋接晶粒500還可以包括電連接到第二通孔521的第二過孔焊盤541。
RDL結構100還可以包括設置為與第一RDL圖案120間隔開的第二RDL圖案110。第二RDL圖案110可以設置為具有與第二過孔焊盤541交疊的部分。第二RDL圖案110可以通過第五RDL圖案140電連接到第一外部連接器210。第一外部連接器210可以是連接到RDL結構100的多個外部連接器200中的一個。外部連接器200可以用作將SiP 10電連接到外部裝置的連接端子或連接引腳。外部連接器200可以是諸如焊球之類的連接構件。
RDL結構100還可以包括設置在第五RDL圖案140和第二RDL圖案110之間的第一介電層191。第一RDL圖案120和第二RDL圖案110可以設置在第一介電層191的頂表面上,並且第五RDL圖案140可以設置在第一介電層191的底表面上。第五RDL圖案140可以基本上貫穿第一介電層191以連接到第二RDL圖案110。RDL結構100還可以包括第二介電層193,第二介電層193設置在第一介電層191的與外部連接器200相對的頂表面上,以將第二RDL圖案110與第一RDL圖案120電隔離。RDL結構100還可以包括第三介電層195,第三介電層195設置在第一介電層191的與第一半導體晶片300相對的底表面上,以將第五RDL圖案140與SiP 10的外部空間電隔離。第一外部連接器210可以基本上貫穿第三介電層195,以連接到第五RDL圖案140。
第六內部連接器621可以接合到第二RDL圖案110,以將第二過孔焊盤541電連接到第二RDL圖案110。第六內部連接器621可以是將橋接晶粒500電連接到RDL結構100的第二組內部連接器620中的任何一個。第七內部連接器631可以將第二柱狀凸塊531電連接到第三晶片焊盤411。第七內部連接器631可以是將橋接晶粒500電連接到第二半導體晶片400的第三組內部連接器630中的任何一個。
參照圖2和圖3,可以提供第二電路徑P2以包括第一外部連接器210、第五RDL圖案140、第二RDL圖案110、第六內部連接器621、第二過孔焊盤541、第二通孔521、第二柱狀凸塊531、第七內部連接器631和第三晶片焊盤411。第二電路徑P2可以是將第二半導體晶片400電連接到第一外部連接器210的路徑。與第一電路徑P1不同,第二電路徑P2不可以電連接到第一半導體晶片300。第一電路徑P1可以將第一半導體晶片300和第二半導體晶片400彼此電連接,使得第一半導體晶片300和第二半導體晶片400彼此通信。相反,第二電路徑P2可以用作用於向第二半導體晶片400供應電源電壓或接地電壓的電路徑。
再次參照圖2,RDL結構100還可以包括設置為與第一RDL圖案120和第二RDL圖案110間隔開的第三RDL圖案130。第三RDL圖案130可以被定位為與第一半導體晶片300交疊。第三RDL圖案130可以通過第六RDL圖案150電連接到第二外部連接器230。第一半導體晶片300還可以包括設置為與第一晶片焊盤312間隔開的第四晶片焊盤313。第三內部連接器613可以設置為將第四晶片焊盤313電連接到第三RDL圖案130。第三內部連接器613可以是將第一半導體晶片300電連接到RDL結構100的第一組內部連接器610中的任何一個。
第三電路徑P3可以設置為包括第四晶片焊盤313、第三內部連接器613、第三RDL圖案130、第六RDL圖案150和第二外部連接器230。第三電路徑P3可以是將第一半導體晶片300電連接至第二外部連接器230的電路徑。第一半導體晶片300可以通過第三電路徑P3與外部裝置通信,或者可以通過第三電路徑P3從外部裝置接收電力。
圖4是例示了圖1的一部分(包括橋接晶粒500)的放大截面圖。圖5是例示了圖4所示的橋接晶粒500的柱狀凸塊530的平面圖。
參照圖1和圖4,橋接晶粒500的主體510可以對應於諸如矽基板之類的半導體基板。當橋接晶粒500的主體510由矽材料製成時,可以使用應用於矽晶圓的微影製程來形成通孔520。橋接晶粒500的通孔520可以對應於具有直徑D1的矽通孔(TSV)。直徑D1可以小於貫穿模製層的通模孔(TMV)的直徑。因此,可以增加在具有有限尺寸的主體510中所形成的通孔520的數量。
如圖3所示,第二組晶片焊盤410可以密集地設置在第二半導體晶片400的突出部435上。橋接晶粒500的電連接到第二組晶片焊盤410的柱狀凸塊530可以包括至少兩個凸塊,如圖5所示。在這種情況下,橋接晶粒500的通孔520可以與第二組晶片焊盤410對齊以交疊,使得柱狀凸塊530與第二半導體晶片400的第二組晶片焊盤410交疊。因為橋接晶粒500的通孔520是使用TSV製程形成的,所以通孔520可以形成為例如與TMV的直徑相比具有相對小的值的直徑D1。因此,可以使得橋接晶粒500的與多個I/O端子、電源端子和接地端子分別對應的通孔520的數量最大化。也就是說,即使第二組晶片焊盤410被密集地設置,也可以形成橋接晶粒500的通孔520,以使得通孔520被定位為具有與第二組晶片焊盤410相同的節距尺寸。因此,即使第二組晶片焊盤410被密集地設置,也可以將第二組晶片焊盤410垂直地連接到橋接晶粒500的相應通孔520,而無需在第二半導體晶片400上形成任何再分配線。
如果通孔520的直徑D1減小,則通孔520的垂直長度也可以減小。當形成通孔520以貫穿具有厚度T3的主體510時,由於填充有通孔520的導通孔的縱橫比的限制,在減小通孔520的直徑D1方面可能存在限制。為了減小橋接晶粒500的通孔520的直徑D1,可能需要減小主體510的厚度T3以滿足通孔520所形成於的導通孔的縱橫比的限制。為了增加形成於主體510中的通孔520的數量,可能需要將主體510的厚度T3減小為比第一半導體晶片300的厚度T1小。在這種情況下,可以減小橋接晶粒500的通孔520的直徑D1。
為了使橋接晶粒500在結構上支撐第二半導體晶片400,將橋接晶粒500的總厚度T2設置為等於第一半導體晶片300的厚度T1可以是有效的。例如,比第一半導體晶片300的厚度T1小的主體510的厚度T3可以由橋接晶粒500的柱狀凸塊530的厚度T4和橋接晶粒500的過孔焊盤540的厚度T5來補償。也就是說,通過適當地調整橋接晶粒500的柱狀凸塊530的厚度T4,可以將橋接晶粒500的總厚度T2調整為等於第一半導體晶片300的厚度T1。橋接晶粒500的總厚度T2可以包括橋接晶粒500的柱狀凸塊530的厚度T4、橋接晶粒500的過孔焊盤540的厚度T5以及主體510的厚度T3。
柱狀凸塊530可以分別直接接合到第三組內部連接器630。第一柱狀凸塊532的直徑D2可以大於通孔520的直徑D1。因此,用作第三組內部連接器630的焊料凸塊可以分別直接接合到橋接晶粒500的柱狀凸塊530。為了使橋接晶粒500的過孔焊盤540直接接合到第二組內部連接器620,過孔焊盤540的直徑D3可以大於通孔520的直徑D1。
圖6是例示了圖1所示的第一半導體晶片300和第二半導體晶片400之間的連接部的放大截面圖。
參照圖1和圖6,第二半導體晶片400可以與第一半導體晶片300部分地交疊,並且第二半導體晶片400的突出部435可以由橋接晶粒500支撐。第二半導體晶片400的突出部435通過第三組內部連接器630接合至橋接晶粒500,並且可以使用虛設凸塊690來支撐第二半導體晶片400的與突出部435相對的邊緣436。因為虛設凸塊690支撐第二半導體晶片400的邊緣436,所以可以防止第二半導體晶片400傾斜。因為在第二半導體晶片400的突出部435接合到橋接晶粒500時虛設凸塊690設置在第一半導體晶片300和第二半導體晶片400之間,所以第二半導體晶片400可以保持水平位準。
虛設凸塊690可以是焊料凸塊。虛設凸塊690可以附接到第二半導體晶片400的第一表面401。虛設接合焊盤691可以形成在第二半導體晶片400的第一表面401上。在這種情況下,虛設凸塊690可以接合至虛設接合焊盤691。虛設接合焊盤691可以形成在設置於第二半導體晶片400的第一表面401上的鈍化層425上。虛設接合焊盤691可以使用金屬濺射製程形成在鈍化層425上。鈍化層425可以形成為覆蓋第二半導體晶片400的主體420(由矽材料製成)並使其電絕緣。因此,虛設凸塊690可以與第二半導體晶片400的內部電路電絕緣。虛設凸塊690可以與第一半導體晶片300的與RDL結構100相對的第二表面302接觸。
圖7是例示了根據另一實施方式的SiP 11的截面圖。
參照圖7,SiP 11可以被配置為包括RDL結構100、第一半導體晶片300、第二半導體晶片400、橋接晶粒500和模製層700。第二半導體晶片400可以與第一半導體晶片300部分地交疊,並且第二半導體晶片400的突出部435可以由橋接晶粒500支撐。黏合層690L可以設置在第一半導體晶片300和第二半導體晶片400之間。黏合層690L可以支撐第二半導體晶片400。當第二半導體晶片400的突出部435接合至橋接晶粒500並由橋接晶粒500支撐時,黏合層690L可以防止第二半導體晶片400傾斜。黏合層690L可以説明第二半導體晶片400保持水準。
黏合層690L可以附接到第二半導體晶片400的第一表面401和第一半導體晶片300的第二表面302。黏合層690L可以將第二半導體晶片400接合至第一半導體晶片300。
圖8是例示了根據又一實施方式的SiP 12的截面圖。圖9是例示了圖8的一部分(包括通模孔(TMV)2800)的截面圖。
參照圖8,SiP 12可以實現為具有封裝體疊層(PoP)形狀。SiP 12可以被配置為包括第一子封裝件SP1和安裝在第一子封裝件SP1上的第二子封裝件SP2。第一子封裝件SP1可以被配置為包括RDL結構2100、第一半導體晶片2300、第二半導體晶片2400、橋接晶粒2500、模製層2700和TMV 2800。
RDL結構2100可以被配置為包括第一RDL圖案2120、第二RDL圖案2110、第三RDL圖案2130、第四RDL圖案2170、第五RDL圖案2140、第六RDL圖案2150、第七RDL圖案2180以及第八RDL圖案2190。RDL結構2100還可以包括第一介電層2191、第二介電層2193和第三介電層2195。第一RDL圖案2120、第二RDL圖案2110、第三RDL圖案2130、第四RDL圖案2170和第七RDL圖案2180可以設置在第一介電層2191的頂表面上。第二介電層2193可以設置在第一介電層2191的頂表面上以使第一RDL圖案2120、第二RDL圖案2110、第三RDL圖案2130、第四RDL圖案2170和第七RDL圖案2180彼此電絕緣。第五RDL圖案2140、第六RDL圖案2150和第八RDL圖案2190可以設置在第一介電層2191的與第二介電層2193相對的底表面上。第三介電層2195可以形成在第一介電層2191的底表面上,以使第五RDL圖案2140、第六RDL圖案2150和第八RDL圖案2190彼此電絕緣。
RDL結構2100可以對應於電連接到第一半導體晶片2300和第二半導體晶片2400的互連結構。在另一實施方式中,印刷電路板(PCB)可以用作互連結構。
外部連接器2200可以附接到RDL結構2100。外部連接器2200可以包括彼此間隔開並且彼此電絕緣的第一外部連接器2210、第二外部連接器2230和第三外部連接器2270。
第一半導體晶片2300可以包括系統上晶片(SoC),並且第二半導體晶片2400可以包括第一記憶體半導體晶片。第二子封裝件SP2可以包括連接到與第一半導體晶片2300相對應的SoC的第二記憶體半導體晶片。第二記憶體半導體晶片可以包括NAND型快閃記憶體裝置或DRAM裝置。第一記憶體半導體晶片可以充當臨時記憶體裝置或緩衝記憶體裝置,並且第二記憶體半導體晶片可以充當主記憶體裝置。
第一半導體晶片2300可以包括多個晶片焊盤2310。第一半導體晶片2300的晶片焊盤2310可以包括第一晶片焊盤2312、第四晶片焊盤2313和第五晶片焊盤2317。
第一半導體晶片2300可以通過多個內部連接器2610電連接到RDL結構2100。內部連接器2610可以包括第三內部連接器2613、第四內部連接器2617和第五內部連接器2612。
第二半導體晶片2400可以包括與懸突部相對應的突出部2435,該懸突部從與第一半導體晶片2300的側表面對齊的垂直線起橫向突出。第二半導體晶片2400包括設置在突出部2435上的多個晶片焊盤2410。
橋接晶粒2500可以在結構上支撐第二半導體晶片2400的突出部2435。橋接晶粒2500可以被配置為包括主體2510、通孔2520、柱狀凸塊2530和過孔焊盤2540。
橋接晶粒2500可以通過內部連接器2620電連接到RDL結構2100。橋接晶粒2500可以通過其它內部連接器2630電連接到第二半導體晶片2400。
多個虛設凸塊2690可以設置在第一半導體晶片2300和第二半導體晶片2400之間,以保持第二半導體晶片2400的水準。
TMV 2800可以基本上貫穿模製層2700以電連接到RDL結構2100。第二子封裝件SP2可以設置在模製層2700上,並且可以通過互連器2250電連接到TMV 2800。互連器2250可以是諸如焊球之類的連接構件。儘管在附圖中未示出,但是第二子封裝件SP2可以設置為包括含有積體電路的半導體晶片、用於在半導體晶片中的元件之間進行電連接的內部互連線以及保護半導體晶片的模製層。
參照圖9,與TMV 2800中的任何一個對應的第一TMV 2817可以連接到第四RDL圖案2170的一端。第四RDL圖案2170的另一端可以通過第四內部連接器2617電連接到第一半導體晶片2300的第五晶片焊盤2317。第一TMV 2817可以通過與互連器2250中的任何一個相對應的第一互連器2257電連接到第二子封裝件SP2。第一互連器2257、第一TMV 2817、第四RDL圖案2170、第四內部連接器2617和第五晶片焊盤2317可以組成第四電路徑P4。第四電路徑P4可以是將第二子封裝件SP2連接到第一半導體晶片2300的信號路徑。
與TMV 2800中的任何一個對應的第二TMV 2818可以將第七RDL圖案2180電連接到與互連器2250中的任何一個對應的第二互連器2258。第七RDL圖案2180可以連接到第八RDL圖案2190,並且第八RDL圖案2190可以連接至第三外部連接器2270。因此,第二互連器2258、第二TMV 2818、第七RDL圖案2180、第八RDL圖案2190和第三外部連接器2270可以組成第五電路徑P5。第五電路徑P5可以是向第二子封裝件SP2提供電源電壓或接地電壓的電路徑。
如上所述,根據實施方式,第二半導體晶片400(或2400)可以層疊在第一半導體晶片300(或2300)上以減小SiP 10、11或12的寬度或尺寸。根據SiP 10、11或12,因為第二半導體晶片400(或2400)使用橋接晶粒500(或2500)電連接至第一半導體晶片300(或2300),所以可以將第二半導體晶片400(或2400)層疊在第一半導體晶片300(或2300)上。
向半導體晶片施加熱的工序會使半導體晶片(特別是儲存晶片)的特性劣化。例如,當熱被施加到DRAM裝置時,DRAM裝置的記憶體單元的資料保持時間縮短,減小了DRAM裝置的刷新週期。另外,如果熱被施加到NAND型快閃記憶體裝置,則NAND型快閃記憶體裝置的記憶體單元的資料保持時間也會被縮短。
根據本教導的實施方式的SiP 10、11和12可以實現為包括附接到RDL結構100的內部連接器,以用於半導體晶片之間的互連以及外部裝置和半導體晶片之間的互連。因此,可以省略或減少用於使用來形成再分配線的聚合物層固化的熱處理(或退火製程)。結果,可以提高SiP 10、11和12的性能。例如,如果在形成RDL結構100之後,將第一半導體晶片300和第二半導體晶片400層疊在RDL結構100上以形成SiP 10、11或12,則可以防止在執行熱處理(或退火製程)以使用於形成RDL圖案的聚合物層固化時熱被施加到第一半導體晶片300和第二半導體晶片400。
圖10是例示了根據一個實施方式的半導體封裝件30的截面圖。
參照圖10,半導體封裝件30可以被配置為包括外部RDL結構3100、第一半導體晶片3300、包括第二半導體晶片3400的層疊模組3400S、橋接晶粒3500和外部密封劑3700。半導體封裝件30可以對應於系統級封裝件(SiP)。例如,第一半導體晶片3300可以被配置為包括系統上晶片(SoC),並且第二半導體晶片3400可以被配置為包括記憶體半導體晶片。記憶體半導體晶片可以是儲存資料的記憶體晶片,例如,DRAM晶片,並且SoC可以是與第二半導體晶片3400通信以執行各種邏輯操作的邏輯晶片。
第一半導體晶片3300可以設置在外部RDL結構3100上。第一半導體晶片3300可以設置在外部RDL結構3100上,使得第一半導體晶片3300的與連接端子相對應的第一組晶片焊盤3310面對外部RDL結構3100。第一組內部連接器3610可以將第一組晶片焊盤3310電連接到外部RDL結構3100。
外部RDL結構3100可以用作將半導體封裝件30電連接到外部裝置或外部系統的互連構件。外部RDL結構3100可以被配置為包括設置在第一介電層3191的表面上的第一RDL圖案3110和設置在第一介電層3191的與第一RDL圖案3110相對的另一表面上的第二RDL圖案3140。第二介電層3193可以形成在第一介電層3191上,以使第一RDL圖案3110彼此電隔離或絕緣。第三介電層3195可以形成在第一介電層3191的底表面上,以使第二RDL圖案3140彼此電隔離或絕緣。第二RDL圖案3140可以貫穿第一介電層3191以電連接到第一RDL圖案3110。外部連接器3200可以附接到第二RDL圖案3140。
第一組內部連接器3610可以將第一半導體晶片3300的第一組晶片焊盤3310電連接到第一RDL圖案3110中的一些。第二組內部連接器3620可以將橋接晶粒3500的導電通孔3520電連接到第一RDL圖案3110中的另一些。像圖1所示的第一RDL圖案120那樣,第一RDL圖案3110中的又一些可以將橋接晶粒3500的導電通孔3520電連接至第一半導體晶片3300。第一RDL圖案3110中的再一些可以通過第二RDL圖案3140將橋接晶粒3500的導電通孔3520電連接到外部連接器3200。
再次參照圖10,層疊模組3400S可以垂直層疊在第一半導體晶片3300上。黏合層3340可以設置在層疊模組3400S和第一半導體晶片3300之間,以將層疊模組3400S附接到第一半導體晶片3300。黏合層3340可以將層疊模組3400S固定到第一半導體晶片3300。
層疊模組3400S可以層疊在第一半導體晶片3300上,使得從平面圖觀察時,層疊模組3400S的邊緣從第一半導體晶片的側表面3301橫向突出,以提供與懸突部相對應的突出部3435。橋接晶粒3500可以設置在外部RDL結構3100上以支撐層疊模組3400S的突出部3435。橋接晶粒3500可以被配置為包括將層疊模組3400S電連接到外部RDL結構3100的導電通孔3520。導電通孔3520可以垂直地貫穿橋接晶粒3500的主體3510。
第三組內部連接器3630可以設置在橋接晶粒3500與層疊模組3400S的突出部3435之間。第三組內部連接器3630可以將橋接晶粒3500的通孔3520電連接到層疊模組3400S的第二半導體晶片3400的第二組晶片焊盤3410。因此,層疊模組3400S的突出部3435可以通過第二組內部連接器3620和第三組內部連接器3630支撐並且可以被穩定地固定。
與圖1中示出的橋接晶粒500類似,橋接晶粒3500可以被配置為進一步包括柱狀凸塊(圖1的530)。
層疊模組3400S被配置為包括內部RDL結構3900、第二半導體晶片3400、電容器晶粒3800和內部密封劑3750。內部密封劑3750可以形成在內部RDL結構3900上以覆蓋第二半導體晶片3400和電容器晶粒3800。內部密封劑3750可以用作用於保持內部RDL結構3900、第二半導體晶片3400和電容器晶粒3800以提供一個模組的基礎層。內部密封劑3750可以由各種模製材料中的至少一種形成。內密封劑3750可以由包括環氧模塑膠(EMC)材料的模製層形成。
第二半導體晶片3400可以設置在內部RDL結構3900上,使得第二組晶片焊盤3410電連接到內部RDL結構3900。電容器晶粒3800可以與第二半導體晶片3400間隔開地設置在內部RDL結構3900上。電容器晶粒3800可以被配置為包括由矽材料構成的主體3890和形成於主體3890中的電容器3830。內部RDL結構3900可以設置為將電容器晶粒3800的電容器3830電連接到第二半導體晶片3400的第二組晶片焊盤3410的互連結構。
圖11是例示了電容器晶粒3800的截面圖。圖11是例示了圖10所示的電容器晶粒3800的一些組件的截面圖。
參照圖10和圖11,電容器晶粒3800可以包括形成於電容器晶粒3800的主體3890的表面上的電容器3830。電容器3830可以被配置為包括第一電極板3832、介電層3833和第二電極板3834。第一電極板3832可以形成於電容器晶粒3800的主體3890上,介電層3833可以形成在第一電極板3832上,並且第二電極板3834可以形成在介電層3833上。電容器晶粒3800的主體3890可以具有提供凹形溝槽3839的表面。第一電極板3832、介電層3833和第二電極板3834可以進一步延伸到溝槽3839中。第一電極板3832和第二電極板3834之間的有效交疊面積可以由於溝槽3839的存在而增加,從而增加電容器3830的電容值。
第一絕緣層3831可以設置在電容器晶粒3800的主體3890與第一電極板3832之間,以使主體3890與第一電極板3832絕緣。此外,可以附加地形成第二絕緣層3837以覆蓋電容器3830。電容器3830還可以包括貫穿第二絕緣層3837以電連接至第一電極板3832的第一電極3835。此外,電容器3830還可包括貫穿第二絕緣層3837以電連接到第二電極板3834的第二電極3836。
圖12是例示了層疊模組3400S的第一內部RDL圖案3910和第二內部RDL圖案3920的平面圖。圖12是例示了構成圖10的內部RDL結構3900的第一內部RDL圖案3910和第二內部RDL圖案3920的平面圖。出於容易和便於說明的目的,圖12中的第一內部RDL圖案3910和第二內部RDL圖案3920被例示為僅包括將第二組晶片焊盤3410連接至第一電極3835和第二電極3836的部分,而沒有覆蓋第二組晶片焊盤3410以及第一電極3835和第二電極3836的部分。
參照圖10、圖11和圖12,內部RDL結構3900可以包括第一RDL圖案3910和第二RDL圖案3920。第一內部RDL圖案3910可以是延伸以將電容器3830的第一電極3835連接到第二組晶片焊盤3410中的第一晶片焊盤3411的導電圖案。第二內部RDL圖案3920可以是延伸以將電容器3830的第二電極3836連接到第二組晶片焊盤3410中的第二晶片焊盤3413的導電圖案。第一晶片焊盤3411可以被設置為用於向第二半導體晶片3400施加電源電壓的電源端子。第二晶片焊盤3413可以被設置為用於向第二半導體晶片3400提供接地電壓的接地端子。
根據以上描述,電容器3830的第一電極3835可以連接到用於向第二半導體晶片3400施加電源電壓的電路徑,並且電容器3830的第二電極3836可以連接到用於將接地電壓提供給第二半導體晶片3400的另一電路徑。這樣,因為電容器3830聯接在電源端子和接地端子之間,所以電容器3830可以用作第二半導體晶片3400的去耦電容器。因此,當第二半導體晶片3400操作時,電容器3830可以減少雜訊。
當形成第一RDL圖案3910和第二RDL圖案3920時,交疊焊盤3930可以形成為與第三晶片焊盤3412交疊。交疊焊盤3930可以是與第一內部RDL圖案3910和第二內部RDL圖案3920同時形成的導電焊盤。內部RDL結構3900還可以包括第一絕緣層3941,第一絕緣層3941設置在第二半導體晶片3400與第一RDL圖案3910和第二RDL圖案3920之間,以使第一RDL圖案3910和第二RDL圖案3920與第二半導體晶片3400絕緣。內部RDL結構3900還可以包括形成為覆蓋第一RDL圖案3910和第二RDL圖案3920的第二絕緣層3942。
再次參照圖10,電容器晶粒3800可以設置在第一半導體晶片3300上以與第一半導體晶片3300的一部分完全交疊。層疊模組3400S可以設置在第一半導體晶片3300上。如果層疊模組3400S不包括電容器晶粒3800,則電容器晶粒3800所佔據的空間可以填充有密封劑材料,例如,內部密封劑3750或外部密封劑3700。在這種情況下,當半導體封裝件30被加熱或冷卻時,與第一半導體晶片3300和第二半導體晶片3400相比,填充電容器晶粒3800的空間的密封劑材料可以相對更大地膨脹或收縮。這是因為密封劑材料包括聚合物組分,而聚合物組分與對應於第一半導體晶片3300和第二半導體晶片3400的主要組分的矽材料相比具有相對高的熱膨脹係數。因此,如果層疊模組3400S包括密封劑材料而不是電容器晶粒3800,則半導體封裝件30可能容易翹曲。然而,根據本實施方式,層疊模組3400S包括電容器晶粒3800,以減少密封劑材料的量。因此,可以抑制或防止半導體封裝件30的翹曲。
圖13是例示了包括採用根據實施方式的系統級封裝件(SiP)和半導體封裝件中的至少一個的記憶卡7800的電子系統的框圖。記憶卡7800包括諸如非易失性記憶體裝置之類的記憶體7810以及記憶體控制器7820。記憶體7810和記憶體控制器7820可以儲存資料並讀出所儲存的資料。記憶體7810和記憶體控制器7820中的至少一個可以包括根據實施方式的至少一個SiP或至少一個半導體封裝件。
記憶體7810可以包括應用了本公開的實施方式的技術的非易失性記憶體裝置。記憶體控制器7820可以控制記憶體7810,使得回應於來自主機7830的讀/寫請求而讀出儲存的資料或儲存資料。
圖14是例示了包括根據實施方式的SiP和半導體封裝件中的至少一個的電子系統8710的框圖。電子系統8710可以包括控制器8711、輸入/輸出單元8712和記憶體8713。控制器8711、輸入/輸出單元8712和記憶體8713可以通過提供資料移動路徑的匯流排8715彼此聯接。
在實施方式中,控制器8711可以包括一個或更多個微處理器、數位訊號處理器、微控制器和/或能夠執行與這些元件相同的功能的邏輯裝置。控制器8711或記憶體8713可以包括根據本公開的實施方式的SiP和半導體封裝件中的至少一個。輸入/輸出單元8712可以包括從小鍵盤、鍵盤、顯示裝置、觸控式螢幕等中選擇的至少一個。記憶體8713是用於儲存資料的裝置。記憶體8713可以儲存要由控制器8711執行的資料和/或命令等。
記憶體8713可以包括諸如DRAM之類的易失性記憶體裝置和/或諸如快閃記憶體之類的非易失性記憶體裝置。例如,可以將快閃記憶體安裝到諸如移動終端或臺式電腦之類的資訊處理系統。快閃記憶體可以構成固態盤(SSD)。在這種情況下,電子系統8710可以在快閃記憶體系統中穩定地儲存大量資料。
電子系統8710還可以包括被配置為向通信網路發送資料和從通信網路接收資料的介面8714。介面8714可以是有線類型或無線類型。例如,介面8714可以包括天線、或者有線收發器或無線收發器。
電子系統8710可以被實現為執行各種功能的移動系統、個人電腦、工業電腦或邏輯系統。例如,移動系統可以是個人數位助理(PDA)、可擕式電腦、平板電腦、行動電話、智慧型電話、無線電話、膝上型電腦、記憶卡、數位音樂系統和資訊發送/接收系統中的任何一種。
如果電子系統8710是能夠執行無線通訊的設備,則電子系統8710可以用在使用CDMA(碼分多址)、GSM(全球移動通信系統)、NADC(北美數位蜂窩)、E-TDMA(增強型時分多址)、WCDMA(寬頻碼分多址)、CDMA2000、LTE(長期演進)或Wibro(無線寬頻互聯網)的技術的通信系統中。
已經出於例示的目的公開了本公開的實施方式。本領域技術人員將理解,在不脫離本公開和所附請求項的範圍和精神的情況下,可以進行各種變型、添加和替換。
10、11、12:系統級封裝件(SiP)
30:半導體封裝件
100:再分配線(RDL)結構
110:第二RDL圖案
120:第一RDL圖案
130:第三RDL圖案
140:第五RDL圖案
150:第六RDL圖案
191:第一介電層
193:第二介電層
195:第三介電層
200:外部連接器
210:第一外部連接器
230:第二外部連接器
300:第一半導體晶片
301:第一表面
302:第二表面
310:第一組晶片焊盤
312:第一晶片焊盤
313:第四晶片焊盤
400:第二半導體晶片
401:第一表面
402:第二表面
410:第二組晶片焊盤
411:第三晶片焊盤
412:第二晶片焊盤
435:突出部
500:橋接晶粒
510:主體
520:通孔
521:第二通孔
522:第一通孔
530:柱狀凸塊
531:第二柱狀凸塊
532:第一柱狀凸塊
540:過孔焊盤
541:第二過孔焊盤
542:第一過孔焊盤
610:第一組內部連接器
612:第五內部連接器
613:第三內部連接器
620:第二組內部連接器
621:第六內部連接器
622:第一內部連接器
630:第三組內部連接器
631:第七內部連接器
632:第二內部連接器
690:虛設凸塊
690L:黏合層
700:模製層
2100:RDL結構
2110:第二RDL圖案
2120:第一RDL圖案
2130:第三RDL圖案2130
2140:第五RDL圖案
2150:第六RDL圖案
2170:第四RDL圖案
2180:第七RDL圖案
2190:第八RDL圖案
2191:第一介電層
2193:第二介電層
2195:第三介電層
2200:外部連接器
2210:第一外部連接器
2230:第二外部連接器
2250:互連器
2257:第一互連器
2258:第二互連器
2270:第三外部連接器
2300:第一半導體晶片
2310:晶片焊盤
2312:第一晶片焊盤
2313:第四晶片焊盤
2317:第五晶片焊盤
2400:第二半導體晶片
2410:晶片焊盤
2435:突出部
2500:橋接晶粒
2510:主體
2520:通孔
2530:柱狀凸塊
2540:過孔焊盤
2610:內部連接器
2612:第五內部連接器
2613:第三內部連接器
2617:第四內部連接器
2620:內部連接器
2630:內部連接器
2690:虛設凸塊
2700:模製層
2800:TMV
2817:第一TMV
2818:第二TMV
3100:外部RDL結構
3110:第一RDL圖案
3140:第二RDL圖案
3191:第一介電層3191
3193:第二介電層
3195:第三介電層
3200:外部連接器
3300:第一半導體晶片
3301:第一半導體晶片的側表面
3310:第一組晶片焊盤
3340:黏合層
3400:第二半導體晶片
3400S:層疊模組
3410:第二組晶片焊盤
3411:第一晶片焊盤
3412:第三晶片焊盤
3413:第二晶片焊盤
3435:突出部
3500:橋接晶粒
3510:主體
3520:導電通孔
3610:第一組內部連接器
3620:第二組內部連接器
3630:第三組內部連接器
3700:外部密封劑
3750:內部密封劑
3800:電容器晶粒
3830:電容器
3831:第一絕緣層
3832:第一電極板
3833:介電層
3834:第二電極板
3835:第一電極
3836:第二電極
3837:第二絕緣層
3839:溝槽
3890:主體
3900:內部RDL結構
3910:第一內部RDL圖案
3920:第二內部RDL圖案
3930:交疊焊盤
3941:第一絕緣層
3942:第二絕緣層
7800:記憶卡
7810:記憶體
7820:記憶體控制器
7830:主機
8711:控制器
8712:輸入/輸出單元
8713:記憶體
8714:介面
8715:匯流排
P1:第一電路徑
P2:第二電路徑
P3:第三電路徑
P4:第四電路徑
P5:第五電路徑
SP1:第一子封裝件
SP2:第二子封裝件
[圖1]是例示了根據一個實施方式的系統級封裝件(SiP)的截面圖。
[圖2]是例示了圖1的一部分(包括橋接晶粒)的放大截面圖。
[圖3]是例示了將圖2所示的半導體晶片彼此連接的電路徑的立體圖。
[圖4]是聚焦於圖1的橋接晶粒的放大截面圖。
[圖5]是例示了圖4的橋接晶粒中所包括的柱狀凸塊的陣列的平面圖。
[圖6]是例示了圖1所示的半導體晶片之間的連接部的放大截面圖。
[圖7]是例示了根據另一實施方式的SiP的截面圖。
[圖8]是例示了根據又另一實施方式的SiP的截面圖。
[圖9]是例示了圖8的一部分(包括通模孔(through mold vias))的截面圖。
[圖10]是例示了根據一個實施方式的半導體封裝件的截面圖。
[圖11]是例示了根據一個實施方式的半導體封裝件的電容器晶粒的截面圖。
[圖12]是例示了根據一個實施方式的設置在半導體封裝件的層疊模組中的內部再分配線的平面圖。
[圖13]是例示了採用包括根據一個實施方式的至少一個SiP或至少一個半導體封裝件的記憶卡的電子系統的框圖。
[圖14]是例示了包括根據一個實施方式的至少一個SiP或至少一個半導體封裝件的另一電子系統的框圖。
10:系統級封裝件(SiP)
100:再分配線(RDL)結構
110:第二RDL圖案
120:第一RDL圖案
130:第三RDL圖案
140:第五RDL圖案
150:第六RDL圖案
191:第一介電層
193:第二介電層
195:第三介電層
200:外部連接器
210:第一外部連接器
230:第二外部連接器
300:第一半導體晶片
301:第一表面
302:第二表面
310:第一組晶片焊盤
312:第一晶片焊盤
313:第四晶片焊盤
400:第二半導體晶片
401:第一表面
402:第二表面
410:第二組晶片焊盤
411:第三晶片焊盤
412:第二晶片焊盤
435:突出部
500:橋接晶粒
510:主體
520:通孔
521:第二通孔
522:第一通孔
530:柱狀凸塊
531:第二柱狀凸塊
532:第一柱狀凸塊
540:過孔焊盤
541:第二過孔焊盤
542:第一過孔焊盤
610:第一組內部連接器
612:第五內部連接器
613:第三內部連接器
620:第二組內部連接器
621:第六內部連接器
622:第一內部連接器
630:第三組內部連接器
631:第七內部連接器
632:第二內部連接器
690:虛設凸塊
Claims (10)
- 一種半導體封裝件,該半導體封裝件包括:外部再分配線(RDL)結構;第一半導體晶片,該第一半導體晶片被設置在所述外部RDL結構上;層疊模組,該層疊模組層疊在所述第一半導體晶片上,使得在平面圖中,所述層疊模組的一部分從所述第一半導體晶片的側表面橫向突出;以及橋接晶粒,該橋接晶粒層疊在所述外部RDL結構上以支撐所述層疊模組的突出部,並且被配置為包括將所述層疊模組電連接到所述外部RDL結構的導電通孔,其中,所述層疊模組包括:內部RDL結構;第二半導體晶片,該第二半導體晶片被設置在所述內部RDL結構上,使得所述第二半導體晶片的晶片焊盤電連接到所述內部RDL結構;電容器晶粒,該電容器晶粒與所述第二半導體晶片間隔開地設置在所述內部RDL結構上,並且被配置為包括通過所述內部RDL結構電連接至所述晶片焊盤的電容器;以及內部密封劑,該內部密封劑形成在所述內部RDL結構上,以覆蓋所述第二半導體晶片和所述電容器晶粒;其中,所述內部RDL結構自該第二半導體晶片延伸至該電容器晶粒,且電連接該第二半導體晶片的所述晶片焊盤至該電容器。
- 根據請求項1所述的半導體封裝件,其中,所述電容器晶粒被定位為與所述第一半導體晶片交疊。
- 根據請求項1所述的半導體封裝件,其中,所述電容器包括:第一電極板,該第一電極板形成在所述電容器晶粒的主體上; 介電層,該介電層形成在所述第一電極板上;第二電極板,該第二電極板形成在所述介電層上;以及第一電極和第二電極,該第一電極和該第二電極連接到相應的所述第一電極板和所述第二電極板。
- 根據請求項3所述的半導體封裝件,其中,所述電容器晶粒包括具有提供溝槽的表面的主體;並且其中,所述第一電極板和所述第二電極板以及所述介電層延伸到所述溝槽中。
- 根據請求項4所述的半導體封裝件,其中,所述電容器晶粒的所述主體由矽材料構成。
- 根據請求項3所述的半導體封裝件,其中,所述內部RDL結構包括:第一內部RDL圖案,該第一內部RDL圖案延伸以將所述第一電極連接至所述晶片焊盤中的第一晶片焊盤,其中,所述第一晶片焊盤是用於向所述第二半導體晶片施加電源供應電壓的電源端子;以及第二內部RDL圖案,該第二內部RDL圖案延伸以將所述第二電極連接到所述晶片焊盤中的第二晶片焊盤,其中,所述第二晶片焊盤是用於向所述第二半導體晶片施加接地電壓的接地端子。
- 根據請求項1所述的半導體封裝件,其中,所述第二半導體晶片包括儲存資料的記憶體半導體晶片;並且其中,所述第一半導體晶片包括與所述第二半導體晶片通信以接收或輸出資料的系統上晶片(SoC)。
- 根據請求項1所述的半導體封裝件,該半導體封裝件還包括:黏合層,該黏合層被設置在所述層疊模組與所述第一半導體晶片之間,以將所 述層疊模組附接到所述第一半導體晶片。
- 根據請求項1所述的半導體封裝件,其中,所述導電通孔被形成為垂直地貫穿所述橋接晶粒的主體。
- 根據請求項1所述的半導體封裝件,該半導體封裝件還包括:外部密封劑,該外部密封劑被設置在所述外部RDL結構上,以覆蓋所述第一半導體晶片、所述橋接晶粒和所述層疊模組。
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TW202245212A (zh) * | 2021-05-11 | 2022-11-16 | 群創光電股份有限公司 | 電子裝置 |
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KR20230016485A (ko) * | 2021-07-26 | 2023-02-02 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
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US20240113004A1 (en) * | 2022-09-30 | 2024-04-04 | Advanced Micro Devices, Inc. | Connecting a chiplet to an interposer die and to a package interface using a spacer interconnect coupled to a portion of the chiplet |
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