TWI828018B - 多高度半導體裝置及其製造方法 - Google Patents

多高度半導體裝置及其製造方法 Download PDF

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TWI828018B
TWI828018B TW110145728A TW110145728A TWI828018B TW I828018 B TWI828018 B TW I828018B TW 110145728 A TW110145728 A TW 110145728A TW 110145728 A TW110145728 A TW 110145728A TW I828018 B TWI828018 B TW I828018B
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金世淵
古賓納 哈瑪撒帝
瑞菲爾 羅伊斯
傑克 卡瓦萊羅斯
塔何 甘尼
阿南德 穆爾蒂
里沙 梅安卓
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美商英特爾股份有限公司
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Abstract

一方法，包括：將多閘極裝置的非平面裝置傳導通道形成在基板上，通道包括從基板的表面上之基層所定義的高度尺寸；進行修改，範圍小於通道的整個部位；以及將閘極堆疊形成在通道上，閘極堆疊包括介電材料及閘極電極。設備包括：基板上之非平面多閘極裝置，其包括通道，通道包括定義傳導部位及氧化部位的高度尺寸與配置在通道上的閘極堆疊，閘極堆疊包含介電材料及閘極電極。

Description

多高度半導體裝置及其製造方法
包括具有有著低能帶隙包覆層之通道區的非平面半導體裝置之半導體裝置。
過去幾十年來，積體電路中的特徵的縮放已成為持續成長的半導體工廠背後之驅動力。縮放到越來越小的特徵能夠增加半導體晶片的有限面積上之功能單元的密度。例如，縮小的電晶體尺寸能夠在晶片上結合更多數量的記憶體裝置，使得能夠製造具有更多容量的產品。然而，持續增加的容量之裝置並非沒有問題。最佳化各個裝置的性能之需要變得日益重要。
諸如中央處理單元裝置等未來電路裝置希望具有高性能裝置及低電容二者，整合在單晶粒或晶片中之低功率裝置。目前，三維非平面金屬氧化半導體場效電晶體(MOSFET)通常利用單一高度的鰭狀物。單一高度鰭狀 物有限制設計的傾向並且需要有所犧牲。
A:裝置
B:裝置
H:高度
H1:高度
h:高度
100:結構
110:基板
120:緩衝層
130:鰭狀物
140:介電材料
145:閘極電極區
150:間隔物
155:摻雜劑區
160A:接面區
160B:接面區
165:催化劑層
170:犧牲性充填層
175:氧化部位
180:閘極電極
185:介電層
190:閘極介電層
200:裝置結構
260A:接面區
260B:接面區
275:修改區
300:互連體
302:基板
304:基板
306:球柵陣列
308:金屬互連
310:通孔
400:計算裝置
402:積體電路晶粒
404:處理器
406:晶粒上記憶體
408:通訊晶片
410:揮發性記憶體
412:非揮發性記憶體
414:圖形處理單元
416:數位信號處理器
420:晶片組
422:天線
424:顯示器或觸碰式螢幕顯示器
426:觸碰式螢幕控制器
428:電池
430:羅盤
432:動作感應器
434:揚聲器
436:相機
438:使用者輸入裝置
440:大量儲存體裝置
442:密碼處理器
444:全球定位系統裝置
1300:鰭狀物
1310:鰭狀物
1800:閘極電極
2300:鰭狀物
[圖1]為基板的一部分之俯瞰側視立體圖，即、例如，晶圓上之積體電路晶粒或晶片的一部分且具有形成在基板上之三維電路裝置的一部分。
[圖2]為圖1直通線2-2’的結構之橫剖面側視圖。
[圖3]為圖1直通線3-3’的結構圖。
[圖4]為在裝置的鰭狀物上引進催化劑層之後的圖2之結構圖。
[圖5]為在裝置的鰭狀物上引進催化劑層之後的圖3之結構圖。
[圖6]為移除或凹入催化劑層的一部分之後的圖4之結構圖。
[圖7]為移除或凹入催化劑層的一部分之後的圖5之結構圖。
[圖8]為修改鰭狀物的一部分之後的圖6之結構圖。
[圖9]為修改鰭狀物的一部分之後的圖7之結構圖。
[圖10]為移除催化劑層、在閘極電極區中引進介電材料到鰭狀物的修改部位之高度、及在鰭狀物上引進閘極堆疊之後的圖8之結構圖。
[圖11]為移除催化劑層、在閘極電極區中引進介電材料到鰭狀物的修改部位之高度、及在鰭狀物上引進閘極堆疊之後的圖9之結構圖。
[圖12]為圖11的結構之放大圖以圖示基板上之兩裝置的存在。
[圖13]為裝置結構的另一實施例之剖面圖。
[圖14]為實施一或更多個實施例之互連體。
[圖15]為計算裝置的實施例圖。
此處所說明的實施例係相關於具有目標或預定的鰭狀物或通道高度之非平面半導體裝置(如、三維裝置)以及在基板上製造目標或預定的鰭狀物或通道高度之非平面半導體裝置的方法，其中，此種鰭狀物高度可以是基板上的裝置之多鰭狀物高度的其中之一。在一此種實施例中，非平面裝置的閘極堆疊包圍鰭狀物的通道區(諸如三閘極或鰭式場效電晶體裝置等)。此方法能夠結合在晶片或晶粒上具有不同鰭狀物高度之三維裝置，諸如需要具有低電容的高電流之高性能裝置、較低功率裝置等。
圖1-11說明將非平面多閘極半導體裝置之鰭狀物或通道高度從最初鰭狀物高度修改至不同於最初鰭狀物高度之目標鰭狀物高度的方法或處理。在一實施例中，裝置為三維金屬氧化半導體場效電晶體(MOSFET)，及為隔離裝置或者為複數個套疊式裝置中之一裝置。如所知一般，有關典型的積體電路，在單一基板上可製造N通道電晶體及P通道電晶體二者，以形成互補金屬氧化物半導體(CMOS)積體電路。而且，可製造其他互連以便將此種 裝置整合到積體電路內。
圖1為例如為晶圓上之積體電路晶粒或晶片的一部分之矽或絕緣體上矽晶片(SOI)基板的一部分之俯瞰側視立體圖。尤其是，圖1為包括矽或SOI的基板110之結構100。覆蓋的基板110為選用的緩衝層120。在一實施例中，緩衝層為在一實施例中由生長技術引進基板110上之矽鍺緩衝層。緩衝層120具有幾百奈米(nm)等級之代表性厚度。
在圖1所示之實施例中，配置在緩衝層120之表面上的是電晶體裝置的一部分，諸如N型電晶體裝置或P型電晶體裝置等。在此實施例中，N型或P型電晶體裝置所共同的是配置在緩衝層120的表面(表面125)上之鰭狀物130。用於鰭狀物130的代表性材料為第III-V族半導體材料，諸如銦鎵砷化物(InGaAs)材料等。在一實施例中，鰭狀物130具有大於高度尺寸H的長度尺寸L。代表性長度範圍係在10nm至1毫米(mm)的等級，及代表性高度範圍係在5nm至200nm的等級。鰭狀物130亦具有代表性為等級4-10nm之寬度W。如圖示，鰭狀物130為從基板110的表面125(或者選用地從緩衝層120)延伸之三維本體。如圖1所示之三維本體為矩形本體，但是應明白在此種本體的處理中，由於可利用的工具可能無法達成正矩形及可能導致其他形狀。代表性形狀包括但並不侷限於梯形(如、底邊大於頂邊)及拱形。
在一實施例中，配置在鰭狀物130上的是例如二氧化 矽的介電材料140，或者具有介電常數(k)小於二氧化矽之介電材料(低k介電)。介電材料140被引進至適合閘極電極結構的厚度。圖1為定義閘極電極的區域之間隔物150。典型上，間隔物150連同犧牲性或假閘極電極一起沉積在鰭狀物130的指定通道區上(與此處鰭狀物或通道1300視作同一物)，接著形成接面區及引進介電材料140。因此，為了此實施例的目的，此種犧牲性或假閘極電極事先沉積在閘極電極區145中，及視需要根據習知處理技術來形成接面區，接著介電材料140沉積。在圖1所示之圖解中，諸如藉由蝕刻處理等已移除犧牲性或假閘極，留下暴露在閘極電極區145中之鰭狀物或通道1300。
圖2為圖1直通線2-2’的結構之橫剖面側視圖。圖3為圖1直通線3-3’的結構圖。參考圖2，結構100圖示具有高度H之鰭狀物或通道1300，其配置在接面區160A及接面區160B之間(分別為源極及汲極區)。接面區160A及160B可以是被摻雜的第III-V族化合物材料區。在接面區160A及接面區160B的每一個下面是摻雜劑或植入物區155。接面區及摻雜劑/植入物係根據習知處理來形成。覆蓋或在接面區160A/160B上(如所看見)是定義閘極電極區145之介電材料140及間隔物150。圖3圖示經過閘極電極區145中之鰭狀物或通道1300所取之結構100，及圖示具有高度H之基板上的鰭狀物130。
圖4及圖5分別圖示在引進(如、沉積)催化劑層 165在鰭狀物1300上之後的圖2及圖3之結構，在一實施例中，催化劑層165為被選擇來增強鰭狀物1300的材料之氧化的材料。在一實施例中，增強鰭狀物1300的材料之氧化的材料為被選擇來降低鰭狀物材料的氧化溫度之材料。典型上，半導體的鰭狀物材料將在約1000℃中的氫及氧環境中氧化。在一實施例中，催化劑層165為在低於1000℃的溫度中將促進鰭狀物1300的材料之氧化的材料，諸如600℃或更低(如、500℃)的等級等。催化劑層的適當材料為氧化鋁(Al2O3)。典型上，氧化鋁的催化劑層可以經由原子層沉積處理引進到10nm或更小的等級之厚度。如圖5所示，催化劑層165係保形地沉積在鰭狀物1300上，及在一實施例為閘極電極區145中之基板的基層上(緩衝層120上)。
圖6及圖7分別圖示在移除或凹入催化劑層165的一部分之後的圖4及圖5的結構。在一實施例中，催化劑層165被降低到選定用於鰭狀物1300的修改之高度。典型上，催化劑層165係藉由將犧牲性充填層引進到閘極電極區內、接著乾蝕刻及濕蝕刻組合來予以凹入。如所示，催化劑層165係從其基層到小於鰭狀物的尖頂來形成在鰭狀物1300上。圖7圖示引進到催化劑層165的高度之犧牲性充填層170。用於犧牲性充填層170的適當材料包括可流動的氧化物，諸如碳熱掩模等。如圖7所示，在凹入處理之後，催化劑層165維持在鰭狀物1300的底部位四周。
圖8及圖9分別圖示在藉由例如選擇性蝕刻來移除犧牲性充填層及鰭狀物1300的一部分之修改之後的圖6及圖7的結構。修改在移除犧牲性充填層之後。在此實施例中，修改為鰭狀物1300的下部位之氧化。在一實施例中，鰭狀物1300的一部分之氧化係在低於習知氧化溫度的溫度中執行(如，低於1000℃的溫度)。經由催化劑層165的存在來完成在例如低於材料的氧化溫度之溫度中氧化鰭狀物1300的下部位。圖8及圖9圖示鰭狀物1300的氧化部位175。在修改之後，鰭狀物1300具有有著高度h之主動部位(如、非氧化部位)。在接面區160A及160B底表面的投影下方沒有與之接觸的氧化物材料。
圖10及圖11分別圖示在藉由例如選擇性蝕刻處理來移除催化劑層165及在閘極電極區中引進介電材料到鰭狀物1300之修改部位175的高度之後的圖8及圖9的結構。在閘極電極區中引進介電層185之後，閘極堆疊被引進(如、沉積)在包括閘極介電及閘極電極之結構上。在實施例中，閘極電極堆疊的閘極電極180係由金屬閘極所組成，及閘極介電層190係由具有介電常數大於二氧化矽的介電常數之材料(高K材料)所組成。例如，在一實施例中，閘極介電層190係由諸如但並不侷限於氧化鉿、氮氧化鉿、鉿矽酸鹽、氧化鑭、氧化鋯、鋯矽酸鹽、氧化鉭、鋇鍶鈦酸鹽、鋇鈦酸鹽、鍶鈦酸鹽、氧化釔、氧化鋁、氧化鉛鈧鉭、鉛鋅鈮酸鹽、或其組合等材料所組成。在一實施例中，閘極電極180係由諸如但並不侷限於金屬 氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳、或導電金屬氧化物等金屬層所組成。
如圖10及圖11所示，鰭狀物1300的主動部位具有有著閘極電極180包圍鰭狀物之高度h。如所示，鰭狀物1300的修改高度h係小於例如圖2及3所示之鰭狀物1300的開始高度H。
圖12圖示圖11的結構之放大圖以圖示基板上之兩裝置的存在。裝置A為圖11所示之裝置。裝置B為包括通道或鰭狀物1310及閘極電極1800之第二三維或非平面多閘極裝置。裝置A具有修改鰭狀物高度h。同一基板上之裝置B具有大於裝置A的修改鰭狀物高度h之鰭狀物高度H(鰭狀物1310)。因此，根據此處所說明之處理，圖解用以整合同一基板上之不同鰭狀物高度的裝置之方法。裝置A具有典型上短於裝置B的鰭狀物或通道。典型上，裝置A可被用在需要較低電容及想要較少漏流之應用中。一例子為用於圖形應用之裝置。裝置B典型上可被用於想要高電流之高性能應用。在圖式中，裝置A具有約為裝置B的鰭狀物高度之尺寸的一半之鰭狀物高度h。應明白，鰭狀物高度可被修改至任何想要的高度，包括高度的一半、高度的四分之三、高度的四分之一等。
圖13圖示裝置結構的另一實施例之橫剖面圖。在此實施例中，諸如三維鰭式場效電晶體等非平面半導體利用接面區下面的修改區以隔離裝置的通道。參考圖13，裝 置結構200包括鰭狀物2300作為通道區。鰭狀物2300具有鰭狀物高度H1，以及接面區260A及接面區260B在鰭狀物的相反側上。除了具有植入物或摻雜劑區在各個接面區下面之外，裝置還包括修改區275。在一實施例中，修改區275為可如上文參考圖2-11所說明一般形成之氧化區。在一實施例中，鰭狀物2300的修改僅在其基層上，使得鰭狀物(通道)具有約最大的目標鰭狀物高度。在此實施例中，結構的氧化不僅包括鰭狀物2300的底部位，而且還包括接面區260A及260B下面的氧化區。應明白，在其他實施例中，若想要的話，亦可修改(如、氧化)鰭狀物2300較大的部位。
在另一實施例中，除了根據上文參考圖2-11所說明之處理來形成裝置結構200以外，在形成接面區260A及260B之前可進行鰭狀物的底部位及接面區下面的區域之氧化。
圖14圖解一包括一或更多個實施例之互連體。互連體300為用於橋接第一基板302至第二基板304之中間基板。第一基板302可以是例如積體電路晶粒。第二基板304可以是例如記憶體模組、電腦母板、或另一積體電路晶粒。通常，互連體300的目的係用於延伸連接到更寬的間距或用於重新路由連接到不同連接。例如，互連體300可耦合積體電路晶粒到可隨後耦合到第二基板304之球柵陣列(BGA)306。在一些實施例中，第一及第二基板302/304係裝附至互連體300的相反側。在其他實施例 中，第一及第二基板302/304係裝附至互連體300的同一側。在其他實施例中，三或更多個基板係藉由互連體300互連。
互連體300係由環氧樹脂、玻璃纖維強化環氧樹脂、陶瓷材料、或諸如聚醯亞胺等聚合物材料來形成。在其他實施中，互連體係由包括上述用於半導體基板中的相同材料之交替的堅硬或撓性材料所形成，諸如矽、鍺、及其他第III-V族及第IV族材料等。
互連體包括金屬互連308及通孔310，包括但並不侷限於矽導通孔(TSV)312。互連體300可另包括崁入式裝置314，崁入式裝置包括被動及主動裝置二者。此種裝置包括但並不侷限於電容器、解偶電容器、電阻器、電導體、熔絲、二極體、變壓器、感應器、及靜電放電(ESD)裝置。亦可將諸如射頻(RF)裝置、功率放大器、電力管理裝置、天線、陣列、感應器、及MEMS裝置等更複雜的裝置形成在互連體300上。
根據實施例，可在製造互連體300時使用此處所揭示之設備或處理。
圖15圖解根據一實施例之計算裝置400。計算裝置400可包括一些組件。在一實施例中，這些組件係裝附至一或更多個母板。在另一實施例中，這些組件被製造至除了母板以外的單一單晶片系統(SoC)晶粒上。計算裝置400中的組件包括但並不侷限於積體電路晶粒402及至少一通訊晶片408。在一些實施例中，通訊晶片408被製造 作為積體電路晶粒402的部分。積體電路晶粒402可包括處理器404及晶粒上記憶體406(通常被使用作為快取記憶體)，它們可藉由諸如崁入式DRAM(eDRAM(崁入式動態隨機存取記憶體))或自旋轉移力矩記憶體(STTM或STTM-RAM(自旋轉移力矩隨機存取記憶體))等技術來提供。
計算裝置400可包括可以或不用實體上及電耦合到母板或者製造在SoC晶粒內之其他組件。這些其他組件包括但並不侷限於揮發性記憶體410(如、DRAM)、非揮發性記憶體412(如、ROM或快閃記憶體)、圖形處理單元414(GPU)、數位信號處理器416、密碼處理器442(執行硬體內的加密演算法之專門處理器)、晶片組420、天線422、顯示器或觸碰式螢幕顯示器424、觸碰式螢幕控制器426、電池428或其他電源、功率放大器(未圖示)、全球定位系統(GPS)裝置444、羅盤430、運動協同處理器或感應器432(其可包括加速儀、迴轉儀、及羅盤)、揚聲器434、相機436、使用者輸入裝置438(諸如鍵盤、滑鼠、電子筆、及觸碰式墊板等)、及大量儲存體裝置440(諸如硬碟機、小型碟(CD)、數位多用途碟(DVD)、諸如此類等)。
通訊晶片408能夠無線通訊以轉移資料至及自計算裝置400。”無線”一詞及其衍生字可被用於說明電路、裝置、系統、方法、技術、通訊頻道等等，它們可經由非固態媒體經由使用已調變電磁輻射來通訊資料。此一詞未暗 示相關裝置未包含任何線路，但是在一些實施例中可不包含線路。通訊晶片408可實施一些無線標準或協定的任一個，包括但並不侷限於Wi-Fi(IEEE 802.11，家用)、WiMAX(IEEE 802.16，家用)、IEEE 802.20、長期演進技術(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生物，以及被指定作3G、4G、5G及以上之任何其他無線協定。計算裝置400可包括複數個通訊晶片408。例如，第一通訊晶片408專屬於較短範圍無線通訊，諸如Wi-Fi及藍芽等，而第二通訊晶片408專屬於較長範圍無線通訊，諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他等。
計算裝置400的處理器404包括一或更多個裝置，諸如電晶體或金屬互連等，它們係根據此處所說明的實施例所形成，包括具有為特別應用所裁剪的鰭狀物高度(如、處理器404上之不同的鰭狀物高度)之三維多閘極電晶體裝置。”處理器”一詞可意指任何裝置或裝置的部位，其處理來自暫存器及/或記憶體的電子資料以將那電子資料轉換成可儲存在暫存器及/或記憶體中之其他電子資料。
通訊晶片408亦可包括一或更多個裝置，諸如電晶體或金屬互連等，它們係根據上文所說明的實施例所形成，包括包括修改或裁剪的鰭狀物高度之三維電晶體裝置。
在其他實施例中，框覆在計算裝置400內之另一組件可包含一或更多個裝置，諸如電晶體或金屬互連等，它們 係根據上文所說明的實施例所形成，包括包括修改或裁剪的鰭狀物高度之三維電晶體裝置。
在各種實施例中，計算裝置400可以是膝上型電腦、小筆電、筆記型電腦、超輕薄筆電、智慧型電話、平板電腦、個人數位助理(PDA)、迷你行動型個人電腦、行動電話、桌上型電腦、伺服器、列印機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位視頻記錄器。在其他實施中，計算裝置400可以是處理資料之任何其他電子裝置。
例子
下面例子係有關於實施例。
例子1為包括將多閘極裝置之非平面傳導通道形成在基板上之方法，通道包括從基板的表面上之基層所定義的高度尺寸；進行修改，範圍小於通道的整個部位；以及將閘極堆疊形成在通道上，閘極堆疊包含介電材料及閘極電極。
在例子2中，例子1的修改包括氧化，及在氧化小於通道的整個部位之前，方法包括將一層催化劑材料形成在通道上，其中，催化劑材料包含具有將增強該通道的材料之氧化的特性之材料。
在例子3中，例子2的氧化通道包括將通道經過低於通道的材料之氧化溫度的溫度。
在例子4中，例子2之催化劑材料的此層係僅形成在 通道的基層中。
在例子5中，將例子2之催化劑材料的此層形成在從通道的基層至低於通道之頂點的高度之通道上。
在例子6中，例子5之催化劑材料的此層係形成在通道之長度的一半上。
在例子7中，例子3的形成催化劑層包括：將催化劑層沉積在通道的整個高度尺寸上；及在沉積之後，方法包括從通道之高度尺寸的一部分移除催化劑材料的此層。
在例子8中，例子1或例子2的通道係配置在基板上的接面區之間，方法另包括氧化接面區下面之基板的一部分。
在例子9中，在形成閘極堆疊之前，例子1或例子2的方法包括：將鄰近通道的介電材料引進到等同通道的氧化部位之高度。
例子10為方法，包括將多閘極裝置的非平面傳導通道形成在基板上；氧化通道的一部分，所氧化的部分係藉由從低於通道的總高度尺寸之基板的表面所測量之通道的高度尺寸來定義；以及將閘極堆疊形成在通道上，閘極堆疊包含介電材料及閘極電極。
在例子11中，在氧化小於通道的整個部位之前，例子10的方法包括將一層催化劑材料形成在通道上，其中，催化劑材料包括具有將增強通道的材料之氧化的特性之材料。
在例子12中，例子11的氧化通道包括將通道經過低 於通道的材料之氧化溫度的溫度。
在例子13中，例子11的將催化劑材料的此層形成在通道上包括：將催化劑材料的此層沉積在通道的整個部位上；及在氧化之前，方法另包括移除催化劑材料之此層的一部分。
在例子14中，例子13的移除催化劑材料之此層的一部分包括：從通道之總高度尺寸的至少一半移除此層。
在例子15中，例子10-14的任一個之通道係配置在基板上的接面區之間，方法另包括氧化接面區下面之基板的一部分。
在例子16中，在形成閘極堆疊之前，例子10-15的任一個之方法包括：將鄰近通道的介電材料引進到等同通道的氧化部位之高度。
例子17為設備，包括基板上之非平面多閘極裝置，其包括通道，通道包括定義傳導部位及修改部位的高度尺寸與配置在通道上的閘極堆疊，閘極堆疊包含介電材料及閘極電極。
在例子18中，例子17的閘極堆疊係僅配置在通道的傳導部位上。
在例子19中，例子17或例子18的通道之修改部位係配置在基板與通道的傳導部位之間。
在例子20中，例子17或例子18的多閘極裝置為第一多閘極裝置，設備另包括第二多閘極裝置，第二多閘極裝置包含通道，通道包含具有高度尺寸大於第一多閘極裝 置的該傳導部位之高度尺寸的傳導部位。
在例子21中，將例子17或例子18的通道之修改部位氧化。
在例子22中，例子17或例子18的多閘極裝置另包括通道之相對側上的每一個上之接面區，將接面區下面的區域氧化。
上述圖解實施的說明(包括摘要中所說明者)並不想成為全面性的或者將本發明侷限於所揭示的精確形式。儘管為了圖解此處揭示例如發明的特定實施及用於發明的例子，但是精於相關技術之人士應明白，在此範疇內可有各種同等修改。
按照上述詳細說明可進行這些修改。下面申請專利範圍所使用的語詞不應被闡釋成將本發明侷限於說明書及申請專利範圍中所揭示的特定實施。而是，本發明的範疇係完全由下面申請專利範圍來決定，申請專利範圍係根據所建立的申請專利解釋條例來闡釋。
100:結構
110:基板
120:緩衝層
125:表面
130:鰭狀物
140:介電材料
145:閘極電極區
150:間隔物

Claims (16)

  1. 一種製造多高度半導體裝置的方法，包含：在基板上形成第一非平面多閘極裝置，該第一非平面多閘極裝置包括第一通道，該第一通道包含具有第一高度尺寸的第一傳導部位；在該第一通道上形成催化劑材料的層，其中，該催化劑材料包含具有增強該第一通道的材料氧化的特性的材料，以降低該第一通道的氧化溫度；氧化該第一通道的整個部位的一部分以形成具有修改高度尺寸的該第一通道的氧化部位，其中，該第一傳導部位係設置於該第一通道的該氧化部位之上，該第一通道係配置在該基板上的接面區之間，其中，該第一通道之相對側的每一側上之該接面區的底表面在該第一通道的該第一傳導部位的底表面下方，且其中，該第一通道的該氧化部位具有頂表面；將第一閘極堆疊形成在該第一通道上，該第一閘極堆疊包含閘極介電材料及第一閘極電極，其中，該第一閘極堆疊具有與該第一通道的該氧化部位的該頂表面共平面的底表面；在該基板上形成第二非平面多閘極裝置，該第二非平面多閘極裝置包括第二通道，該第二通道包含具有第二高度尺寸的第二傳導部位；以及將第二閘極堆疊形成在該第二非平面多閘極裝置的該 第二通道上，其中，該第一通道的該修改高度尺寸小於該第二通道的該第二高度尺寸，且其中，該第二通道的該第二高度尺寸大於該第一通道的該第一高度尺寸。
  2. 如請求項1之方法，其中，氧化包含將該第一通道經過低於該第一通道的材料之氧化溫度的溫度。
  3. 如請求項1之方法，其中，該催化劑材料的層係僅形成在該第一通道的基層上。
  4. 如請求項1之方法，其中，將該催化劑材料的層形成在從該第一通道的該基層至低於該第一通道之頂點的高度之該第一通道上。
  5. 如請求項4之方法，其中，將該催化劑材料的該層形成在該第一通道之長度的一半上。
  6. 如請求項1之方法，其中，形成該催化劑材料的層包含：將該催化劑層沉積在該第一通道的整個高度尺寸上，及在沉積之後，該方法包含從該第一通道之該整個高度尺寸的一部分移除該催化劑材料的層。
  7. 如請求項1之方法，其中，在形成該第一閘極堆疊之前，該方法包含將鄰近該第一通道的介電材料引進到等同該第一通道的該氧化部位之高度。
  8. 一種製造多高度半導體裝置的方法，包含：在基板上形成第一非平面多閘極裝置，該第一非平面 多閘極裝置包括第一通道，該第一通道包含具有第一高度尺寸的第一傳導部位；在該第一通道上形成催化劑材料的層，其中，該催化劑材料包含具有增強該第一通道的材料氧化的特性的材料，以降低該第一通道的氧化溫度；氧化該第一通道的整個部分的一部分以形成該第一通道的氧化部位，該第一通道的該氧化部位係藉由從小於該第一通道的總高度尺寸之該基板的表面所測量之該第一通道的修改高度尺寸來定義，其中，該第一通道係配置在該基板上的接面區之間，其中，該第一通道之相對側的每一側上之該接面區的底表面在該第一通道的該第一傳導部位的底表面下方，該第一傳導部位係設置於該氧化部位之上，且其中，該第一通道的該氧化部位具有頂表面；將第一閘極堆疊形成在該第一通道上，該第一閘極堆疊包含閘極介電材料及第一閘極電極，其中，該第一閘極堆疊具有與該第一通道的該氧化部位的該頂表面共平面的底表面；在該基板上形成第二非平面多閘極裝置，該第二非平面多閘極裝置包括第二通道，該第二通道包含具有第二高度尺寸的第二傳導部位；以及將第二閘極堆疊形成在該第二非平面多閘極裝置的該第二通道上，其中，該第一通道的該修改高度尺寸小於該第二通道的該第二高度尺寸，且其中，該第二通道的該第二高度尺 寸大於該第一通道的該第一高度尺寸。
  9. 如請求項8之方法，其中，氧化包含將該通道經過低於該第一通道的材料之氧化溫度的溫度。
  10. 如請求項8之方法，其中，將該催化劑材料的該層形成在該第一通道上包含將該催化劑材料的層沉積在該第一通道的整個部位上，及在氧化之前，該方法進一步包含移除該催化劑材料的層的一部分。
  11. 如請求項10之方法，其中，移除該催化劑材料的層的一部分包含從該第一通道之該總高度尺寸的至少一半移除該層。
  12. 如請求項8之方法，其中，在形成該閘極堆疊之前，該方法包含將鄰近該第一通道的介電材料引進到等同該第一通道的該氧化部位之高度。
  13. 一種多高度半導體裝置，包含：基板上之非平面多閘極裝置，其包含第一通道與配置在該第一通道上的第一閘極堆疊，該第一通道包含具有第一高度尺寸的第一傳導部位及具有第一修改高度尺寸的第一修改部位，其中，該第一傳導部位係設置於該第一修改部位之上，該第一修改部位具有頂表面，其中，該第一修改部位係透過在該第一通道上形成催化劑材料的層並且氧化該第一通道的整個高度尺寸的一部分來形成，該第一閘極堆疊包含閘極介電材料及第一閘極電極，其中，該第一閘極堆疊具有與該第一修改部位的該頂表面共平面的底表面，其中，該催化劑材料包含具有增強該第一通道的材料 氧化的特性的材料，以降低該第一通道的氧化溫度，其中，該第一非平面多閘極裝置還包含該第一通道之相對側的每一側上之接面區，且其中，該第一通道之相對側的每一側上之該接面區的底表面在該第一通道的該第一傳導部位的底表面下方；在該基板上的第二非平面多閘極裝置，該第二非平面多閘極裝置包括第二通道，該第二通道包含具有第二高度尺寸的第二傳導部位；以及配置在該第二非平面多閘極裝置的該第二通道上的第二閘極堆疊，其中，該第一通道的該第一修改高度尺寸小於該第二通道的該第二高度尺寸，且其中，該第二通道的該第二高度尺寸大於該第一通道的該第一高度尺寸。
  14. 如請求項13之裝置，其中，該第一閘極堆疊係僅配置在該第一通道的該第一傳導部位上。
  15. 如請求項13之裝置，其中，該第一通道的該第一修改部位係配置在該基板與該第一通道的該第一傳導部位之間。
  16. 如請求項13之裝置，其中，該第一通道的該第一修改部位係被氧化。
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US20180151702A1 (en) 2018-05-31
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