TWI823962B - 電漿處理期間減少微粒形成之卡盤的保護層 - Google Patents
電漿處理期間減少微粒形成之卡盤的保護層 Download PDFInfo
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- TWI823962B TWI823962B TW108123568A TW108123568A TWI823962B TW I823962 B TWI823962 B TW I823962B TW 108123568 A TW108123568 A TW 108123568A TW 108123568 A TW108123568 A TW 108123568A TW I823962 B TWI823962 B TW I823962B
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- protective layer
- chuck
- microelectronic workpiece
- processing chamber
- microelectronic
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- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
本文敘述諸實施例,以藉由在諸如電漿蝕刻製程(例如反應離子蝕刻(RIE)製程)及/或電漿沉積製程的電漿處理之前,將一層(例如厚膜)沉積於卡盤(諸如靜電卡盤(ESC))的表面上,減少在微電子工件之電漿處理期間形成不期望的微粒。此層用作潤滑劑或保護塗層,以減少或最小化微電子工件(例如,半導體晶圓)和卡盤之間的實體接觸。實體接觸中之此減少會減少微電子工件背面的刮擦,並減少相關之不希望微粒的形成,這些微粒可輸送至微電子工件之正面並造成缺陷且降低良率。如此,所揭示的實施例改善用於電漿蝕刻及/或沉積製程之微粒(PA)性能參數。
Description
(相關申請案)本申請案主張以下共同待審之臨時申請案的優先權:2018年7月6日提交之標題為「蝕刻處理期間的保護塗層」之美國臨時專利申請案序號第62 / 694,641號、和2018年9月17日提交的標題為「電漿處理期間減少微粒形成之卡盤的保護層」之美國臨時專利申請案序號第62 / 732,235號,其全部以引用的方式併入本文中。
本揭示內容有關用於製造微電子工件的方法,且尤其是有關蝕刻微電子工件上之材料層的方法。
在微電子工件內之裝置形成典型涉及與形成、圖案化、和移除基板上的多個材料層有關之一系列製造技術。為了滿足當前和下一代半導體裝置的物理和電氣規格,需要處理流程以減小特徵尺寸,同時保持製程品質參數。
用於高級處理節點,藉由將每單位面積之更多裝置堆疊進入微電子工件,裝置最小化已變成降低製造成本的一主要常規方法。隨著裝置臨界尺寸已減小到奈米大小,控制微粒形成和減少微粒雜質對於維持期望之裝置性能和良率目標已變得越來越重要,尤其是相對於電漿蝕刻製程。
圖1A(先前技術)提供使用卡盤108(諸如靜電卡盤(ESC))的常規電漿蝕刻製程之示範實施例100,以將微電子工件106保持在處理室102內。對於實施例100,諸如半導體晶圓的微電子工件106遭受如在視圖122中所顯示之電漿處理。電漿處理可為譬如於處理室102內施行的電漿蝕刻製程及/或電漿沉積製程。如藉由箭頭110所指示,在電漿處理步驟期間發生溫度轉變。於此溫度轉變期間,如視圖124中所示,由熱膨脹中之差異而產生了不期望的微粒(PA)。這些不期望之微粒可被輸送至微電子工件106的正面,並在所形成之裝置中造成缺陷。
更詳細地查看視圖122,於諸如電漿蝕刻的電漿製程或沉積製程期間,微電子工件106耦接至卡盤108。在將ESC用作卡盤108之情況下,微電子工件106利用於ESC上感應的靜電荷耦接至ESC,其將微電子工件106保持在適當位置。於電漿製程期間,點燃電漿氣體以在處理室102內形成電漿104,且於微電子工件106上施行一或更多蝕刻及/或沉積步驟。
更詳細地查看視圖124,顯示微電子工件106(例如,晶圓)和卡盤108(例如,ESC)之間的實體接觸可造成不期望之微粒(諸如微粒134)的形成。尤其是,由於在微電子工件106和卡盤108內之材料的熱膨脹係數中之差異,通常在用於電漿蝕刻及/或沉積製程(諸如反應性離子蝕刻(RIE)製程)的溫度轉變期間發生微粒形成。如藉由方框120及相關箭頭所示,在溫度轉變期間於熱膨脹中之差異造成微電子工件106之背面與卡盤108的正面之間的摩擦及/或運動。不期望之微粒的形成源自這些條件。例如,微粒134可藉由微電子工件106和卡盤108之間的刮擦所形成。
一旦形成,諸如微粒134之不期望的微粒(PA)可在處理室102內輸送至微電子工件106之正面。此微粒傳送至正面上典型以二方式發生。一方式係由於在微電子工件106和卡盤108之間施加惰性氣體以改善熱傳導。此惰性氣體會將微粒(諸如微粒134)推入處理室,且這些微粒可能掉落至微電子工件106的表面上。另一方式是由於處理室與卡盤108和微電子工件106間之間隙之間的壓力差。典型地,此間隙包括具有壓力範圍為1-5 Torr之氦(He)氣,而處理室典型具有1-10毫托(mTorr)的壓力範圍。壓力差趨向於將諸如微粒134之微粒從高壓輸送到低壓。微粒的輸送增加抵達微電子工件106之正面的微粒雜質之數量。所得到的高PA計數導致微電子工件106之表面內的缺陷,且導致所製造之微電子工件的裝置良率降低。
相對於方框130更詳細地顯示諸如微粒134之不期望的微粒之形成,其代表微電子工件106之背面與卡盤108的正面之間的相互作用之一部分。如所示,卡盤108的表面之不平坦部分132可相對於微電子工件106的背面由於摩擦和運動而造成微粒產生。由於在微電子工件106及卡盤108內之材料用的熱膨脹係數中之差異,此摩擦及運動係在溫度轉變增加。一旦形成,諸如微粒134的不期望之微粒(PA)可於處理室102內輸送到微電子工件106的正面,如藉由箭頭136所指示。
圖1B(先前技術)顯示一示範代表性實施例150,其針對圖1A之傳統蝕刻製程的抵達微電子工件106正面之大量不期望的微粒(現有技術)。對於此範例,發現約有162個微粒撞擊微電子工件106之表面。
本文敘述諸實施例,以藉由在諸如電漿蝕刻製程(例如反應離子蝕刻(RIE)製程)及/或電漿沉積製程的電漿處理之前,將一層(例如厚膜)沉積於卡盤(諸如靜電卡盤(ESC))的表面上,減少在微電子工件之電漿處理期間形成不期望的微粒。此層用作潤滑劑或保護塗層,以減少或最小化微電子工件(例如,半導體晶圓)和卡盤之間的實體接觸。此實體接觸之減少會減少微電子工件背面的刮擦,並減少相關之不希望微粒的形成,這些微粒可能輸送至微電子工件之正面並造成缺陷且降低良率。如此,所揭示的實施例改善用於電漿蝕刻及/或沉積製程之微粒(PA)性能參數。也可實現不同或附加的特徵、變型、和實施例,且同樣可利用相關之系統和方法。
用於一實施例,揭示一種處理微電子工件的方法,其包括在處理室內的卡盤之表面上形成一層,將微電子工件定位於卡盤的表面上,及在微電子工件上施行蝕刻製程或沉積製程之至少一者。
於另外的實施例中,所述施行步驟包括蝕刻製程。在進一步實施例中,蝕刻製程包括電漿蝕刻製程。於又進一步實施例中,電漿蝕刻製程包括反應離子蝕刻(RIE)製程。
在另外之實施例中,所述施行步驟包括沉積製程。於進一步實施例中,沉積製程包括電漿沉積製程。
在另外的實施例中,所述方法還包括於卡盤和微電子工件之間注入惰性氣體以促進熱傳導。在另外的實施例中,卡盤為靜電卡盤。於另外之實施例中,微電子工件為半導體晶圓。
在另外的實施例中,所述層建構成減少微電子工件的背面與卡盤之間的接觸。於進一步實施例中,減少之接觸導致在微電子工件的背面中之刮擦比沒有所述層時發生的刮擦少,且所述刮痕傾向於形成可輸送到微電子工件之正面的微粒。在進一步實施例中,此方法藉由使用所述層將微電子工件之正面上的微粒數減少達1%至80%。
於另外之實施例中,所述形成步驟包括使用沉積製程來沉積所述層。在進一步實施例中,沉積製程包括電漿沉積製程。於進一步實施例中,所述層包括碳基膜。在又進一步實施例中,電漿沉積製程使用氣體化學材料,其包括以下至少一種:CF4
、CH4
、CH2
F2
、CO2
、CO、CHF3
、CH3
F、C4
F8
、或C4
F6
。於其他實施例中,所述層包括矽基膜。在進一步實施例中,電漿沉積製程使用包括SiCl4
的氣體化學材料。
於另外之實施例中,所述施行步驟包括一或更多溫度轉變。在另外的實施例中,此方法還包括施行清潔製程以從卡盤之表面移除所述層。
如本文所敘述,在電漿處理(諸如電漿蝕刻處理(例如RIE處理)及/或電漿沉積處理)期間,於使用卡盤固持微電子工件之前,將一層沉積在卡盤(諸如靜電卡盤(ESC))的表面上。此附加材料層(例如,薄膜)於卡盤上之此沉積用作保護塗層或潤滑劑,以減少或防止微電子工件(例如,半導體晶圓)和卡盤(例如,ESC)之間的實體接觸和磨損。在實體接觸以及晶圓背面的相關刮擦上的減少,減少不期望之微粒的形成,這些微粒可能輸送至晶圓的正面。不期望之微粒數量的此減少使缺陷減少並改善裝置良率。這樣,所揭示之實施例改善諸如電漿蝕刻製程、RIE製程、及/或沉積製程的電漿製程之微粒(PA)性能。在仍然利用本文所敘述的製程技術之同時,亦可達成其他優點和實施例。
針對蝕刻處理室,已發現由於諸如半導體晶圓的微電子工件之邊緣上的溫度轉變,在電漿蝕刻製程(諸如反應性離子蝕刻(RIE)製程)期間,微粒(PA)的形成可顯著地增加。於電漿沉積處理期間亦可發生類似之特定形成。此不期望的微粒形成主要是由於微電子工件用之材料和卡盤用的材料之間的熱膨脹係數中之差異而在溫度轉變期間造成。例如,熱膨脹係數中的差異通常導致於溫度轉變期間的晶圓背面刮擦,且此刮擦已被識別為導致不期望之微粒雜質的形成。尤其是,晶圓背面之刮擦導致微粒形成,且這些微粒通常從晶圓的背面輸送至晶圓之正面。大量的微粒雜質通常會藉由增加表面缺陷並減少所製造裝置之裝置良率來降低晶圓正面上的缺陷性能。另外,晶圓背面刮擦和相關聯之微粒形成還傾向於將污染引入晶圓傳送模組,並藉此傾向於將污染引入到電漿蝕刻/沉積處理設備之後的其他處理設備。
用於本文所敘述之實施例,減少與微電子工件(例如,半導體晶圓)的背面之實體接觸和刮擦。如此,還減少不期望的微粒之形成以及這些微粒雜質向微電子工件的正面之輸送。如本文所敘述,經過在施行電漿蝕刻/沉積製程之前於卡盤(例如,ESC)的表面上形成諸如薄膜之一層來達成微粒雜質中的此減少。此層用作潤滑劑或保護性塗層,以最小化微電子工件與卡盤之間的實體接觸,藉此減少或消除由於微電子工件之背面的刮擦之不期望的微粒的形成。藉由減少缺陷並增加使用電漿蝕刻/沉積製程所製造之微電子工件的裝置良率,微粒數量之此減少導致顯著改善微粒性能參數。
圖2A提供示範實施例200,在此於將微電子工件106耦接至卡盤108上以進行電漿蝕刻及/或沉積處理之前,在卡盤108上形成保護層202。例如,可使用電漿沉積製程將薄膜沉積至卡盤108的表面上。於形成保護層202之後,將微電子工件106耦接至卡盤108。
用於實施例200,如視圖204中所示,使微電子工件106(諸如半導體晶圓)遭受電漿處理。電漿處理可例如為在處理室102內施行的電漿蝕刻製程及/或電漿沉積製程。如藉由箭頭110所指示,於電漿處理步驟期間發生溫度轉變。在如圖206所示之此溫度轉變期間,與圖1A(先前技術)中的先前解決方案相比,由於保護層202大大地減少或消除不期望之微粒的形成。
更詳細地查看視圖204,在諸如電漿蝕刻製程(例如,RIE製程)及/或電漿沉積製程之電漿處理期間,微電子工件106耦接至卡盤108。在將ESC用作卡盤108之情況下,微電子工件106使用在ESC上感應的靜電荷耦接至ESC,其將微電子工件106固持於適當位置中。在電漿蝕刻/沉積製程期間,點燃電漿氣體以於處理室102內形成電漿104,並在微電子工件106上施行一或更多蝕刻及/或沉積製程步驟。
更詳細地查看視圖206,其顯示藉由形成保護層202來減少微電子工件106(例如,晶圓)和卡盤108(例如,ESC)之間的實體接觸。尤其是,儘管於微電子工件106和卡盤108內之材料的熱膨脹係數中之差異,但是在電漿製程的溫度轉變期間以先前解決方法通常發生的微粒形成被大大地減少或消除。如方框120和相關箭頭所表示,在溫度轉變期間之熱膨脹中的差異仍然存在,但微粒形成藉由保護層202所抑制。所得到之低微粒(PA)數量導致微電子工件106的表面內之缺陷減少以及所製造的微電子工件之裝置良率改善。
如本文所敘述,層202用作保護塗層,以減少由於微電子工件106和卡盤108之間的實體接觸而形成之不期望的微粒之形成。例如,在溫度轉變期間,由於熱膨脹係數中的差異,微電子工件106之背面刮擦藉由保護層202的存在而減少。如與傳統製程相比,用於不期望之微粒的微粒數量因此大幅地減少。此低微粒數量導致減少由於微粒雜質引起之缺陷,並增加裝置良率。例如,已發現與傳統製程相比,經過在電漿處理之前將保護層202沉積於卡盤108上,可達成在微電子工件正面上的微粒數量減少1%至80%。
在標註方框230中更詳細地顯示不期望之微粒的形成上之減少的代表圖,其代表微電子工件106之背面與卡盤108的正面之間的相互作用之一部分。如所顯示,保護層202有效地保護微電子工件106的背面免於被卡盤108之表面的不平坦部分132所刮擦。因此,即使在溫度轉變期間於卡盤108和微電子工件106之間的相對運動由於熱膨脹係數中之差異而增加,減少或消除不期望的微粒形成。
亦進一步注意的是,通常在微電子工件106和卡盤108之間的間隙中注入諸如氦氣(He)之惰性氣體。如此,預期惰性氣體232(例如He)會進入保護層202和微電子工件106之間的間隙中。此惰性氣體232用於維持卡盤108和微電子工件106之間的熱傳導。由於此目的,預期用於此惰性氣體232之高壓條件。
圖2B顯示示範代表性實施例,其用於減少微電子工件106的正面上之不期望的微粒,這使用本文所敘述之保護層技術來達成,以減少針對微電子工件106的實體接觸和背面刮擦。針對此範例,發現約44個微粒已撞擊微電子工件106之表面。與圖1B(先前技術)的先前解決方案相比,微粒總數減少27%。
圖3係示範實施例300之製程圖,在此保護層用於減少在電漿處理期間由於背面刮擦而形成的不期望之微粒。在方塊302中,於處理室內的卡盤表面上形成一層。在方塊304中,將微電子工件定位於卡盤之表面上。例如,在使用ESC作為卡盤的情況下,微電子工件使用於ESC上感應之靜電荷加以耦接至ESC,其將微電子工件固持在適當位置中。於方塊306中,在微電子工件上施行電漿製程。用於一實施例,電漿製程係諸如RIE製程及/或其他蝕刻製程的電漿蝕刻製程。用於一實施例,電漿製程為沉積製程。再者,電漿蝕刻及/或沉積製程可包括一或更多溫度轉變。於仍然利用本文所敘述之製程技術的同時,也可使用附加及/或不同之製程步驟。
藉由在卡盤上方形成保護層,所揭示的實施例減少用於微電子工件之基板的背面與卡盤之間的接觸。如本文所敘述,此減少之接觸導致在溫度轉變期間於基板背面中的刮痕較少。相反地,在用於先前解決方法之溫度轉變期間的背面刮擦造成微粒之形成,所述微粒通常輸送至基板的正面,從而增加缺陷。與不包括在電漿處理之前於卡盤上形成保護層的方法相比,本文所述之方法建構成將微粒數減少1%至80%。使用本文所述的在微電子工件和卡盤之間形成保護層的技術,也可達成其他特徵和優點。
圖4A-D提供示範實施例之橫截面視圖,在此一層202形成於處理室內的卡盤108之表面上。如本文所述,此層202在卡盤108和微電子工件106之間提供保護塗層,藉此減少於蝕刻/沉積處理期間的不期望之微粒產生。
圖4A提供示範實施例401的橫截面視圖,在此一層202形成於卡盤108之表面上,以提供潤滑劑或保護塗層。部分地,保護層202還有效地平滑化並覆蓋針對卡盤108的粗糙/不平坦表面132。用於一示範實施例,在施行實際的電漿製程之前,將選定的氣體化學材料注入處理室,且施行薄膜之電漿輔助式沉積,以於卡盤108(例如,ESC)的表面上形成保護層202。除了在卡盤108上形成保護層202之外,此薄膜或其他材料層也可沉積於處理室上。如本文所敘述,此保護層202用作保護塗層或潤滑劑,以減少或防止晶圓與ESC之間的實體接觸及/或磨損。
用於一實施例,藉由電漿沉積製程和電漿氣體化學方法將保護層202沉積在卡盤108(例如,ESC)之表面上,以沉積保護層,諸如碳基膜、矽基膜、及/或其他保護膜。用於形成碳基膜的氣體化學材料可包括以下之一或更多個:CF4
、CH4
、CH2
F2
、CO2
、CO、CHF3
、CH3
F、C4
F8
、C4
F6
、及/或其他所期望的含碳化合物或氣體。再者,可在氣體化學材料內包括用於形成碳基膜之額外氣體,諸如以下的一或更多個:SF6
、SO2
、O2
、Ar、He、N2
、Cl2
、HBr、NF3
、及/或其他化合物或氣體。用於形成矽基膜之氣體化學材料可包括以下的一或更多個:SiCl4
及/或其他期望之含矽化合物或氣體。再者,可在氣體化學材料內包括用於形成矽基膜的額外氣體,諸如以下之一或更多個:CF4
、CH2
F2
、SF6
、CO2
、CO、O2
、Ar、He、N2
、CHF3
、CH3
F、Cl2
、HBr、C4
F8
、C4
F6
、NF3
、及/或其他所期望的化合物或氣體。
圖4B提供示範實施例402之橫截面視圖,在此微電子工件106耦接至於處理室內的卡盤108。例如,在將層202形成於卡盤108上之後,可將微電子工件106移入處理室,耦接至卡盤108,並準備用於電漿處理。在卡盤108為ESC之情況下,微電子工件106也靜電地耦接至卡盤108並藉由其所固持。然而,如本文所述,微電子工件106實體地就坐於層202的頂部,諸如一沉積的薄膜上,所述薄膜用作潤滑劑或保護性塗層。再者,通常在微電子工件106和卡盤108之間的間隙中注入諸如氦氣(He)之惰性氣體。如此,預期惰性氣體232(例如He)將位於保護層202和微電子工件106之間的間隙中。此惰性氣體232用於保持卡盤108和微電子工件106之間的導熱性。由於此目的,預期用於此惰性氣體232之高壓條件。
圖4C提供示範實施例403的橫截面視圖,在此如藉由箭頭410所示,使微電子工件106遭受電漿處理。如本文所述,層202用作保護塗層,以減少或防止微電子工件106及卡盤108的表面之間的實體接觸,藉此減小或最小化對微電子工件106背面之刮擦。例如,由於在藉由箭頭410所指示的電漿處理之溫度轉換期間之膨脹係數中的差異,可發生這些刮擦。藉由減小或最小化所述刮擦,減少由微電子工件106和卡盤108之間的實體接觸所形成之微粒的數量。
圖4D提供示範實施例404之橫截面視圖,在此微電子工件106的正面上已減少不期望之微粒420。如本文所述,來自背面刮擦而形成的不期望之微粒中的減少顯著地減少輸送至微電子工件106之正面的微粒之數量。減少不期望的微粒420抵達微電子工件106之正面的數量或微粒數減少缺陷並改善良率。
應當指出,圖4A-D提供一示範實施例,且還可使用附加的及/或不同的製程步驟。例如,於處理微電子工件106之後,還可使用附加的腔室清潔製程來移除材料層202(例如,薄膜)並重置腔室條件用於後續之微電子工件的處理。例如,取決於所沉積者,此腔室清潔製程可用於從卡盤108之表面及/或從處理室移除所沉積的薄膜。可對每一經處理之微電子工件106重複此腔室清潔處理程序。在仍然利用本文所敘述的技術之同時,還可實現其他變型。
注意,可使用一或更多沉積製程來形成本文所述的材料層。例如,可使用化學氣相沉積(CVD)、電漿增強CVD(PECVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、及/或其他沉積製程來實施的一或更多沉積。對於電漿沉積製程,可使用前驅物氣體混合物,包括但不限於碳氫化合物、碳氟化合物、或含氮之碳氫化合物,並在諸多壓力、功率、流量、和溫度條件下與一或更多稀釋氣體(例如,氬氣、氮氣等)結合使用。可使用光學微影術、極紫外(EUV)微影術、及/或其他微影術製程來實現相對於PR層的微影術製程。可使用電漿蝕刻製程、放電蝕刻製程、及/或其他期望之蝕刻製程來實施蝕刻製程。例如,可使用含有碳氟化合物、氧、氮、氫、氬、及/或其他氣體的電漿來實施電漿蝕刻製程。另外,可控制用於製程步驟之操作變數,以確保在通孔形成期間達成用於通孔的CD目標參數。操作變數可包括例如腔室溫度、腔室壓力、氣體之流速、在產生電漿時施加至電極組件的頻率及/或功率、及/或用於處理步驟之其他操作變數。在仍然利用本文所敘述的技術之同時,也可實現變型。
注意,於整個本說明書中對「一實施例」或「實施例」的引用意指與實施例結合地敘述之特定特徵、結構、材料、或特性包括在本發明的至少一實施例中,但是不表示它們存在於每一實施例中。因此,在整個本說明書中於各處出現之片語「在一實施例中」或「於實施例中」不一定是意指本發明的相同實施例。再者,於一或更多實施例中,能以任何合適之方式來結合特定的特徵、結構、材料、或特性。在其他實施例中,可包括諸多附加層及/或結構及/或可省略所敘述之特徵。
如本文所使用,「微電子工件」通常意指待根據本發明處理的物體。微電子工件可包括裝置、尤其是半導體或其他電子裝置之任何材料部分或結構,且例如可為基底基板結構、諸如半導體基板、或在基底基板結構上或重疊基底基板結構的層、諸如薄膜。因此,工件不意欲受限於圖案化或未圖案化之任何特定的基底結構、下層、或上覆層,而非設想包括任何此類層或基底結構、及諸層及/或基底結構之任何組合。下面的敘述可參考特定類型之基板,但這僅是出於說明性目的、而不是限制。
如本文所使用,「基板」一詞意指並包括在其上形成材料之基底材料或構造。將理解的是,基板可包括單一材料、不同材料之複數層、其中具有不同材料或不同結構的區域之一或更多層等。這些材料可包括半導體、絕緣體、導體、或其組合。例如,基板可為半導體基板、於支撐結構上的基底半導體層、在其上形成有一或更多層、結構、或區域之金屬電極或半導體基板。基板可為常規的矽基板或包含半導體材料層之其他塊狀基板。如本文所使用的,「塊狀基板」一詞不僅意指且包括矽晶圓,而且包括絕緣體上矽(「SOI」)基板、諸如藍寶石上矽(「SOS」)基板、和玻璃上矽(「SOG」)基板、基底半導體基礎結構上之矽外延層、及諸如矽鍺、鍺、砷化鎵、氮化鎵、和磷化銦的其他半導體或光電材料。基板可為已摻雜或未摻雜的。
於諸多實施例中敘述用於處理微電子工件之系統和方法。相關領域的技術人員將認識到,可在沒有一或更多特定細節之情況下,或於具有其他替換及/或附加方法、材料、或部件的情況下實踐諸多實施例。在其他場合中,未詳細顯示或敘述熟知之結構、材料、或操作,以避免使本發明的諸多實施例之各態樣不清楚。類似地,出於解釋之目的,闡述具體的數目、材料和組構,以便提供對本發明之透徹理解。雖然如此,可在沒有具體細節的情況下實踐本發明。再者,應當理解,各圖面中所顯示之諸多實施例係說明性代表圖,並且不一定按比例繪製。
鑑於本敘述,所敘述的系統和方法之進一步修改和替代實施例對於本領域的技術人員將為顯而易見的。因此,將認識到,所敘述之系統和方法不受這些示範配置所限制。應當理解,本文所顯示和敘述的系統和方法之形式將被視為示範實施例。可在諸實施例中進行諸多改變。因此,儘管本文參考特定實施例敘述本發明,但是可於不脫離本發明的範圍之情況下進行諸多修改和變化。因此,說明書和附圖應認為是說明性的而不是限制性的,且此等修改意欲包括在本發明之範圍內。再者,本文針對特定實施例所敘述的任何益處、優點、或問題之解決方案均不意欲解釋為任何或所有申請專利範圍的關鍵、必需、或必要特徵或要素。
100:實施例
102:處理室
104:電漿
106:微電子工件
108:卡盤
110:箭頭
120:盒子
122:視圖
124:視圖
130:方框
132:不平坦部分
134:微粒
136:箭頭
150:實施例
200:實施例
202:保護層
204:視圖
206:視圖
230:標註方框
232:惰性氣體
300:實施例
401:實施例
402:實施例
403:實施例
404:實施例
410:箭頭
420:不期望之微粒
藉由參考以下結合附圖進行的敘述,可獲得對本發明及其優點之更完整的理解,其中,相像之參考數字指示相像的特徵。然而,應當注意,附圖僅說明所揭示概念之示範性實施例,且因此不應被認為限制其範圍,因為所揭示的概念可允許其他等效之實施例。
圖1A(先前技術)提供用於電漿製程的示範實施例,其使用卡盤將微電子工件固持在處理室內,於此熱膨脹係數中之差異導致不期望的微粒之形成增加。
圖1B(先前技術)顯示用於圖1A(先前技術)的傳統蝕刻製程之大量不期望的微粒抵達晶圓之正面的示範代表性實施例。
圖2A提供示範實施例,在此於將微電子工件耦接至卡盤以進行電漿蝕刻及/或沉積處理之前,在處理室內的卡盤上形成保護層。
圖2B顯示一示範代表性實施例,其用於減少使用圖2A之保護層技術所達成的微電子工件之正面上的不期望之微粒。
圖3係示範實施例的製程圖,在此保護層形成於處理室內之卡盤上,以減少在電漿處理期間由背面刮擦而形成的不期望之微粒。
圖4A-D提供示範性實施例的橫截面視圖,在此保護層形成於卡盤之表面上,且用於減少電漿處理期間的不期望之微粒產生。
Claims (16)
- 一種處理微電子工件之方法,包含:在一處理室內的一卡盤之一表面上形成一保護層,其中該保護層係使用氣體化學材料加以形成,該氣體化學材料包括以下至少一種:CF4、CH4、CH2F2、CO2、CO、CHF3、CH3F、C4F8、或C4F6;在該處理室之中,將一微電子工件定位於該卡盤的該表面上所形成的該保護層之上,使得該保護層係與該微電子工件的背面表面直接實體接觸;及在該處理室之中,在該保護層形成在該卡盤的該表面上的情況下,在該微電子工件上施行蝕刻製程或沉積製程其中至少一者,其中,該保護層係在該微電子工件與該卡盤之間提供潤滑的一薄膜,在處理該微電子工件之後,在該處理室之中施行一清潔製程,以從該卡盤的該表面移除該保護層,其中,該保護層係第一保護層,該微電子工件係第一微電子工件,且該清潔製程係第一清潔製程,該方法更包含:在該處理室之中施行該第一清潔製程之後,在該處理室內的該卡盤之該表面上形成一第二保護層;在該處理室之中,將一第二微電子工件定位於該卡盤的該表面上所形成的該第二保護層之上; 在該第二保護層形成在該處理室之中該卡盤的該表面上的情況下,在該第二微電子工件上施行蝕刻製程或沉積製程其中至少一者;及在處理該第二微電子工件之後,在該處理室之中施行一第二清潔製程,以從該卡盤的該表面移除該第二保護層。
- 如申請專利範圍第1項之方法,其中該施行步驟包含蝕刻製程。
- 如申請專利範圍第2項之方法,其中該蝕刻製程包含電漿蝕刻製程。
- 如申請專利範圍第3項之方法,其中該電漿蝕刻製程包含反應離子蝕刻(RIE)製程。
- 如申請專利範圍第1項之方法,更包含在該卡盤的表面上所形成的該保護層與該微電子工件的該背面表面之間的一間隙中注入惰性氣體,以促進熱傳導。
- 如申請專利範圍第1項之方法,其中該卡盤為靜電卡盤。
- 如申請專利範圍第1項之方法,其中該微電子工件為半導體晶圓。
- 如申請專利範圍第1項之方法,其中該保護層建構為減少該微電子工件的該背面表面及該卡盤之間的接觸。
- 如申請專利範圍第8項之方法,其中該減少的接觸導致在該微電子工件之該背面表面中的刮擦比在沒有該保護層的狀況下發生之刮擦少,且該等刮擦傾向於形成可輸送至該微電子工件的正面之微粒。
- 如申請專利範圍第9項之方法,其中該方法藉由使用該保護層將該微電子工件的正面上之微粒數減少達1%至80%。
- 如申請專利範圍第1項之方法,其中該施行步驟包含由於在該微電子工件的一種以上材料與該卡盤的一種以上材料之間的熱膨脹係數的差異所致之一或更多溫度轉變,且其中由該保護層所提供的潤滑在該一或更多溫度轉變期間降低在該微電子工件與該卡盤之間的摩擦。
- 如申請專利範圍第1項之方法,其中該形成步驟包含使用一第二沉積製程來在該卡盤的該表面上沉積該保護層,及其中,該第二沉積製程係以下的一者:電漿沉積製程、化學氣相沉積(CVD)製程、原子層沉積(ALD)製程、及物理氣相沉積(PVD)製程。
- 如申請專利範圍第1項之方法,其中該氣體化學材料更包括以下至少一種:SF6、SO2、O2、Ar、He、N2、Cl2、HBr、或NF3。
- 如申請專利範圍第12項之方法,其中該第二沉積製程係一電漿沉積製程,該電漿沉積製程使用包含SiCl4的氣體化學材料。
- 一種處理微電子工件之方法,包含:在一處理室內的一卡盤之一表面上形成一保護層;在該處理室之中,將一微電子工件定位於該卡盤的該表面上所形成的該保護層之上,使得該保護層係與該微電子工件的背面表面直接實體接觸;在該處理室之中,在該保護層形成在該卡盤的該表面上的情況下,在該微電子工件上施行蝕刻製程或沉積製程其中至少一者;其中,該保護層係在該微電子工件與該卡盤之間提供潤滑的一薄膜,且其中形成在該卡盤的該表面上的該保護層包含碳基膜, 在處理該微電子工件之後,在該處理室之中施行一清潔製程,以從該卡盤的該表面移除該保護層,其中,該保護層係第一保護層,該微電子工件係第一微電子工件,且該清潔製程係第一清潔製程,該方法更包含:在該處理室之中施行該第一清潔製程之後,在該處理室內的該卡盤之該表面上形成一第二保護層;在該處理室之中,將一第二微電子工件定位於該卡盤的該表面上所形成的該第二保護層之上;在該第二保護層形成在該處理室之中該卡盤的該表面上的情況下,在該第二微電子工件上施行蝕刻製程或沉積製程其中至少一者;及在處理該第二微電子工件之後,在該處理室之中施行一第二清潔製程,以從該卡盤的該表面移除該第二保護層。
- 一種處理微電子工件之方法,包含:在一處理室內的一卡盤之一表面上形成一保護層;在該處理室之中,將一微電子工件定位於該卡盤的該表面上所形成的該保護層之上,使得該保護層係與該微電子工件的背面表面直接實體接觸;在該處理室之中,在該保護層形成在該卡盤的該表面上的情況下,在該微電子工件上施行蝕刻製程或沉積製程其中至少一者;其中,該保護層係在該微電子工件與該卡盤之間提供潤滑的一薄膜,且 其中該保護層係使用一電漿沉積製程加以形成,該電漿沉積製程使用氣體化學材料,其包括以下至少一種:CF4、CH4、CH2F2、CO2、CO、CHF3、CH3F、C4F8、或C4F6,在處理該微電子工件之後,在該處理室之中施行一清潔製程,以從該卡盤的該表面移除該保護層,其中,該保護層係第一保護層,該微電子工件係第一微電子工件,且該清潔製程係第一清潔製程,該方法更包含:在該處理室之中施行該第一清潔製程之後,在該處理室內的該卡盤之該表面上形成一第二保護層;在該處理室之中,將一第二微電子工件定位於該卡盤的該表面上所形成的該第二保護層之上;在該第二保護層形成在該處理室之中該卡盤的該表面上的情況下,在該第二微電子工件上施行蝕刻製程或沉積製程其中至少一者;及在處理該第二微電子工件之後,在該處理室之中施行一第二清潔製程,以從該卡盤的該表面移除該第二保護層。
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US20020109955A1 (en) * | 2000-12-11 | 2002-08-15 | Shinsuke Masuda | Electrostatic chuck and method of manufacturing the same |
US20030047283A1 (en) * | 2001-09-10 | 2003-03-13 | Applied Materials, Inc. | Apparatus for supporting a substrate and method of fabricating same |
US20070212816A1 (en) * | 2006-03-08 | 2007-09-13 | Tokyo Electron Limited | Substrate processing system |
US20100112820A1 (en) * | 2008-11-04 | 2010-05-06 | E.I. Du Pont De Nemours And Company | Method for membrane protection during reactive ion/plasma etching processing for via or cavity formation in semiconductor manufacture |
TW201543610A (zh) * | 2014-02-26 | 2015-11-16 | Tokyo Electron Ltd | 靜電夾頭、載置台、電漿處理裝置、以及靜電夾頭之製造方法 |
US20170140970A1 (en) * | 2015-11-17 | 2017-05-18 | Applied Materials, Inc. | Substrate support assembly with deposited surface features |
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US20020109955A1 (en) * | 2000-12-11 | 2002-08-15 | Shinsuke Masuda | Electrostatic chuck and method of manufacturing the same |
US20030047283A1 (en) * | 2001-09-10 | 2003-03-13 | Applied Materials, Inc. | Apparatus for supporting a substrate and method of fabricating same |
US20070212816A1 (en) * | 2006-03-08 | 2007-09-13 | Tokyo Electron Limited | Substrate processing system |
US20100112820A1 (en) * | 2008-11-04 | 2010-05-06 | E.I. Du Pont De Nemours And Company | Method for membrane protection during reactive ion/plasma etching processing for via or cavity formation in semiconductor manufacture |
TW201543610A (zh) * | 2014-02-26 | 2015-11-16 | Tokyo Electron Ltd | 靜電夾頭、載置台、電漿處理裝置、以及靜電夾頭之製造方法 |
US20170140970A1 (en) * | 2015-11-17 | 2017-05-18 | Applied Materials, Inc. | Substrate support assembly with deposited surface features |
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