TWI814262B - 晶片置中式扇出面板級封裝結構及其封裝方法 - Google Patents

晶片置中式扇出面板級封裝結構及其封裝方法 Download PDF

Info

Publication number
TWI814262B
TWI814262B TW111107166A TW111107166A TWI814262B TW I814262 B TWI814262 B TW I814262B TW 111107166 A TW111107166 A TW 111107166A TW 111107166 A TW111107166 A TW 111107166A TW I814262 B TWI814262 B TW I814262B
Authority
TW
Taiwan
Prior art keywords
layer
chip
metal
polyimide
winding
Prior art date
Application number
TW111107166A
Other languages
English (en)
Other versions
TW202326949A (zh
Inventor
藤島浩幸
張簡上煜
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Publication of TW202326949A publication Critical patent/TW202326949A/zh
Application granted granted Critical
Publication of TWI814262B publication Critical patent/TWI814262B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Packaging Frangible Articles (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本發明係一種晶片置中式扇出面板級封裝結構及其封裝方法，該晶片置中式扇出面板級封裝結構包含一繞線層、一形成於該繞線層上並包含多個柱狀開口及一晶片開口之聚醯亞胺層、多個分別穿經對應的該柱狀開口設置於該繞線層上之金屬柱、一穿經該晶片開口設置於該繞線層上之晶片及一形成於該聚醯亞胺層上並包覆該些金屬柱及該晶片之封膠層；其中該聚醯亞胺層係用於消除該封裝的翹曲，由於該聚醯亞胺層係形成於該封膠體內，且該晶片係穿經該晶片開口直接設置於該繞線層上，因此，額外增加一聚醯亞胺層並不會增加該晶片置中式扇出面板級封裝結構的高度。

Description

晶片置中式扇出面板級封裝結構及其封裝方法
本發明係關於一種封裝結構，特別指一種晶片置中式扇出面板級封裝結構。
請參閱圖6及圖7，係現有的二晶片置中式扇出面板級封裝結構93、93’，如圖6所示的該晶片置中式扇出面板級封裝結構93係包含一上繞線層931、一下繞線層932、一封膠層933以及多個晶片94，其中該些晶片94係由該封膠層933包覆；該些晶片94及該封膠層933係由該上及下繞線層931、932包夾；因此，該些晶片94係設置於該晶片置中式扇出面板級封裝結構93的中間位置。
如圖6所示，各該晶片94的一主動面941係朝下並電連接該下繞線層932，故該下繞線層932(例如5P4M重佈線層)的層數係多於該上繞線層931(例如2P1M重佈線層)；因此，該下繞線層932的收縮力F1係大於該上繞線層的收縮力F2，此一收縮力的差異造成該晶片置中式扇出面板級封裝結構93向下彎曲；另一方面，如圖7所示，各該晶片94的該主動面941係朝上並電連接該上繞線層931，故該上繞線層931(例如3P2M重佈線層)的層數係多於該下繞線層 932(例如1P1M重佈線層)，因此，該上繞線層931的收縮力F2係大於該下繞線層932的收縮力F1，此一收縮力的差異造成該晶片置中式扇出面板級封裝結構93’向上彎曲。
綜上所述，該上繞線層及該下繞線層之間的層數差異會造成該晶片置中式扇出面板級封裝結構的翹曲。當該晶片置中式扇出面板級封裝結構的高度必須維持不變時，也無法透過在較少層數之繞線層中增加膠層的方式來克服翹曲問題；因此，現有的該晶片置中式扇出面板級封裝結構有必要進行改良。
有鑑於上述晶片置中式扇出面板級封裝結構的翹曲的問題，本發明的主要目的係提出一種消除雙繞線層的層數差異所造成之翹曲的晶片置中式扇出面板級封裝結構及其封裝方法。
為達上述目的，本發明所使用的主要技術手段係令上述晶片置中式扇出面板級封裝結構包含：一第一繞線層；一第一聚醯亞胺層，係形成於該第一繞線層上，並包含：一第一晶片開口；以及多個柱狀開口；多個金屬柱，係形成於該第一繞線層上，並分別穿經該些柱狀開口；一晶片，係穿經該第一晶片開口並設置於該第一繞線層上，其包含：一主動面； 一背面，係相對於該主動面；多個金屬凸塊，係形成於該主動面上；以及一黏著層，係形成於該背面及該第一繞線層之間；一第一封膠層，係形成於該第一聚醯亞胺層上，並包覆該些金屬柱以及該晶片；以及一第二繞線層，係形成於該第一封膠層上，並分別電連接至該些金屬柱以及該晶片的該些金屬凸塊，其中該第二繞線層的層數係多於該第一繞線層。
由上述說明可知，該第一聚醯亞胺層係用於消除該晶片置中式扇出面板級封裝結構的翹曲；該第一聚醯亞胺層係形成於該晶片置中式扇出面板級封裝結構內部，且該晶片係穿經該第一晶片開口並直接設置於該第一繞線層上；如此，本發明額外增加該第一聚醯亞胺層，可有效地消除該晶片置中式扇出面板級封裝結構的翹曲，且不會使該晶片置中式扇出面板級封裝結構的高度增加。
為達上述目的，本發明所使用的主要技術手段係令上述晶片置中式扇出面板級封裝方法包含以下步驟：(a)於一第一載板上形成一第一繞線層；(b)於該第一繞線層上形成一第一聚醯亞胺層；(c)於該第一聚醯亞胺層貫穿形成多個第一晶片開口及多個柱狀開口；(d)於該第一繞線層上形成多個金屬柱，該些金屬柱係分別穿經該些柱狀開口，並與該第一繞線層電連接； (e)將多個晶片分別穿經該些第一晶片開口設置於該第一繞線層上，其中各該晶片的一背面係由一黏著層設置於該第一繞線層上，且各該晶片的一主動面係形成多個金屬凸塊；(f)於該第一聚醯亞胺層上形成一第一封膠層以包覆該些金屬柱及該些晶片；(g)對該第一封膠層進行一減薄製程，直至該些金屬柱及各該晶片的該些金屬凸塊自該第一封膠層外露；(h)於該第一封膠層上形成一第二繞線層，並令該第二繞線層分別與該些金屬柱及該些晶片的該些金屬凸塊電連接；以及(i)進行一切割步驟，以分離各該晶片置中式扇出面板級封裝結構。
由上述說明可知，該第一聚醯亞胺層係於設置該些晶片前形成於該第一繞線層上，因此，該第一聚醯亞胺層係形成於該晶片置中式扇出面板級封裝結構內以消除其翹曲；此外，由於該些晶片係同樣穿經各該第一晶片開口並直接設置於該第一繞線層上，於該晶片置中式扇出面板級封裝結構內額外增加該第一聚醯亞胺層時，該晶片置中式扇出面板級封裝結構的高度維持不變，可於消除翹曲的同時維持電子元件尺寸。
10:晶片置中式扇出面板級封裝結構
10’:晶片置中式扇出面板級封裝結構
10”:晶片置中式扇出面板級封裝結構
20:第一繞線層
201:底部
21:聚醯亞胺壓合層
22:金屬層
221:金屬墊
30:第一聚醯亞胺層
30a:第二聚醯亞胺層
31:柱狀開口
32:第一晶片開口
33:接墊開口
34:第二晶片開口
40:晶片
41:堆疊晶片組
411:主動面
412:背面
42:金屬柱
421:突出端
422:平端
43:金屬凸塊
431:自由端
44:黏著層
50:第一封膠層
50a:第二封膠層
51:上表面
60:第二繞線層
61:金屬層
62:金屬層
63:外凸塊
70:錫球
80:第三繞線層
81:接墊
90:第一載板
91:黏膠層
92:第二載板
93:晶片置中式扇出面板級封裝結構
93’:晶片置中式扇出面板級封裝結構
931:上繞線層
932:下繞線層
933:封膠層
94:晶片
941:主動面
圖1：本發明晶片置中式扇出面板級封裝結構的第一實施例的一剖面圖。
圖2：本發明晶片置中式扇出面板級封裝結構的第二實施例的一剖面圖。
圖3：本發明晶片置中式扇出面板級封裝結構的第三實施例的一剖面圖。
圖4A至4H：本發明第一實施例封裝方法的各步驟的一剖面圖。
圖5A至5J：本發明第三實施例封裝方法的各步驟的一剖面圖。
圖6：現有技術的晶片置中式扇出面板級封裝結構的一剖面圖。
圖7：現有技術的另一晶片置中式扇出面板級封裝結構的一剖面圖。
本發明針對該晶片置中式扇出面板級封裝結構進行改良，以下謹以多個實施例配合圖式詳加說明本發明技術內容。
首先請參閱圖1，係本發明晶片置中式扇出面板級封裝結構的第一實施例，該晶片置中式扇出面板級封裝結構10係包含一第一繞線層20、一第一聚醯亞胺層30、多個金屬柱42、一晶片40、一第一封膠層50以及一第二繞線層60。
上述第一繞線層20係可為一重佈線層，於本實施例，如圖1所示，該第一繞線層20係包含一聚醯亞胺壓合層21以及一金屬層22，因此該第一繞線層20可為一1P1M重佈線層(其中1P代表該聚醯亞胺壓合層21為單層，1M代表該金屬層22為單層)，但並不以此為限；該金屬層22係包含多個金屬墊221，且多個錫球70係分別設置於各該金屬墊221上。
上述第一聚醯亞胺層30係形成於該第一繞線層20上並包含多個柱狀開口31及一第一晶片開口32，其中該些柱狀開口31係貫穿形成於該第一聚醯亞胺層30，使得該第一繞線層20的該些金屬墊221外露；該第一晶片開口32係同樣貫穿形成於該第一聚醯亞胺層30；於本實施例，該些柱狀開口31係圍繞該第一晶片開口32。
上述多個金屬柱42係形成於該第一繞線層20上，並分別穿經該些柱狀開口31與該第一繞線層20的該金屬層22電連接；於本實施例，各該金屬柱42係包含一突出端421以及一平端422；又於本實施例，各該突出端421係直接與外露於該第一聚醯亞胺層30的各該金屬墊221電連接；該突出端421具有一第一直徑D1，其中該第一直徑D1係小於該平端422的第二直徑D2，又該突出端421的該第一直徑D1係匹配與其對應的該第一聚醯亞胺層30的該柱狀開口31的直徑D1。
上述晶片40係穿經該第一聚醯亞胺層30的該第一晶片開口32並設置於該第一繞線層20上；於本實施例，該晶片40包含一主動面411以及一背面412，其中多個金屬凸塊43形成於該主動面411上，且一黏著層44形成於該背面412上；該晶片40的該背面412透過該黏著層44設置於該第一繞線層20，因此，該黏著層44位於該晶片40的該背面412與該第一繞線層20之間；該晶片40小於與其對應的該第一晶片開口32，因此，一間隙G形成於該晶片40與其對應的該第一聚醯亞胺層30之間；又於本實施例，形成於該主動面411的各該金屬凸塊43的一自由端431與各該金屬柱42的該平端422共平面。
上述第一封膠層50係形成於該第一聚醯亞胺層30上，並包覆該些金屬柱42、該晶片40以及該晶片40的該些金屬凸塊43，但不包覆各該金屬凸塊43的該自由端431以及各該金屬柱42的該平端422；該第一封膠層50的一上表面51係與各該金屬凸塊43的該自由端431以及各該金屬柱42的該平端422共平面；於本實施例，上述間隙G亦由該第一封膠層50填滿。
上述第二繞線層60係形成於該第一封膠層50上，具體而言，該第二繞線層60係形成於該第一封膠層50的該上表面51、各該金屬凸塊43的該自 由端431以及各該金屬柱42的該平端422上；於本實施例，該第二繞線層60可為一重佈線層，例如3P2M重佈線層，但並不以此為限，且該第二繞線層60的層數多於該第一繞線層20；其中靠近該第一封膠層50之該第二繞線層60的其中一金屬層61直接與各該金屬凸塊43及各該金屬柱42連接，如此，該第二繞線層60與該些金屬凸塊43及該些金屬柱42電連接；多個外凸塊63係進一步形成於該第二繞線層60上，並與遠離該第一封膠層50之該第二繞線層60的其中一金屬層62連接。
請參閱圖2，係本發明晶片置中式扇出面板級封裝結構的第二實施例，該晶片置中式扇出面板級封裝結構10’的結構係與圖1的該晶片置中式扇出面板級封裝結構10大致相同，惟於本實施例，該晶片置中式扇出面板級封裝結構10’係進一步於該第一繞線層20的一底部201形成一第二聚醯亞胺層30a，並部份包覆該些金屬墊221，故該第一繞線層20係位於該第一聚醯亞胺層30及該第二聚醯亞胺層30a之間，其中該第二聚醯亞胺層30a的厚度小於各該錫球70的高度。又於本實施例，該第一及第二聚醯亞胺層30、30a同樣用以消除該晶片置中式扇出面板級封裝結構10’的翹曲。
請參閱圖3，係本發明晶片置中式扇出面板級封裝結構的第三實施例，該晶片置中式扇出面板級封裝結構10”的結構係與圖2的該晶片置中式扇出面板級封裝結構10’大致相同，惟於本實施例，該晶片置中式扇出面板級封裝結構10”的該第一繞線層20不包含如圖2的該些錫球70，因此，該第一繞線層20的該金屬墊221外露於該第一繞線層20的該底部201；又於本實施例，該晶片置中式扇出面板級封裝結構10”係進一步包含一第三繞線層80，該第三繞線層80係形成於該第一繞線層20的該底部201上，並電連接至該第一繞線層20 的該些金屬墊221，且該第三繞線層80包含多個接墊81；一第二聚醯亞胺層30a係形成於該第三繞線層80上，且多個接墊開口33及一第二晶片開口34形成於該第二聚醯亞胺層30a，其中該第二晶片開口34係對應該第一聚醯亞胺層30的該第一晶片開口32；於本實施例，一堆疊晶片組41穿經該第二聚醯亞胺層30a的該第二晶片開口34並設置於該第三繞線層80上；且該些接墊開口33係分別對應該第三繞線層80的該些接墊81，故該疊晶片組41係透過連接線通過該接墊開口33，以電連接至相對應的該第三繞線層80的各該接墊81；一第二封膠層50a係形成於該第二聚醯亞胺層30a，以包覆該堆疊晶片組41。
再請參閱圖4A至4H，係本發明晶片置中式扇出面板級封裝結構的第一實施例的封裝方法，其包含如下所述之步驟(a)至(i)。
於步驟(a)，如圖4A及4B所示，先準備一第一載板90，再於該第一載板90上形成一第一繞線層20；於本實施例，一黏膠層91係形成於該第一載板90上，再將該第一繞線層20形成於該黏膠層91上；又於本實施例，該第一繞線層20係一1P1M重佈線層，即包含一聚醯亞胺壓合層21以及一金屬層22，其中該金屬層22係形成於該黏膠層91上並包含多個金屬墊221，而該聚醯亞胺壓合層21係形成於該金屬層22上，且部分的該金屬墊221係外露於該聚醯亞胺壓合層21。
於步驟(b)，如圖4B所示，一第一聚醯亞胺層30係形成於該第一繞線層20上；於本實施例，該第一聚醯亞胺層30係形成於該第一繞線層20的該聚醯亞胺壓合層21上。
於步驟(c)，如圖4B所示，於該第一聚醯亞胺層30對應部分外露的該金屬墊221貫穿形成多個柱狀開口31，又於該第一聚醯亞胺層30貫穿形成多個第一晶片開口32，且該些柱狀開口31圍繞對應的各該第一晶片開口32。
於步驟(d)，如圖4C所示，於該第一繞線層20上形成多個金屬柱42，該些金屬柱42係分別穿經該些柱狀開口31，並與該第一繞線層20電連接；於本實施例，各該金屬柱42的一端係直接形成於與其對應並部份外露的該金屬墊221，因此，該金屬柱42係電連接至該第一繞線層20，由於各該金屬柱42的直徑係大於各該柱狀開口31，該金屬柱42伸入該柱狀開口31的一端的直徑係小於該金屬柱42的直徑。
於步驟(e)，如圖4C及4D所示，將多個晶片40分別穿經對應的該些第一晶片開口32並設置在該第一繞線層20上；於本實施例，各該晶片40的一背面412係由一黏著層44設置於該第一繞線層20，並於各該晶片40的一主動面411形成多個金屬凸塊43；其中各該晶片40係小於各該第一晶片開口32，因此，多個間隙G係分別形成於該些晶片40及其對應之該些第一開口32之間。
於步驟(f)，如圖4E所示，於該第一聚醯亞胺層30上形成一第一封膠層50以包覆該些金屬柱42、該些晶片40以及該些晶片40的該些金屬凸塊43；同時，該第一封膠層50亦將各該間隙G填滿。
於步驟(g)，如圖4E所示，對該第一封膠層50進行一減薄製程，直至該些金屬柱42及各該晶片40的該些金屬凸塊43自該第一封膠層50外露。
於步驟(h)，如圖4F所示，係於該第一封膠層50上形成一第二繞線層60，並令該第二繞線層60分別與該些金屬柱42及該些晶片40的該些金屬凸塊43電連接，於本實施例，該第二繞線層60可為一3P2M重佈線層，其中3P代 表三層聚醯亞胺壓合層，而2M代表二層金屬層61、62，並且各該聚醯亞胺壓合層及各該金屬層61、62係交錯且依序形成於該第一封膠層50上，其中靠近該第一封膠層50的其中一金屬層61係電連接至自該第一封膠層50外露的各該金屬柱42及各該晶片40的各該金屬凸塊43；多個外凸塊63係形成於該第二繞線層60上，並與遠離該第一封膠層50的其中一金屬層62電連接；再如圖4G所示，該第一載板90係自該第一繞線層20移除，以令該些金屬墊221外露，再進一步如圖4H所示，令多個錫球70分別設置於相對應的各該金屬墊221。於另一實施例，即對如圖2所示之該晶片置中式扇出面板級封裝結構10’進行封裝時，係可於設置該些錫球70於各該金屬墊221前，令一第二聚醯亞胺層30a進一步形成於該第一繞線層20上，但該第二聚醯亞胺層30a不包覆該第一繞線層20的該些金屬墊221，然後再令該些錫球70貫穿該第二聚醯亞胺層30a設置於對應的該些金屬墊221上。
於步驟(i)，如圖4H所示，係沿著多個切割道L進行一切割步驟，以分離出如圖1所示的多個晶片置中式扇出面板級封裝結構10。
再請參閱圖5A至5J，係本發明該晶片置中式扇出面板級封裝結構10”之封裝方法的第三實施例，其包含步驟(a)至(m)；如圖5A至5E，本實施例的封裝方法的步驟(a)至(g)係與圖4A至4E的第一實施例封裝方法的步驟(a)至(g)相同，惟不同之處在於步驟(h)至(m)；以下詳細說明本發明第三實施例的步驟(h)至(m)。
於步驟(h)，如圖5F所示，係同樣於該第一封膠層50上形成該第二繞線層60，但如圖4F所示的該些外凸塊63係不形成於該第二繞線層60上。
於步驟(I)，如圖5G所示，係將該第二繞線層60與一第二載板92接觸，並移除該第一載板90以令該第一繞線層20外露，其中該第一繞線層20的該些金屬墊221係自該第一繞線層20外露。
於步驟(j)，如圖5H及圖5I所示，係於該第一繞線層20上形成一第三繞線層80，其中該第三繞線層80係包含多個接墊81，再於該第三繞線層80上形成一第二聚醯亞胺層30a，並於該第二聚醯亞胺層30a貫穿形成多個接墊開口33，以令該些接墊81外露，且對應該第一聚醯亞胺層30的該些第一晶片開口32貫穿形成多個第二晶片開口34。
於步驟(k)，如圖5J所示，係將多個堆疊晶片組41穿經對應的該第二晶片開口34設置於該第三繞線層80上，再將各該堆疊晶片組41透過連接線通過該些接墊開口33與相對應的該第三繞線層80的各該接墊81電連接。
於步驟(l)，如圖5J所示，係於該第二聚醯亞胺層30a上形成一第二封膠層50a，並包覆該些堆疊晶片組41。
於步驟(m)，如圖5J所示，係沿著多個切割道L進行一切割步驟，以分離出如圖3所示的多個晶片置中式扇出面板級封裝結構10”。
綜合上述說明可知，本發明的晶片置中式扇出面板級封裝結構結構中包含層數不同的第一及第二繞線層，故主要將該第一聚醯亞胺層係於設置該些晶片前形成於該第一繞線層上，以縮小第一及第二繞線層的層數差；因此，透過形成該第一聚醯亞胺層於該晶片置中式扇出面板級封裝結構結構內以消除翹曲；此外，由於該些晶片係同樣穿經各該第一晶片開口並直接設直於該第一繞線層上，於該晶片置中式扇出面板級封裝結構內額外增加該第一聚醯亞 胺層時，該晶片置中式扇出面板級封裝結構的高度仍維持不變，可於消除翹曲的同時維持電子元件尺寸。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。
10:晶片置中式扇出面板級封裝結構 20:第一繞線層 21:聚醯亞胺壓合層 22:金屬層 221:金屬墊 30:第一聚醯亞胺層 31:柱狀開口 32:第一晶片開口 40:晶片 411:主動面 412:背面 42:金屬柱 421:突出端 422:平端 43:金屬凸塊 431:自由端 44:黏著層 50:第一封膠層 51:上表面 60:第二繞線層 61:金屬層 62:金屬層 63:外凸塊 70:錫球

Claims (11)

  1. 一種晶片置中式扇出面板級封裝結構，包含： 一第一繞線層； 一第一聚醯亞胺層，係形成於該第一繞線層上，並包含： 一第一晶片開口；以及 多個柱狀開口； 多個金屬柱，係形成於該第一繞線層上，並分別穿經該些柱狀開口； 一晶片，係穿經該第一晶片開口並設置於該第一繞線層上，其包含： 一主動面； 一背面，係相對於該主動面； 多個金屬凸塊，係形成於該主動面上；以及 一黏著層，係形成於該背面及該第一繞線層之間； 一第一封膠層，係形成於該第一聚醯亞胺層上，並包覆該些金屬柱以及該晶片；以及 一第二繞線層，係形成於該第一封膠層上，並分別電連接至該些金屬柱以及該晶片的該些金屬凸塊，其中該第二繞線層的層數係多於該第一繞線層的層數。
  2. 如請求項1所述之晶片置中式扇出面板級封裝結構，其中各該金屬柱係包含： 一突出端，係具有一第一直徑，其中該第一直徑係匹配該第一聚醯亞胺層中與該突出端相對應的該柱狀開口的一直徑；以及 一平端，係具有一第二直徑，其中該第二直徑係大於該第一直徑。
  3. 如請求項1所述之晶片置中式扇出面板級封裝結構，其中： 該晶片係小於其對應的該第一晶片開口；以及 該晶片與其對應的該第一晶片開口之間係形成有一間隙，且該間隙係由該第一封膠層填滿。
  4. 如請求項1所述之晶片置中式扇出面板級封裝結構，其中該第一繞線層係包含： 一金屬層，係包含多個金屬墊；以及 一聚醯亞胺壓合層，係形成於該金屬層及該第一聚醯亞胺層之間，其中各該金屬墊係外露於該聚醯亞胺壓合層。
  5. 如請求項4所述之晶片置中式扇出面板級封裝結構，係進一步包含多個錫球，其中該些錫球係分別設置於各該金屬墊上。
  6. 如請求項5所述之晶片置中式扇出面板級封裝結構，係進一步包含一第二聚醯亞胺層，其形成於該第一繞線層上，以部份包覆該些金屬墊，其中該第二聚醯亞胺層的厚度係小於各該錫球的高度。
  7. 如請求項4所述之晶片置中式扇出面板級封裝結構，係進一步包含： 一第三繞線層，係形成於該第一繞線層上，並電連接該第一繞線層的該些金屬墊，其中該第三繞線層係包含多個接墊； 一第二聚醯亞胺層，係形成於該第三繞線層上，並包含： 多個接墊開口，係對應該些接墊；以及 一第二晶片開口； 一堆疊晶片組，係穿經該第二晶片開口並設置於該第三繞線層上，並透過連接線通過該接墊開口，以電連接至相對應的第三繞線層的該些接墊；以及 一第二封膠層，係形成於該第二聚醯亞胺層上，以包覆該堆疊晶片組。
  8. 一種晶片置中式扇出面板級封裝方法，係包含以下步驟： (a)於一第一載板上形成一第一繞線層； (b)於該第一繞線層上形成一第一聚醯亞胺層； (c)於該第一聚醯亞胺層貫穿形成多個第一晶片開口及多個柱狀開口； (d)於該第一繞線層上形成多個金屬柱，該些金屬柱係分別穿經該些柱狀開口，並與該第一繞線層電連接； (e)將多個晶片分別穿經該些第一晶片開口設置於該第一繞線層上，其中各該晶片的一背面係由一黏著層設置於該第一繞線層上，且各該晶片的一主動面係形成多個金屬凸塊； (f)於該第一聚醯亞胺層上形成一第一封膠層以包覆該些金屬柱及該些晶片； (g)對該第一封膠層進行一減薄製程，直至該些金屬柱及各該晶片的該些金屬凸塊自該第一封膠層外露； (h)於該第一封膠層上形成一第二繞線層，並令該第二繞線層與該些金屬柱及該些晶片的該些金屬凸塊電連接；以及 (i)進行一切割步驟，以分離各該晶片置中式扇出面板級封裝結構。
  9. 如請求項8所述之晶片置中式扇出面板級封裝方法，其中於該步驟(i)前，移除該第一載板以令該第一繞線層外露，並令多個錫球設置於對應的多個金屬墊。
  10. 如請求項9所述之晶片置中式扇出面板級封裝方法，其中： 於設置該些錫球前，一第二聚醯亞胺層係進一步形成於該第一繞線層上；以及 該第一繞線層的該金屬墊係外露於該第二聚醯亞胺層，其中該第二聚醯亞胺層的厚度係小於該錫球的高度。
  11. 如請求項8所述之晶片置中式扇出面板級封裝方法，係於進行該步驟(i)之前進一步包含以下步驟： (j)將該第二繞線層與一第二載板接觸，並移除該第一載板以令該第一繞線層外露； (k)於該第一繞線層上形成一第三繞線層，其中該第三繞線層係包含多個接墊； (l)於該第三繞線層上形成一第二聚醯亞胺層，並於該第二聚醯亞胺層貫穿形成多個接墊開口，以令該些接墊外露，且對應該第一聚醯亞胺層的該些第一晶片開口貫穿形成多個第二晶片開口； (m)將多個堆疊晶片組穿經對應的該第二晶片開口並設置於該第三繞線層上，再將各該堆疊晶片組透過連接線通過該些接墊開口，以與相對應的該第三繞線層的該些接墊電連接；以及 (n)於該第二聚醯亞胺層上形成一第二封膠體，並包覆該些堆疊晶片組。
TW111107166A 2021-12-27 2022-02-25 晶片置中式扇出面板級封裝結構及其封裝方法 TWI814262B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/562,211 2021-12-27
US17/562,211 US20230207434A1 (en) 2021-12-27 2021-12-27 Chip-middle type fan-out panel-level package and packaging method thereof

Publications (2)

Publication Number Publication Date
TW202326949A TW202326949A (zh) 2023-07-01
TWI814262B true TWI814262B (zh) 2023-09-01

Family

ID=86897124

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111107166A TWI814262B (zh) 2021-12-27 2022-02-25 晶片置中式扇出面板級封裝結構及其封裝方法

Country Status (3)

Country Link
US (1) US20230207434A1 (zh)
CN (1) CN116364680A (zh)
TW (1) TWI814262B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111403368A (zh) * 2019-01-02 2020-07-10 台湾积体电路制造股份有限公司 半导体封装体
TW202042353A (zh) * 2019-05-08 2020-11-16 力成科技股份有限公司 半導體封裝及其製造方法
TW202121637A (zh) * 2019-11-20 2021-06-01 力成科技股份有限公司 扇出型封裝結構及其製法
TWI734175B (zh) * 2019-08-21 2021-07-21 矽品精密工業股份有限公司 電子封裝件及其製法與電子封裝模組
US20210296249A1 (en) * 2020-03-17 2021-09-23 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111403368A (zh) * 2019-01-02 2020-07-10 台湾积体电路制造股份有限公司 半导体封装体
TW202042353A (zh) * 2019-05-08 2020-11-16 力成科技股份有限公司 半導體封裝及其製造方法
TWI734175B (zh) * 2019-08-21 2021-07-21 矽品精密工業股份有限公司 電子封裝件及其製法與電子封裝模組
TW202121637A (zh) * 2019-11-20 2021-06-01 力成科技股份有限公司 扇出型封裝結構及其製法
US20210296249A1 (en) * 2020-03-17 2021-09-23 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices

Also Published As

Publication number Publication date
US20230207434A1 (en) 2023-06-29
CN116364680A (zh) 2023-06-30
TW202326949A (zh) 2023-07-01

Similar Documents

Publication Publication Date Title
US20200335447A1 (en) Method for fabricating electronic package
TWI496270B (zh) 半導體封裝件及其製法
US9520304B2 (en) Semiconductor package and fabrication method thereof
US20090218671A1 (en) Semiconductor device and method of fabricating the same
US10121736B2 (en) Method of fabricating packaging layer of fan-out chip package
TW201717343A (zh) 封裝上封裝構件及其製作方法
US20170148761A1 (en) Method of fabricating semiconductor package
JP2001257307A (ja) 半導体装置
JP6125209B2 (ja) 半導体装置及びその製造方法
TWI730917B (zh) 電子封裝件及其製法
TW201434131A (zh) 半導體元件及其形成方法
US11610850B2 (en) Electronic package and fabrication method thereof
US11232999B2 (en) Chip package structure and method for forming chip package
TW201742167A (zh) 電子封裝件及其製法
CN111725146A (zh) 电子封装件及其制法
TWI814262B (zh) 晶片置中式扇出面板級封裝結構及其封裝方法
TW202306093A (zh) 半導體封裝
KR20240022787A (ko) 반도체 패키지
KR101013558B1 (ko) 인터포저 및 이를 이용한 반도체 패키지
JP2014192171A (ja) 半導体装置及びその製造方法
TWI721383B (zh) 具有多個積體電路單元的封裝結構及其製作方法
TW202209507A (zh) 電子封裝件及其製法
KR20100096914A (ko) 반도체 패키지 및 이를 이용한 스택 패키지
TWI615926B (zh) 電子封裝件及其製法
KR100805092B1 (ko) 적층형 다중칩 패키지 및 그 제조 방법