TWI813944B - 主動元件基板及主動元件基板的製造方法 - Google Patents

主動元件基板及主動元件基板的製造方法 Download PDF

Info

Publication number
TWI813944B
TWI813944B TW110104720A TW110104720A TWI813944B TW I813944 B TWI813944 B TW I813944B TW 110104720 A TW110104720 A TW 110104720A TW 110104720 A TW110104720 A TW 110104720A TW I813944 B TWI813944 B TW I813944B
Authority
TW
Taiwan
Prior art keywords
hydrogen atom
atom distribution
distribution region
substrate
concentration
Prior art date
Application number
TW110104720A
Other languages
English (en)
Other versions
TW202232763A (zh
Inventor
黃震鑠
陳國光
薛芷苓
Original Assignee
友達光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 友達光電股份有限公司 filed Critical 友達光電股份有限公司
Priority to TW110104720A priority Critical patent/TWI813944B/zh
Priority to CN202111221758.4A priority patent/CN113964187B/zh
Priority to US17/572,662 priority patent/US20220254933A1/en
Publication of TW202232763A publication Critical patent/TW202232763A/zh
Application granted granted Critical
Publication of TWI813944B publication Critical patent/TWI813944B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02565Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Bipolar Transistors (AREA)
  • Liquid Crystal (AREA)
  • Recrystallisation Techniques (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種主動元件基板,包括基板、主動元件以及阻隔層。主動元件位於基板上。阻隔層位於主動元件上。阻隔層包括第一氫原子分佈區以及第二氫原子分佈區。第一氫原子分佈區包括氮化矽以及氫原子。第一氫原子分佈區位於第二氫原子分佈區與基板之間。第二氫原子分佈區包括氮化矽以及氫原子。第一氫原子分佈區中之氮原子的濃度小於第二氫原子分佈區中之氮原子的濃度。第一氫原子分佈區中之氫原子之最高濃度大於第二氫原子分佈區中之氫原子之最高濃度。

Description

主動元件基板及主動元件基板的製造方法
本發明是有關於一種主動元件基板,且特別是有關於一種具有阻隔層的主動元件基板及主動元件基板的製造方法。
在現有的電子裝置的製造過程中,半導體材料若接觸到水氣及/或氫氣,可能會導致半導體材料的性質出現變化,進而影響電子裝置的製造良率。舉例來說,薄膜電晶體的半導體層若接觸到氫氣,則半導體層的導電性質可能會被改變,使薄膜電晶體故障。因此,目前亟需一種能避免半導體層接觸到水氣及/或氫氣的方法。
本發明提供一種主動元件基板,能避免水氣以及氫對主動元件造成損傷。
本發明提供一種主動元件基板的製造方法,能避免水氣以及氫對半導體層造成損傷。
本發明的至少一實施例提供一種主動元件基板。主動元件基板包括基板、主動元件以及阻隔層。主動元件位於基板上。阻隔層位於主動元件上。阻隔層包括第一氫原子分佈區以及第二氫原子分佈區。第一氫原子分佈區位於主動元件上。第一氫原子分佈區包括氮化矽以及氫原子。第一氫原子分佈區位於第二氫原子分佈區與基板之間。第二氫原子分佈區包括氮化矽以及氫原子。第一氫原子分佈區中之氮原子的濃度小於第二氫原子分佈區中之氮原子的濃度。第一氫原子分佈區中之氫原子之最高濃度大於第二氫原子分佈區中之氫原子之最高濃度。第一氫原子分佈區之厚度小於或等於第二氫原子分佈區之厚度。
本發明的至少一實施例提供一種主動元件基板。主動元件基板包括基板、主動元件以及阻隔層。主動元件位於基板上,且包括半導體層、第一閘極、源極以及汲極。半導體層位於基板上。第一閘極重疊於半導體層。第一閘極與半導體層之間夾有閘極絕緣層。第一閘極包括鋁、鋁合金或含有鋁層的堆疊層。源極以及汲極電性連接至半導體層。阻隔層位於主動元件上。阻隔層包括氧氮化矽以及氫原子。第一閘極位於該阻隔層與該半導體層之間。
本發明的至少一實施例提供一種主動元件基板的製造方法。主動元件基板的製造方法包括:提供基板;於基板上形成半導體層;以薄膜沉積製程於半導體層上形成阻隔層。阻隔層包括第一氫原子分佈區以及第二氫原子分佈區。第一氫原子分佈區位於半導體層上。第一氫原子分佈區包括氮化矽以及氫原子。第一氫原子分佈區位於第二氫原子分佈區與基板之間。第二氫原子分佈區包括氮化矽以及氫原子。第一氫原子分佈區中之氮原子的濃度小於第二氫原子分佈區中之氮原子的濃度。第一氫原子分佈區中之氫原子之最高濃度大於第二氫原子分佈區中之氫原子之最高濃度。第一氫原子分佈區之厚度小於或等於該第二氫原子分佈區之厚度。
圖1A至圖1D是依照本發明的一實施例的一種主動元件基板的製造方法的剖面示意圖。
請參考圖1A,提供基板100。基板100的材質可為玻璃、石英、有機聚合物、或是不透光/反射材料(例如:導電材料、金屬、晶圓、陶瓷或其他可適用的材料)或是其他可適用的材料。若使用導電材料或金屬時,則在基板100上覆蓋一層絕緣層(未繪示),以避免短路問題。
於基板100上形成半導體層130。在本實施例中,半導體層130的材料包括金屬氧化物。舉例來說,半導體層130的材料包括氧化銦鎵鋅(Indium-Gallium-Zinc Oxide, IGZO)、氧化鋅(ZnO)、氧化錫(SnO)、氧化銦鋅(Indium-Zinc Oxide, IZO)、氧化鎵鋅(Gallium-Zinc Oxide, GZO)、氧化鋅錫(Zinc-Tin Oxide, ZTO)或氧化銦錫(Indium-Tin Oxide, ITO)或其他合適材料。在本實施例中,半導體層130的材料包括氧化銦鎵鋅,且厚度T1為5奈米至100奈米。
在本實施例中,在形成半導體層130之前,於基板100上形成第一導電層110以及第一絕緣層120。第一導電層110為單層或多層結構。
第一導電層110包括遮光結構112、電容電極114以及訊號線116。半導體層130重疊於遮光結構112。第一絕緣層120覆蓋第一導電層110。半導體層130形成於第一絕緣層120上。
形成閘極絕緣層140於半導體層130上。在一些實施例中,閘極絕緣層140包括氮化矽、氧化矽、氮氧化矽(Silicon oxynitride, SiONx)、氧氮化矽(silicon nitride oxide,SiNOx)、氮化鋁、氧化鋁、氧化鉿、金屬氧化物、金屬氮化物、光阻或其他適合材料,其中氮氧化矽(SiONx)中氧的濃度大於氮的濃度,氧氮化矽(SiNOx)中氮的濃度大於氧的濃度。在本實施例中,閘極絕緣層140為氮氧化矽,且厚度為10奈米至500奈米。
形成第二導電層150於閘極絕緣層140上。第二導電層150包括第一閘極152、訊號線154以及訊號線156。第一閘極152重疊於半導體層130。第一閘極152與半導體層130之間夾有閘極絕緣層140。訊號線154透過貫穿第一絕緣層120以及閘極絕緣層140的通孔而電性連接至電容電極114。訊號線156透過貫穿第一絕緣層120以及閘極絕緣層140的通孔而電性連接至訊號線116。第二導電層150為單層或多層結構。第二導電層150的材料包括鋁、鋁合金、鉬鋁合金、鈦鋁合金、鉬鈦鋁合金或含有鋁層的堆疊層。
請參考圖1B,對半導體層130執行摻雜製程P,以於半導體層130中形成摻雜區132、摻雜區136以及通道區134。通道區134位於摻雜區132以及摻雜區136之間。在本實施例中,摻雜製程P為氫電漿處理製程,但本發明不以此為限。在其他實施例中,摻雜製程P為離子佈植製程或其他合適的摻雜製程。在一些實施例中,以第二導電層150為罩幕,對半導體層130執行摻雜製程P,但本發明不以此為限。在其他實施例中,形成其他遮罩(例如光阻),並以其他遮罩為罩幕,對半導體層130執行摻雜製程P。
請參考圖1C,以薄膜沉積製程於半導體層130上形成阻隔層160。在本實施例中,以薄膜沉積製程於第一閘極152、訊號線154、訊號線156以及閘極絕緣層140上形成阻隔層160。薄膜沉積製程包括電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition)。
阻隔層160的材料包括氫原子以及氮化矽(SiNx)或氧氮化矽(SiNOx)。在本實施例中,阻隔層160的厚度(厚度T3加上厚度T4)為50奈米至600奈米。在本實施例中,阻隔層160中的氫原子濃度為1E21 atoms/cm 3至5E22 atoms/cm 3,例如1E22 atoms/cm 3至5E22 atoms/cm 3。在本實施例中,阻隔層160中的氮原子濃度為1E21 atoms/cm 3至5E23 atoms/cm 3,例如1E21 atoms/cm 3至1E22 atoms/cm 3
在一些實施例中,閘極絕緣層140中包含氧原子,因此,部分氧原子有可能會擴散至阻隔層160。在本實施例中,阻隔層160中的氧原子濃度為2E18 atoms/cm 3至5E20 atoms/cm 3,例如2E18 atoms/cm 3至5E19 atoms/cm 3
圖2A是依照本發明的一實施例的一種主動元件基板的氮原子濃度分佈的示意圖。圖2B是依照本發明的一實施例的一種主動元件基板的氫原子濃度分佈的示意圖。圖2C是依照本發明的一實施例的一種主動元件基板的氧原子濃度分佈的示意圖。需注意的是,圖2A至圖2C用於表示不同元素各自在圖1C之線A-A’處不同深度位置的相對濃度變化,並非用於表示不同元素各自的具體濃度數值。圖2A至圖2C之縱軸的單位例如為at%或atom/cm -3
請參考圖1C以及圖2A至圖2C,阻隔層160包括第一氫原子分佈區162以及第二氫原子分佈區164。第一氫原子分佈區162位於半導體層130上。在本實施例中,第一氫原子分佈區162接觸並覆蓋第一閘極152、訊號線154、訊號線156以及閘極絕緣層140。第一閘極152位於第一氫原子分佈區162與半導體層130之間。
第二氫原子分佈區164位於第一氫原子分佈區162上,且第一氫原子分佈區162位於第二氫原子分佈區164與基板100之間。第二氫原子分佈區164直接連接第一氫原子分佈區162。第一氫原子分佈區162包括氮化矽以及氫原子。第二氫原子分佈區164包括氮化矽以及氫原子。
在本實施例中,形成第一氫原子分佈區162以及第二氫原子分佈區164的方式包括電漿增強化學氣相沉積。舉例來說,以矽甲烷(Silane,SiH 4)、氨氣(Ammonia,NH 3)以及氮氣(N 2)為原料,形成氧化氮(SiNx)、氫自由基(Hx radical)以及氮氫自由基(NHx radical)以及氮氣。
在本實施例中,第二氫原子分佈區164較第一氫原子分佈區162致密,且沉積第一氫原子分佈區162時生成之氫自由基的解離率較沉積第二氫原子分佈區164時生成之氫自由基的解離率小。在本實施例中,第一氫原子分佈區162中之氮原子的濃度小於第二氫原子分佈區164中之氮原子的濃度。第一氫原子分佈區162中之氫原子之最高濃度大於第二氫原子分佈區164中之氫原子之最高濃度。
在本實施例中,沉積第一氫原子分佈區162時生成之氫自由基的速率較慢,因此能減輕沉積第一氫原子分佈區162的過程中氫擴散到半導體層130內的問題,避免半導體層130的導電性質受到影響。在本實施例中,雖然第一氫原子分佈區162中之氫原子之最高濃度大於第二氫原子分佈區164中之氫原子之最高濃度,但沉積第一氫原子分佈區162時生成之氫原子較沉積第二氫原子分佈區164時生成之氫原子不容易移動,因此能減少氫離子在沉積阻隔層160的過程中擴散至半導體層130。
在一些實施例中,由阻隔層160的氮濃度的平均值定義出第一氫原子分佈區162與第二氫原子分佈區164的界線。換句話說,第一氫原子分佈區162與第二氫原子分佈區164的界線上的氮濃度即等於阻隔層160的氮濃度的平均值。
在一些實施例中,第一氫原子分佈區162中之氫原子之濃度在朝向基板100的方向DR1之分布為先升後降。在一些實施例中,第一氫原子分佈區162中之氮元素之濃度在朝向基板100的方向DR1之分布為逐漸下降。
在一些實施例中,第一氫原子分佈區162中之氫原子濃度為1E22atoms/cm 3至5E22atoms/cm 3,第二氫原子分佈區164中之氫原子濃度為1E21atoms/cm 3至5E22atoms/cm 3。在一些實施例中,閘極絕緣層140中之氫原子濃度為5E20atoms/cm 3至5E21atoms/cm 3
在一些實施例中,第一氫原子分佈區162中之氮原子濃度為1E21atoms/cm 3至1E22atoms/cm 3,第二氫原子分佈區164中之氮原子濃度為1E21atoms/cm 3至5E23atoms/cm 3。在一些實施例中,閘極絕緣層140中之氮原子濃度為2E18atoms/cm 3至5E20atoms/cm 3
在本實施例中,第一氫原子分佈區162之厚度T3小於或等於第二氫原子分佈區164之厚度T4。在一些實施例中,厚度T3為10奈米至600奈米,且厚度T4為10奈米至600奈米。
在一些實施例中,第一氫原子分佈區162以及第二氫原子分佈區164例如是於同一道沉積製程中所形成,然而沉積第一氫原子分佈區162時的製程參數不同於沉積第二氫原子分佈區164時的製程參數。舉例來說,沉積第二氫原子分佈區164時的功率大於沉積第一氫原子分佈區162時的功率。在其他實施例中,沉積第一氫原子分佈區162時所用之原料的流量比例不同於第二氫原子分佈區164時所用之原料的流量比例。
在一些實施例中,第一氫原子分佈區162中之氧原子的濃度高於第二氫原子分佈區164中之氧原子的濃度。
在一些實施例中,第一氫原子分佈區162中之氧原子濃度為2E18atoms/cm 3至5E19atoms/cm 3,第二氫原子分佈區164中之氧原子濃度為2E18atoms/cm 3至5E20atoms/cm 3。在一些實施例中,閘極絕緣層140中之氧原子濃度為1E21atoms/cm 3至5E22atoms/cm 3
請參考圖1D,形成平坦層170於阻隔層160上。平坦層170接觸並覆蓋第二氫原子分佈區164。形成第二絕緣層180於平坦層170上。
形成源極192、汲極194以及訊號線196於第二絕緣層180上。源極192以及汲極194電性連接至半導體層130的摻雜區132、136。訊號線196電性連接至訊號線156。
形成保護層200於源極192、汲極194以及訊號線196上。形成絕緣層210於保護層200上。形成第一電極220於絕緣層210上,且第一電極220電性連接至汲極194。形成畫素定義層230於第一電極220上。形成有機發光半導體層240於畫素定義層230的開口中,且有機發光半導體層240接觸第一電極220。形成第二電極250於有機發光半導體層240上。
在本實施例中,主動元件基板10包括基板100、主動元件T以及阻隔層160。在本實施例中,主動元件T為頂部閘極型薄膜電晶體,但本發明不以此為限。在其他實施例中,主動元件T為底部閘極型薄膜電晶體,舉例來說,第一導電層110的遮光結構112可作為第一閘極。在其他實施例中,主動元件T為雙閘極型薄膜電晶體,舉例來說,第二導電層150包括第一閘極152,且第一導電層110的遮光結構112可作為第二閘極,其中第二閘極重疊於半導體層130,且第二閘極位於基板100與半導體層130之間。
在本實施例中,主動元件基板10適用於有機發光二極體顯示裝置(OLED display),但本發明不以此為限。在其他實施例中,主動元件基板10適用於微型發光二極體顯示裝置(micro-LED display)、液晶顯示裝置或其他電子裝置。
圖3A是依照本發明的一實施例的一種主動元件基板的氮原子濃度分佈的示意圖。圖3B是依照本發明的一實施例的一種主動元件基板的氫原子濃度分佈的示意圖。圖3C是依照本發明的一實施例的一種主動元件基板的氧原子濃度分佈的示意圖。需注意的是,圖3A至圖3C用於表示不同元素各自在主動元件基板的不同深度位置的相對濃度變化,並非用於表示不同元素各自的具體濃度數值。圖3A至圖3C之縱軸的單位例如為at%或atom/cm -3
圖3A至圖3C的實施例類似於圖2A至圖2C的實施例,差異在於:圖3A至圖3C的實施例的第一氫原子分佈區162的厚度小於第二氫原子分佈區164的厚度。
圖4是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是,圖4的實施例沿用圖1A至圖1D的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。
圖4的主動元件基板20與圖1D的主動元件基板10的差異在於:圖4的主動元件基板20的阻隔層160a包括氧氮化矽(SiNOx)以及氫原子。
請參考圖4,在本實施例中,形成阻隔層160a的方式包括電漿增強化學氣相沉積。舉例來說,以矽甲烷(Silane,SiH 4)、氨氣(Ammonia,NH 3)、氧化亞氮(Nitrous oxide,N 2O)以及氮氣(N 2)為原料,形成氧氮化矽、氫自由基(Hx radical)以及氮氫自由基(NHx radical)以及氮氣。在本實施例中,閘極絕緣層140包括氮氧化矽(SiONx)。
在本實施例中,阻隔層160a中的氫原子濃度為5E20 atoms/cm 3至5E21 atoms/cm 3。在本實施例中,阻隔層160a中的氮原子濃度為1E21 atoms/cm 3至5E22 atoms/cm 3。在本實施例中,阻隔層160a中的氧原子濃度為1E21 atoms/cm 3至5E22 atoms/cm 3
在本實施例中,第一閘極152重疊於半導體層130,且第一閘極152與半導體層130之間夾有閘極絕緣層140。第一閘極152位於阻隔層160a與半導體層130之間。第一閘極152包括鋁、鋁合金或含有鋁層的堆疊層。鋁金屬具有阻隔氫氣的能力,因此,在沉積阻隔層160a的製程中第一閘極152可以保護半導體層130的通道區134,減少氫自由基擴散至半導體層130的通道區134。在本實施例中,的阻隔層160a中的氧氮化矽適用於阻擋水氣。
圖5A是依照本發明的一實施例的一種主動元件基板的氮原子濃度分佈的示意圖。圖5B是依照本發明的一實施例的一種主動元件基板的氫原子濃度分佈的示意圖。圖5C是依照本發明的一實施例的一種主動元件基板的氧原子濃度分佈的示意圖。需注意的是,圖5A至圖5C用於表示不同元素各自在圖4之線A-A’處不同深度位置的相對濃度變化,並非用於表示不同元素各自的具體濃度數值。圖5A至圖5C之縱軸的單位例如為at%或atom/cm -3
在本實施例中,阻隔層160a中之氮原子的濃度大於閘極絕緣層140中之氮原子的濃度。在本實施例中,阻隔層160a中之氫原子的濃度大於閘極絕緣層140中之氫原子的濃度。在本實施例中,阻隔層160a中之氧原子的濃度小於閘極絕緣層140中之氧原子的濃度。
在本實施例中,阻隔層160a包含氧氮化矽且可作為阻水層,第一閘極152包含鋁且可作為阻氫層,基於此,可以避免水氣以及氫對主動元件T造成損傷。
圖6A是依照本發明的一實施例的一種主動元件基板的氮原子濃度分佈的示意圖。圖6B是依照本發明的一實施例的一種主動元件基板的氫原子濃度分佈的示意圖。圖6C是依照本發明的一實施例的一種主動元件基板的氧原子濃度分佈的示意圖。需注意的是,圖6A至圖6C用於表示不同元素各自在主動元件基板的不同深度位置的相對濃度變化,並非用於表示不同元素各自的具體濃度數值。圖6A至圖6C之縱軸的單位例如為at%或atom/cm -3
圖6A至圖6C的實施例類似於圖5A至圖5C的實施例,差異在於:圖6A至圖6C的實施例的阻隔層160a包括第一氫原子分佈區162a以及第二氫原子分佈區164a。
請參考圖6A至圖6C,在本實施例中,形成阻隔層160a的方式包括電漿增強化學氣相沉積。舉例來說,以矽甲烷、氨氣、氧化亞氮以及氮氣為原料,形成氧氮化矽(SiNOx)、氫自由基以及氮氫自由基以及氮氣。在本實施例中,閘極絕緣層140包括氮氧化矽(SiONx)。
阻隔層160a中之氮原子的濃度大於閘極絕緣層140中之氮原子的濃度。在本實施例中,阻隔層160a中之氫原子的濃度大於閘極絕緣層140中之氫原子的濃度。在本實施例中,阻隔層160a中之氧原子的濃度小於閘極絕緣層140中之氧原子的濃度。
阻隔層160a包括第一氫原子分佈區162a以及第二氫原子分佈區164a。第一氫原子分佈區162a位於半導體層130上。第一氫原子分佈區162a位於第二氫原子分佈區164a與基板100(繪於圖4)之間。第一氫原子分佈區162a中之氮原子的濃度小於第二氫原子分佈區164a中之氮原子的濃度。第一氫原子分佈區162a中之氫原子的濃度小於第二氫原子分佈區164a中之氫原子的濃度。
在一些實施例中,由阻隔層160a的氮濃度的平均值定義出第一氫原子分佈區162a與第二氫原子分佈區164a的界線。換句話說,第一氫原子分佈區162a與第二氫原子分佈區164a的界線上的氮濃度即等於阻隔層160a的氮濃度的平均值。
在一些實施例中,第一氫原子分佈區162a以及第二氫原子分佈區164a例如是於同一道沉積製程中所形成,然而沉積第一氫原子分佈區162a時的製程參數不同於沉積第二氫原子分佈區164a時的製程參數。舉例來說,沉積第二氫原子分佈區164a時的功率大於沉積第一氫原子分佈區162a時的功率。在其他實施例中,沉積第一氫原子分佈區162a時所用之原料的氨氣流量與氧化亞氮的流量的比值低於第二氫原子分佈區164a時所用之原料的氨氣的流量與氧化亞氮的流量的比值。
在本實施例中,阻隔層160a包含氧氮化矽且可作為阻水層,第一閘極152包含鋁且可作為阻氫層,基於此,可以避免水氣以及氫對主動元件造成損傷。
10、20:主動元件基板 100:基板 110:第一導電層 112:遮光結構 114:電容電極 116、154、156、196:訊號線 120:第一絕緣層 130:半導體層 132、136:摻雜區 134:通道區 140:閘極絕緣層 150:第二導電層 152:第一閘極 160、160a:阻隔層 162、162a:第一氫原子分佈區 164、164a:第二氫原子分佈區 170:平坦層 180:第二絕緣層 192:源極 194:汲極 200:保護層 210:絕緣層 220:第一電極 230:畫素定義層 240:機發光半導體層 250:第二電極 DR1:方向 P:摻雜製程 T:主動元件 T1、T2、T3、T4:厚度
圖1A至圖1D是依照本發明的一實施例的一種主動元件基板的製造方法的剖面示意圖。 圖2A是依照本發明的一實施例的一種主動元件基板的氮原子濃度分佈的示意圖。 圖2B是依照本發明的一實施例的一種主動元件基板的氫原子濃度分佈的示意圖。 圖2C是依照本發明的一實施例的一種主動元件基板的氧原子濃度分佈的示意圖。 圖3A是依照本發明的一實施例的一種主動元件基板的氮原子濃度分佈的示意圖。 圖3B是依照本發明的一實施例的一種主動元件基板的氫原子濃度分佈的示意圖。 圖3C是依照本發明的一實施例的一種主動元件基板的氧原子濃度分佈的示意圖。 圖4是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 圖5A是依照本發明的一實施例的一種主動元件基板的氮原子濃度分佈的示意圖。 圖5B是依照本發明的一實施例的一種主動元件基板的氫原子濃度分佈的示意圖。 圖5C是依照本發明的一實施例的一種主動元件基板的氧原子濃度分佈的示意圖。 圖6A是依照本發明的一實施例的一種主動元件基板的氮原子濃度分佈的示意圖。 圖6B是依照本發明的一實施例的一種主動元件基板的氫原子濃度分佈的示意圖。 圖6C是依照本發明的一實施例的一種主動元件基板的氧原子濃度分佈的示意圖。
10:主動元件基板
100:基板
110:第一導電層
112:遮光結構
114:電容電極
116、154、156、196:訊號線
120:第一絕緣層
130:半導體層
132、136:摻雜區
134:通道區
140:閘極絕緣層
150:第二導電層
152:第一閘極
160:阻隔層
162:第一氫原子分佈區
164:第二氫原子分佈區
170:平坦層
180:第二絕緣層
192:源極
194:汲極
200:保護層
210:絕緣層
220:第一電極
230:畫素定義層
240:機發光半導體層
250:第二電極
T:主動元件

Claims (15)

  1. 一種主動元件基板,包括:一基板;一主動元件,位於該基板上;以及一阻隔層,位於該主動元件上,其中該阻隔層包括:一第一氫原子分佈區,位於該主動元件上,其中該第一氫原子分佈區包括氮化矽以及氫原子;以及一第二氫原子分佈區,該第一氫原子分佈區位於該第二氫原子分佈區與該基板之間,其中該第二氫原子分佈區包括氮化矽以及氫原子,其中該第一氫原子分佈區中之氮原子的濃度小於該第二氫原子分佈區中之氮原子的濃度,其中該第一氫原子分佈區中之氫原子之最高濃度大於該第二氫原子分佈區中之氫原子之最高濃度,其中該第一氫原子分佈區之厚度小於或等於該第二氫原子分佈區之厚度。
  2. 如請求項1所述的主動元件基板,其中該第一氫原子分佈區中之氫原子之濃度在朝向該基板的方向之分布為先升後降。
  3. 如請求項1所述的主動元件基板,其中該第一氫原子分佈區中之氮元素之濃度在朝向該基板的方向之分布為逐漸下降。
  4. 如請求項1所述的主動元件基板,其中該主動元件包括: 一半導體層,位於該基板上;一第一閘極,重疊於該半導體層,且該第一閘極與該半導體層之間夾有一閘極絕緣層,其中該第一氫原子分佈區接觸並覆蓋該閘極絕緣層;以及一源極以及一汲極,電性連接至該半導體層。
  5. 如請求項4所述的主動元件基板,其中該第一閘極的材料包括鋁、鋁合金、鉬鋁合金、鈦鋁合金、鉬鈦鋁合金或含有鋁層的堆疊層,該半導體層的材料包括金屬氧化物。
  6. 如請求項4所述的主動元件基板,其中該第一氫原子分佈區接觸並覆蓋該第一閘極,且該第一閘極位於該第一氫原子分佈區與該半導體層之間。
  7. 如請求項5所述的主動元件基板,其中該主動元件更包括:一第二閘極,重疊於該半導體層,且該第二閘極位於該基板與該半導體層之間。
  8. 如請求項1所述的主動元件基板,更包括:一平坦層,位於該阻隔層上,其中該平坦層接觸並覆蓋該第二氫原子分佈區。
  9. 如請求項1所述的主動元件基板,其中該第二氫原子分佈區的厚度為10奈米至600奈米,且該第一氫原子分佈區的厚度為10奈米至600奈米。
  10. 如請求項1所述的主動元件基板,其中該第二氫原子分佈區較該第一氫原子分佈區致密。
  11. 如請求項1所述的主動元件基板,其中該第二氫原子分佈區直接連接該第一氫原子分佈區。
  12. 一種主動元件基板,包括:一基板;一主動元件,位於該基板上,且包括:一半導體層,位於該基板上;一第一閘極,重疊於該半導體層,且該第一閘極與該半導體層之間夾有一閘極絕緣層,且該第一閘極包括鋁、鋁合金或含有鋁層的堆疊層;以及一源極以及一汲極,電性連接至該半導體層;以及一阻隔層,位於該主動元件上,其中該阻隔層包括氧氮化矽以及氫原子,其中該阻隔層包括一第一氫原子分佈區以及一第二氫原子分佈區,其中該第一氫原子分佈區位於該半導體層上且位於該第二氫原子分佈區與該基板之間,其中該第一氫原子分佈區中之氮原子的濃度小於該第二氫原子分佈區中之氮原子的濃度,其中該第一氫原子分佈區中之氫原子的濃度小於該第二氫原子分佈區中之氫原子的濃度,其中該第一閘極位於該阻隔層與該半導體層之間。
  13. 一種主動元件基板的製造方法,包括:提供一基板; 於該基板上形成一半導體層;以薄膜沉積製程於該半導體層上形成一阻隔層,其中該阻隔層包括:一第一氫原子分佈區,位於該半導體層上,其中該第一氫原子分佈區包括氮化矽以及氫原子;以及一第二氫原子分佈區,該第一氫原子分佈區位於該第二氫原子分佈區與該基板之間,其中該第二氫原子分佈區包括氮化矽以及氫原子,其中該第一氫原子分佈區中之氮原子的濃度小於該第二氫原子分佈區中之氮原子的濃度,其中該第一氫原子分佈區中之氫原子之最高濃度大於該第二氫原子分佈區中之氫原子之最高濃度,其中該第一氫原子分佈區之厚度小於或等於該第二氫原子分佈區之厚度。
  14. 如請求項13所述的主動元件基板的製造方法,其中該薄膜沉積製程包括電漿增強化學氣相沉積,且沉積該第二氫原子分佈區時的功率大於沉積該第一氫原子分佈區時的功率。
  15. 如請求項13所述的主動元件基板的製造方法,更包括:形成一閘極絕緣層於該半導體層上;形成一第一閘極於該閘極絕緣層上;以薄膜沉積製程於該第一閘極以及該閘極絕緣層上形成該阻隔層;以及 形成一源極以及一汲極,該源極以及該汲極電性連接至該半導體層。
TW110104720A 2021-02-08 2021-02-08 主動元件基板及主動元件基板的製造方法 TWI813944B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW110104720A TWI813944B (zh) 2021-02-08 2021-02-08 主動元件基板及主動元件基板的製造方法
CN202111221758.4A CN113964187B (zh) 2021-02-08 2021-10-20 主动元件基板及主动元件基板的制造方法
US17/572,662 US20220254933A1 (en) 2021-02-08 2022-01-11 Active device substrate and fabrication method of active device substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW110104720A TWI813944B (zh) 2021-02-08 2021-02-08 主動元件基板及主動元件基板的製造方法

Publications (2)

Publication Number Publication Date
TW202232763A TW202232763A (zh) 2022-08-16
TWI813944B true TWI813944B (zh) 2023-09-01

Family

ID=79465043

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110104720A TWI813944B (zh) 2021-02-08 2021-02-08 主動元件基板及主動元件基板的製造方法

Country Status (3)

Country Link
US (1) US20220254933A1 (zh)
CN (1) CN113964187B (zh)
TW (1) TWI813944B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230131235A1 (en) * 2021-10-25 2023-04-27 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display device and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6245602B1 (en) * 1999-11-18 2001-06-12 Xerox Corporation Top gate self-aligned polysilicon TFT and a method for its production
US8866136B2 (en) * 2009-12-02 2014-10-21 Samsung Electronics Co., Ltd. Transistor, method of manufacturing the transistor and electronic device including the transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4873528B2 (ja) * 2005-09-02 2012-02-08 財団法人高知県産業振興センター 薄膜トランジスタの製造方法
US8963147B2 (en) * 2010-09-28 2015-02-24 Toppan Printing Co., Ltd. Thin film transistor, method of manufacturing the same, and image display device equipped with thin film transistor
US20140312341A1 (en) * 2013-04-22 2014-10-23 Shenzhen China Star Optoelectronics Technology Co., Ltd. Transistor, the Preparation Method Therefore, and Display Panel
TWI515912B (zh) * 2013-05-08 2016-01-01 友達光電股份有限公司 半導體元件
US11302717B2 (en) * 2016-04-08 2022-04-12 Semiconductor Energy Laboratory Co., Ltd. Transistor and method for manufacturing the same
TW201920038A (zh) * 2017-09-29 2019-06-01 美商康寧公司 包含具有硬度及強度之分級保護塗層之玻璃、玻璃陶瓷及陶瓷製品

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6245602B1 (en) * 1999-11-18 2001-06-12 Xerox Corporation Top gate self-aligned polysilicon TFT and a method for its production
US8866136B2 (en) * 2009-12-02 2014-10-21 Samsung Electronics Co., Ltd. Transistor, method of manufacturing the transistor and electronic device including the transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Japanese Journal of Applied Physics 50 (2011) 096502 *

Also Published As

Publication number Publication date
CN113964187A (zh) 2022-01-21
TW202232763A (zh) 2022-08-16
CN113964187B (zh) 2023-05-16
US20220254933A1 (en) 2022-08-11

Similar Documents

Publication Publication Date Title
US10283529B2 (en) Method of manufacturing thin-film transistor, thin-film transistor substrate, and flat panel display apparatus
US11296074B2 (en) Electrostatic protection circuit and manufacturing method thereof, array substrate and display apparatus
JP5099740B2 (ja) 薄膜トランジスタ
US10615266B2 (en) Thin-film transistor, manufacturing method thereof, and array substrate
JP5780902B2 (ja) 半導体薄膜、薄膜トランジスタ及びその製造方法
KR102105485B1 (ko) 박막 트랜지스터 기판 및 그 제조 방법
US20230095169A1 (en) Thin film transistor substrate, manufacturing method thereof, and display panel
US9246007B2 (en) Oxide thin film transistor and method for manufacturing the same, array substrate, and display apparatus
TWI405335B (zh) 半導體結構及其製造方法
KR102650692B1 (ko) 박막 트랜지스터, 이를 포함하는 박막 트랜지스터 표시판 및 그 제조 방법
KR20140020602A (ko) 박막 트랜지스터 기판 및 그 제조 방법
KR102091444B1 (ko) 표시 기판 및 표시 기판의 제조 방법
TWI497689B (zh) 半導體元件及其製造方法
CN111341849A (zh) 显示基板及其制备方法、显示面板
KR20150007000A (ko) 박막 트랜지스터 기판 및 박막 트랜지스터 기판의 제조 방법
WO2019033762A1 (zh) 晶体管、阵列基板及其制作方法、显示装置
KR20100118838A (ko) 박막 트랜지스터 표시판 및 이의 제조 방법
US9252284B2 (en) Display substrate and method of manufacturing a display substrate
TWI813944B (zh) 主動元件基板及主動元件基板的製造方法
TWI814636B (zh) 主動元件基板
KR102643111B1 (ko) 박막 트랜지스터, 이를 포함하는 박막 트랜지스터 표시판 및 그 제조 방법
KR20160089592A (ko) 산화물 박막트랜지스터의 제조방법
KR20170072438A (ko) 트랜지스터 표시판 및 그 제조 방법
US20230183858A1 (en) Semiconductor device and manufacturing method thereof
KR102105005B1 (ko) 박막 트랜지스터 기판 및 그 제조 방법