TWI805636B - 半導體裝置以及提供半導體裝置的方法 - Google Patents

半導體裝置以及提供半導體裝置的方法 Download PDF

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TWI805636B
TWI805636B TW107138395A TW107138395A TWI805636B TW I805636 B TWI805636 B TW I805636B TW 107138395 A TW107138395 A TW 107138395A TW 107138395 A TW107138395 A TW 107138395A TW I805636 B TWI805636 B TW I805636B
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fins
providing
semiconductor device
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TW201923909A (zh
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洪俊九
徐康一
博爾納 奧布拉多維奇
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南韓商三星電子股份有限公司
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Abstract

描述一種半導體裝置以及提供半導體裝置的方法。所述方法提供多個鰭。多個鰭中的每一個的第一部分由罩幕覆蓋。多個鰭中的每一個的第二部分通過罩幕暴露。方法還在在高於一百攝氏度且不超過六百攝氏度的退火溫度下在體積增大環境（例如氫中）執行退火。鰭中的每一個的第二部分在退火期間暴露使得鰭中的每一個的第二部分經歷體積膨脹。

Description

半導體裝置以及提供半導體裝置的方法
本申請案主張2017年11月16日提交的名稱為“選擇性增大垂直場效應電晶體的矽鰭面積的方法（METHOD TO SELECTIVELY INCREASE SILICON FIN AREA FOR A VERTICAL FIELD EFFECT TRANSISTOR）”的臨時專利申請案第62/587,333號的權益，所述專利申請案指配給本申請的受讓人且以引用的方式併入本文中。
本申請有關一種半導體裝置以及提供半導體裝置的方法。
CMOS裝置的趨勢是減小尺寸。然而，尺寸縮小通常降低裝置性能。為解決平面CMOS裝置中的問題，已研發出垂直裝置。垂直架構可增大裝置密度且提高性能。舉例來說，已研發出鰭場效應電晶體（fin field effect transistor，finFET）。相較於平面CMOS裝置，FinFET可具有更佳靜電或短溝道效果（short channel effect，SCE）控制。密度和有效發射器寬度（Weff ）效率與閘極長度（Lg ）無關，其允許更鬆弛Lg 用於垂直裝置。由此，FinFET裝置以更小尺度替代平面CMOS裝置。
仍需改進垂直裝置的性能。除改變Lg 以外的用於提高性能的機械裝置受限，這是由於這類裝置的特定佈局內的緊密密度。因此，垂直裝置架構的研究持續進行。
描述一種提供半導體裝置的方法。所述方法提供多個鰭。多個鰭中的每一個的第一部分由罩幕覆蓋。多個鰭中的每一個的第二部分通過罩幕暴露。方法還在體積增大環境（volume-increasing ambient）（例如氫）中執行退火。退火是在高於一百攝氏度且不超過六百攝氏度的退火溫度下進行的。鰭中的每一個的第二部分在退火期間暴露使得鰭中的每一個的第二部分經歷體積膨脹。
描述一種提供半導體裝置的方法。所述方法包括：提供多個鰭使得所述多個鰭中的每一個的第一部分由罩幕覆蓋且所述多個鰭中的每一個的第二部分通過所述罩幕暴露，所述多個鰭中的每一個由矽形成；以及在至少一種退火溫度下在氫環境中執行退火持續退火時間，所述至少一種退火溫度為至少兩百攝氏度且不超過五百攝氏度，所述退火時間為至少二十秒且不超過四百秒，所述多個鰭中的每一個的所述第二部分在所述退火期間暴露使得所述多個鰭中的每一個的所述第二部分經歷體積膨脹，所述第二部分為溝道區以及頂部源極/汲極區中的至少一個。
描述一種提供半導體裝置。所述半導體裝置包括：多個鰭，所述多個鰭中的每一個具有溝道區以及頂部源極/汲極區，所述多個鰭以及所述頂部源極/汲極區中的至少一個具有擴展面積；多個閘極，覆蓋所述多個鰭的一部分；多個氧化層，存在於所述多個鰭與多個閘極之間；以及多個源極/汲極區。
方法對鰭進行處理使得鰭鼓脹，其中鰭暴露於氫退火。換句話說，暴露部分經歷體積膨脹。如果溝道面積暴露且退火，那麼有效溝道寬度通過鼓脹/體積膨脹而增大。如果鰭的頂部暴露，那麼鼓脹/體積增大可為頂部源極/汲極處理提供更大的體積。這可減小頂部源極/汲極側處的寄生電阻。
示範性實施例有關形成finFET。呈現以下描述以使本領域的普通技術人員能夠製造並使用本發明，並且在專利申請案和其要求的情況中提供。對於本文所述的示範性實施例和通用原理以及特徵的各種修改將容易顯而易見。主要關於具體實施方案中提供的具體方法和系統來描述示範性實施例。然而，所述方法和系統也將有效地操作於其它實施方案中。
例如“示範性實施例”、“一個實施例”以及“另一實施例”的術語可以指相同或不同實施例以及多個實施例。將相對於具有某些元件的系統及/或裝置描述所述實施例。然而，系統及/或裝置可包含比所示更多或更少的組件，且可在不脫離本發明的範圍的情況下對元件的佈置和類型作出變化。還將在具有某些步驟的具體方法的上下文中描述示範性實施例。然而，方法和系統有效地操作用於具有不同及/或額外步驟的其它方法以及與示範性實施例相容的不同順序的步驟。因此，本發明並非意圖限於所示的實施例，而應符合與本文所述的原理和特徵相一致的最廣泛範圍。
除非本文另外指示或明顯與內容相矛盾，否則在描述本發明的內容中（尤其在以下申請專利範圍的內容中）使用術語“一（a/an）”和“所述”以及類似指示物應理解為涵蓋單數以及複數。除非另外指出，否則術語“包括”、“具有”、“包含”以及“含有”應理解為開放式術語（即，意味“包含（但不限於）”）。
除非另外定義，否則本文所使用的所有技術和科學術語均具有與本發明本領域的普通技術人員通常所理解相同的含義。應注意，除非另外說明，否則本文中提供的任何和所有實例或示範性術語的使用，僅期望更好地闡明本發明，而非限制本發明的範圍。另外，除非另外定義，否則不可過度解釋以通常使用詞典限定的所有術語。
描述一種提供半導體裝置的方法。所述方法提供多個鰭。多個鰭中的每一個的第一部分由罩幕覆蓋。多個鰭中的每一個的第二部分通過罩幕暴露。方法還在體積增大環境（例如氫）中執行退火。退火是在高於一百攝氏度且不超過六百攝氏度的退火溫度下執行的。鰭中的每一個的第二部分在退火期間暴露使得鰭中的每一個的第二部分經歷體積膨脹。
圖1是描繪用於在半導體裝置中為元件（即鰭場效應電晶體（finFET））提供具有選擇性擴展體積的鰭結構的方法100的示範性實施例的流程圖。為簡單起見，一些步驟可省略，以另一順序及/或組合執行。一些步驟還可包含子步驟。另外，方法100可在已執行形成半導體裝置的其它步驟之後開始。舉例來說，方法可在已提供用於鰭的半導體之後開始。圖2A到圖2B以及圖3A到圖3B分別地描繪使用方法100製造鰭結構期間的半導體裝置200和半導體裝置200A的示範性實施例。為簡單起見，並非全部元件繪示於圖2A到圖3B中且圖2A到圖3B未按比例繪製。另外，出於解釋性的目的，可放大具體層的厚度或形狀。在半導體裝置200和半導體裝置200A的背景下描述方法100。然而，並未阻止方法100與不同的半導體裝置一起使用。
通過步驟102製造且製備用於半導體裝置的鰭以供用於體積增強退火（volume-enhancing anneal）。步驟102中的鰭的形成包含將較薄硬罩幕提供於半導體層，例如Si上。硬罩幕覆蓋Si層的待形成鰭的部分且暴露Si層的待移除的部分。隨後可執行蝕刻以從Si層限定鰭。另外，步驟102確保鰭的所需部分暴露以用於體積增強退火。因此，還提供退火罩幕，所述罩幕暴露將具有增大體積的鰭的部分。退火罩幕覆蓋不需要經歷體積膨脹的鰭的部分。在一些實施例中，退火罩幕包含用於形成鰭的硬罩幕的部分。在這類實施例中，需要保護鰭的頂部免於體積增大退火（volume-increasing anneal）。在其它實施例中，硬罩幕經移除且硬罩幕不是退火罩幕的部分。在一些這類實施例中，鰭的頂部需要具有增大的體積。其它結構，例如間隔層或其它罩幕層，可形成將罩幕退火的全部或部分。
圖2A和圖3A分別地描繪步驟102後的半導體裝置200和半導體裝置200A。參看圖2A，鰭210已從半導體層201形成。如上文所論述，半導體層201可以是Si。需要半導體裝置200的溝道體積增大。因此，鰭的側壁需要向外彎曲，為鰭210中的每一個提供凸出截面。然而，每一鰭的頂面需要保持大體上不變。因此，罩幕220暴露鰭210的側壁。在一些實施例中，罩幕220用於從下方半導體層201限定鰭210。類似地，圖3A描繪已由半導體層201形成的鰭210A。然而，需要半導體裝置200A在頂部源極及/或汲極（源極/汲極）附近具有鰭體積增大。需要溝道寬度保持大體上不變。因此，罩幕220A覆蓋鰭210A的側壁的大部分，但暴露鰭210A的頂部。
當存在罩幕220和罩幕220A時，通過步驟104，使半導體裝置200和半導體裝置200A在體積增大環境中進行退火。用於Si鰭210和Si鰭210A的體積增大環境是氫。進行退火使得鰭210和鰭210A的所需部分經歷體積膨脹。舉例來說，除在氫中以外，退火可在高於一百攝氏度且不超過六百攝氏度的溫度下進行。在一些實施例中，退火溫度是至少兩百攝氏度且不超過五百攝氏度。退火可進行持續至少十秒且不超過五百秒的退火時間。在一些實施例中，退火時間是至少二十秒且不超過四百秒。因此，鰭210和鰭210A的暴露部分鼓脹。
圖2B和圖3B分別地描繪執行步驟104後的半導體裝置200和半導體裝置200A。參看圖2B，鰭210'的側邊暴露於退火。虛線指示側壁的原始位置。因此，鰭210'的側壁已向外凸出。因此，鰭210'在溝道區中具有凸出截面。由於鰭210'的體積增大，因此溝道寬度增大。參看圖3B，鰭210A'的頂部暴露於退火。鰭210A'的頂部的原始位置也由虛線繪示。因此，鰭210A'的頂部已經歷體積膨脹。因此，鰭210A'具有更大的頂部源極/汲極體積。儘管氫退火是已知的，但這類退火僅用來降低Si裝置的表面粗糙度。相比於步驟104中執行的退火，這類退火可不增大經歷退火的結構（例如鰭210/210A）的體積。換句話說，進行步驟104中執行的退火使得鰭210/210A的所需部分的尺寸擴展。
使用方法100，可調適鰭210和鰭210A的幾何形狀。通過使鰭210和鰭210A的部分選擇性地暴露於氫退火，可選擇性地增大鰭210和鰭210A的這些部分的體積。在所示出實施例中，鰭210'的溝道的寬度可增大。類似地，鰭210A'的頂部的尺寸可增大。因此，鰭210A'具有更大的頂部源極/汲極體積。在其它實施例中，鰭的其它及/或額外區域可暴露於退火。這些其它及/或額外區域可由此增大體積。因此，可在無需顯著改變半導體裝置200/200A的製造或微影的情況下調適鰭210/210A的幾何形狀。
圖4是描繪用於在半導體裝置中提供具有擴展溝道體積的finFET的方法120的示範性實施例的流程圖。為簡單起見，一些步驟可包含子步驟、可省略、可以另一循序執行及/或可組合。另外，方法120可在已執行形成半導體裝置的其它步驟之後開始。圖5A到圖7描繪使用方法120製造finFET期間的半導體裝置250的示範性實施例的部分。為簡單起見，並非全部元件繪示於圖5A到圖7中且圖5A到圖7未按比例繪製。舉例來說，未示出可在鰭之前形成的各種結構。另外，出於解釋性目的，可放大層的厚度。為了清晰起見，僅展示電晶體的區域中形成的結構。在半導體裝置250的背景下描述方法120。然而，並未阻止方法120與不同的半導體裝置一起使用。
通過步驟122由矽層提供鰭。舉例來說，可在下方Si層上製造介電硬罩幕。硬罩幕中的孔口對應於待移除的Si區域。接著蝕刻Si層，留下鰭。通過步驟124形成底部源極/汲極區。在一些實施例中，步驟124包含生成外延層，例如SiGe，以供用於源極/汲極。還通過步驟126提供底部間隔層。步驟126包含在鰭上形成具有所需高度的介電層。
圖5A和圖5B描繪已執行步驟126後的半導體裝置250的截面圖和透視圖。鰭260已由下方矽層251形成。硬罩幕252用於限定來自矽層251的鰭260。也已製造源極/汲極區262和底部間隔件264。
通過步驟128，半導體裝置250在氫環境中退火使得溝道區的體積增大。在一些實施例中，步驟128包含在至少兩百攝氏度且不超過五百攝氏度的退火溫度下將半導體裝置250退火至少二十秒且不超過四百秒。在一些實施例中，可在至少兩百五十攝氏度的退火溫度下進行退火。在一些實施例中，退火時間可為至少三十秒且不超過三百秒。在示出的實施例中，在步驟124和步驟126後執行步驟128。在其它實施例中，可在步驟126之前或在步驟124和步驟126之前執行步驟128。
圖6A和圖6B描繪執行步驟128之後的半導體裝置250的截面圖和透視圖。在圖6A中，通過虛線指示底部間隔件264上方的側壁的原始位置。由硬罩幕252、源極/汲極區262以及底部間隔件264覆蓋的鰭260'的部分的體積未顯著改變。由於氫退火，因此矽鰭260'的暴露部分的體積擴展，向外彎曲。這使得鰭260'的溝道區的體積增大。另外，如圖6B中可見，鰭260'的外部區域傾向於體積擴展超過中心區域。
接著繼續finFET的製造。通過步驟130提供氧化層以及導電閘極層。舉例來說，可在步驟130中提供介面氧化層和閘極氧化層。另外，可沉積金屬閘極。通過步驟132將氧化層和閘極層圖案化成所需形狀。通過步驟134提供用於鰭260'的頂部間隔層。也通過步驟136提供頂部源極及/或汲極區。在一些實施例中，步驟136包含形成外延源極/汲極層。可通過步驟138將絕緣體沉積於半導體裝置250上。通過步驟140形成到頂部源極/汲極以及底部源極/汲極的接觸件。可通過步驟142沉積額外介電質。可通過步驟144完成半導體裝置250的製造。
圖7描繪製造完成之後的半導體裝置250的一部分。因此，繪示三個鰭場效應電晶體280。每一鰭場效應電晶體280包含具有擴展溝道區的鰭260'、源極/汲極區262、底部間隔件264、介面氧化物266、閘極氧化物270、金屬閘極272、頂部間隔件274以及頂部源極/汲極276。
方法120以及半導體裝置250可共用方法100以及半導體裝置200的益處。使用方法120，已選擇性地增大鰭260'的一部分的體積。更具體地說，鰭場效應電晶體280中的鰭260'的溝道區已擴展。因此，可在無需顯著改變鰭260'之間的間距或無需製造鰭場效應電晶體280的方法120的情況下調適鰭場效應電晶體280的幾何形狀。
圖8是描繪用於在半導體裝置中提供具有擴展溝道體積的finFET的方法150的示範性實施例的流程圖。為簡單起見，一些步驟可省略、可包含子步驟、可以另一循序執行及/或可組合。另外，方法150可在已執行形成半導體裝置的其它步驟之後開始。圖9到圖12描繪使用方法150製造finFET期間的半導體裝置250A的示範性實施例的部分。為簡單起見，並非全部元件繪示於圖9到圖12中且圖9到圖12未按比例繪製。舉例來說，未示出可在鰭之前形成的各種結構。另外，出於解釋性目的，可放大層的厚度。為了清晰起見，僅展示電晶體的區域中形成的結構。在半導體裝置250A的背景下描述方法150。然而，並未阻止方法150與不同的半導體裝置一起使用。
通過步驟152由矽層提供鰭。舉例來說，可在下方Si層上製造介電硬罩幕。硬罩幕中的孔口對應於待移除的Si區域。接著蝕刻Si層，留下鰭。通過步驟154形成底部源極/汲極區。在一些實施例中，步驟154包含生成外延層，例如SiGe，以供用於源極/汲極區。步驟152和步驟154類似於方法120的步驟122和步驟124。
圖9描繪已執行步驟154之後的半導體裝置250A。因此，鰭260A已由下方矽層251形成。硬罩幕252用於從矽層251限定鰭260A。也已製造源極/汲極區262和底部間隔件264。
通過步驟156移除用於形成鰭260A的硬罩幕252。進行這一步驟使得可在退火期間暴露鰭260A的頂面，下文論述。通過步驟158沉積底部間隔層。
接著通過步驟160使底部間隔件264A凹陷來暴露鰭260A的頂部。圖10描繪執行步驟160之後的半導體裝置250A。因此，底部間隔件264A已沉積且其高度已減小以允許所需量的鰭260A突出高於底部間隔件264A的頂面。
通過步驟162，半導體裝置250A在氫環境中退火使得鰭260A的頂部的體積增大。在一些實施例中，步驟162包含在至少兩百攝氏度且不超過五百攝氏度的退火溫度下將半導體裝置250A進行退火至少二十秒且不超過四百秒。在一些實施例中，可在至少兩百五十攝氏度的退火溫度下進行退火。在一些實施例中，退火時間可為至少三十秒且不超過三百秒。
圖11描繪執行步驟162之後的半導體裝置250A的截面圖。通過虛線指示底部間隔件264A上方的鰭260A'的側壁和頂部的原始位置。由源極/汲極區262以及底部間隔件264A覆蓋的鰭260A'的部分的體積未顯著改變。由於氫退火，因此矽鰭260A'的暴露部分的體積擴展，向外彎曲。這一凸出形狀使得鰭260A'的頂部區的體積增大。
接著繼續finFET的製造。底部間隔件264A比最終裝置所需的更厚。因此，底部間隔件264A通過步驟164進一步凹陷。通過步驟166提供氧化層和導電閘極。舉例來說，可在步驟166中提供介面氧化層和閘極氧化層。另外，可沉積金屬閘極。以用於半導體裝置250的類似方式來將氧化層和閘極層圖案化成所需形狀。然而，為達到目標長度，也需要將氧化層和閘極層從鰭260A'的頂部移除。因此，這些層通過步驟168凹陷。通過步驟170提供用於鰭260A'的頂部間隔層。還通過步驟172提供頂部源極及/或汲極區。在一些實施例中，步驟172包含形成外延源極/汲極層。可通過步驟174將絕緣體沉積於半導體裝置250A上。通過步驟176形成到頂部源極/汲極和底部源極/汲極的接觸件。可通過步驟178沉積額外介電質。可通過步驟180完成半導體裝置250A的製造。
圖12描繪製造完成之後的半導體裝置250A的一部分。因此，繪示三個鰭場效應電晶體280A。每一鰭場效應電晶體280A包含具有擴展源極/汲極區的鰭260A'、源極/汲極區262、底部間隔件264A'、介面氧化物266A、閘極氧化物270A、金屬閘極272A、頂部間隔件274A以及頂部源極/汲極276A。在步驟164中底部間隔件264A'已減小厚度。另外，介面氧化物266A和閘極氧化物270A以及金屬閘極272A暴露鰭260A'的頂部。
方法150以及半導體裝置250A可共用方法100以及半導體裝置200的益處。使用方法150，已選擇性地增大鰭260A'的一部分的體積。更具體地說，已擴展鰭場效應電晶體280A中的鰭260A'的頂部源極/汲極區。這為步驟172的頂部源極汲極處理提供更大的體積。因此，可減小寄生電阻。因此，可提高鰭場效應電晶體280A的性能。
已描述用於選擇性地擴展半導體裝置中的鰭的體積的方法和系統。已根據所繪示的示範性實施例描述方法和系統，且本領域的普通技術人員將容易地認識到實施例可變化，且任何變化將在方法和系統的精神和範圍內。因此，在不脫離所附申請專利範圍的精神和範圍的情況下，本領域的普通技術人員可以作出許多修改。
100、120、150‧‧‧方法102、104、122、124、126、128、130、132、134、136、138、140、142、144、152、154、156、158、160、162、164、166、168、170、172、174、176、178、180‧‧‧步驟200、200A、250、250A‧‧‧半導體裝置201‧‧‧半導體層210、210'、210A、210A'、260、260'、260A、260A'‧‧‧鰭220、220A‧‧‧罩幕251‧‧‧矽層252‧‧‧硬罩幕262‧‧‧源極/汲極區264、264A、264A'‧‧‧底部間隔件266、266A‧‧‧介面氧化物270、270A、‧‧‧閘極氧化物272、272A‧‧‧金屬閘極274、274A‧‧‧頂部間隔件276、276A‧‧‧頂部源極/汲極280、280A‧‧‧鰭場效應電晶體
圖1是描繪用於選擇性地增大半導體裝置中的鰭結構的一部分的體積的方法的示範性實施例的流程圖。 圖2A到圖2B描繪製造期間的鰭結構的示範性實施例的部分。 圖3A到圖3B描繪製造期間的鰭結構的另一示範性實施例的部分。 圖4是描繪用於在半導體裝置中提供具有擴展溝道體積的finFET的方法的示範性實施例的流程圖。 圖5A到圖7描繪製造期間的包含finFET的半導體裝置的示範性實施例的部分。 圖8是描繪用於在半導體裝置中提供具有擴展頂部源極/汲極體積的finFET的方法的示範性實施例的流程圖。 圖9到圖12描繪製造期間的包含finFET的半導體裝置的示範性實施例的部分。
100‧‧‧方法
102、104‧‧‧步驟

Claims (11)

  1. 一種提供半導體裝置的方法，包括：提供多個鰭使得所述多個鰭中的每一個的第一部分由罩幕覆蓋且所述多個鰭中的每一個的第二部分通過所述罩幕暴露，其中所述多個鰭為矽鰭；以及在高於一百攝氏度且不超過六百攝氏度的至少一種退火溫度下在體積增大環境中執行退火，所述多個鰭中的每一個的所述第二部分在所述退火期間暴露使得所述多個鰭中的每一個的所述第二部分經歷體積膨脹。
  2. 如申請專利範圍第1項所述的提供半導體裝置的方法，其中所述體積增大環境是氫氣。
  3. 如申請專利範圍第2項所述的提供半導體裝置的方法，其中執行所述退火的步驟更包含：執行所述退火持續至少十秒且不超過五百秒的退火時間。
  4. 如申請專利範圍第3項所述的提供半導體裝置的方法，其中所述退火時間是至少二十秒且不超過四百秒。
  5. 如申請專利範圍第2項所述的提供半導體裝置的方法，其中所述至少一種退火溫度是至少兩百攝氏度且不超過五百攝氏度。
  6. 如申請專利範圍第2項所述的提供半導體裝置的方法，其中所述多個鰭中的每一個的所述第二部分包含溝道區使得所述溝道區在所述退火期間經歷膨脹。
  7. 如申請專利範圍第2項所述的提供半導體裝置的方法，其中所述多個鰭中的每一個的所述第二部分包含源極區域以及汲 極區域中的至少一個使得所述源極區域以及所述汲極區域中的至少一個在所述退火期間經歷膨脹。
  8. 如申請專利範圍第2項所述的提供半導體裝置的方法，其中提供所述多個鰭的步驟更包含：在半導體層上提供硬罩幕，所述硬罩幕暴露所述半導體層的一部分；移除所述半導體層的暴露部分以形成所述多個鰭，所述多個鰭中的每一個具有頂面，所述硬罩幕存在於所述頂面上；在所述半導體層的移除部分上提供底部源極/汲極外延層；以及在所述底部源極/汲極外延層上提供底部間隔件，所述底部間隔件以及所述硬罩幕形成所述罩幕。
  9. 如申請專利範圍第2項所述的提供半導體裝置的方法，其中提供所述多個鰭的步驟更包含：在半導體層上提供硬罩幕，所述硬罩幕暴露所述半導體層的一部分；移除所述半導體層的暴露部分以形成所述多個鰭，所述多個鰭中的每一個具有頂面，所述硬罩幕存在於所述頂面上；移除所述硬罩幕；在所述半導體層的移除部分上提供底部源極/汲極外延層；以及在所述底部源極/汲極外延層上提供凹陷的底部間隔件，所述凹陷的底部間隔件形成所述罩幕。
  10. 一種提供半導體裝置的方法，包括： 提供多個鰭使得所述多個鰭中的每一個的第一部分由罩幕覆蓋且所述多個鰭中的每一個的第二部分通過所述罩幕暴露，所述多個鰭中的每一個由矽組成；以及在至少一種退火溫度下在氫環境中執行退火持續退火時間，所述至少一種退火溫度為至少兩百攝氏度且不超過五百攝氏度，所述退火時間為至少二十秒且不超過四百秒，所述多個鰭中的每一個的所述第二部分在所述退火期間暴露使得所述多個鰭中的每一個的所述第二部分經歷體積膨脹，所述第二部分為溝道區以及頂部源極/汲極區中的至少一個。
  11. 一種半導體裝置，包括：多個鰭，所述多個鰭為矽鰭，所述多個鰭中的每一個具有溝道區以及頂部源極/汲極區，所述多個鰭以及所述頂部源極/汲極區中的至少一個具有擴展面積，其中所述擴展面積包括所述頂部源極/汲極區，使得所述頂部源極/汲極區在退火期間經歷膨脹；多個閘極，覆蓋所述多個鰭的一部分；多個氧化層，存在於所述多個鰭與多個閘極之間；以及多個源極/汲極區。
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