TWI801113B - 被處理體之處理方法及電漿處理裝置 - Google Patents
被處理體之處理方法及電漿處理裝置 Download PDFInfo
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- TWI801113B TWI801113B TW111103533A TW111103533A TWI801113B TW I801113 B TWI801113 B TW I801113B TW 111103533 A TW111103533 A TW 111103533A TW 111103533 A TW111103533 A TW 111103533A TW I801113 B TWI801113 B TW I801113B
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- Prior art keywords
- processing apparatus
- workpiece
- processing method
- plasma processing
- plasma
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- 238000003672 processing method Methods 0.000 title 1
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Analytical Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017162602A JP6817168B2 (ja) | 2017-08-25 | 2017-08-25 | 被処理体を処理する方法 |
JP2017-162602 | 2017-08-25 |
Publications (2)
Publication Number | Publication Date |
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TW202220030A TW202220030A (zh) | 2022-05-16 |
TWI801113B true TWI801113B (zh) | 2023-05-01 |
Family
ID=65437918
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107128531A TW201921432A (zh) | 2017-08-25 | 2018-08-16 | 被處理體之處理方法 |
TW111103533A TWI801113B (zh) | 2017-08-25 | 2018-08-16 | 被處理體之處理方法及電漿處理裝置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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TW107128531A TW201921432A (zh) | 2017-08-25 | 2018-08-16 | 被處理體之處理方法 |
Country Status (5)
Country | Link |
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US (3) | US10748766B2 (zh) |
JP (1) | JP6817168B2 (zh) |
KR (1) | KR102632154B1 (zh) |
CN (2) | CN115732351A (zh) |
TW (2) | TW201921432A (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7066565B2 (ja) * | 2018-07-27 | 2022-05-13 | 東京エレクトロン株式会社 | プラズマ処理方法およびプラズマ処理装置 |
US10950428B1 (en) * | 2019-08-30 | 2021-03-16 | Mattson Technology, Inc. | Method for processing a workpiece |
Citations (4)
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US20070232071A1 (en) * | 2006-03-31 | 2007-10-04 | Applied Materials, Inc. | Method to improve the step coverage and pattern loading for dielectric films |
US20160203995A1 (en) * | 2015-01-12 | 2016-07-14 | Lam Research Corporation | Integrating atomic scale processes: ald (atomic layer deposition) and ale (atomic layer etch) |
US20170033178A1 (en) * | 2015-07-30 | 2017-02-02 | GlobalFoundries, Inc. | Integrated circuits and methods for their fabrication |
TW201727706A (zh) * | 2015-11-13 | 2017-08-01 | 佳能股份有限公司 | 反調圖案形成之方法 |
Family Cites Families (24)
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JP3267199B2 (ja) * | 1996-07-11 | 2002-03-18 | 株式会社デンソー | 半導体装置の製造方法 |
US6620741B1 (en) * | 2002-06-10 | 2003-09-16 | Intel Corporation | Method for controlling etch bias of carbon doped oxide films |
KR100480610B1 (ko) | 2002-08-09 | 2005-03-31 | 삼성전자주식회사 | 실리콘 산화막을 이용한 미세 패턴 형성방법 |
US6770852B1 (en) * | 2003-02-27 | 2004-08-03 | Lam Research Corporation | Critical dimension variation compensation across a wafer by means of local wafer temperature control |
JP2005064324A (ja) * | 2003-08-18 | 2005-03-10 | Konica Minolta Holdings Inc | 微細形状の加工方法及び光学素子 |
JP4727171B2 (ja) * | 2003-09-29 | 2011-07-20 | 東京エレクトロン株式会社 | エッチング方法 |
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US20190067009A1 (en) | 2019-02-28 |
US20200343091A1 (en) | 2020-10-29 |
JP6817168B2 (ja) | 2021-01-20 |
CN109427607A (zh) | 2019-03-05 |
US11322354B2 (en) | 2022-05-03 |
US20220254635A1 (en) | 2022-08-11 |
US11735423B2 (en) | 2023-08-22 |
KR20190022394A (ko) | 2019-03-06 |
JP2019041021A (ja) | 2019-03-14 |
US10748766B2 (en) | 2020-08-18 |
TW202220030A (zh) | 2022-05-16 |
CN109427607B (zh) | 2022-12-23 |
CN115732351A (zh) | 2023-03-03 |
KR102632154B1 (ko) | 2024-01-31 |
TW201921432A (zh) | 2019-06-01 |
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