TWI800832B - 記憶體元件、具有其的系統及操作其的方法 - Google Patents
記憶體元件、具有其的系統及操作其的方法 Download PDFInfo
- Publication number
- TWI800832B TWI800832B TW110117642A TW110117642A TWI800832B TW I800832 B TWI800832 B TW I800832B TW 110117642 A TW110117642 A TW 110117642A TW 110117642 A TW110117642 A TW 110117642A TW I800832 B TWI800832 B TW I800832B
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- Taiwan
- Prior art keywords
- same
- operating
- memory device
- memory
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2281—Timing of a read operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Static Random-Access Memory (AREA)
- Memory System (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
WOPCT/CN2021/083507 | 2021-03-29 | ||
PCT/CN2021/083507 WO2022204850A1 (en) | 2021-03-29 | 2021-03-29 | Memory device and asynchronous multi-plane independent read operation thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202238392A TW202238392A (zh) | 2022-10-01 |
TWI800832B true TWI800832B (zh) | 2023-05-01 |
Family
ID=79016668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110117642A TWI800832B (zh) | 2021-03-29 | 2021-05-17 | 記憶體元件、具有其的系統及操作其的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US11763892B2 (zh) |
JP (1) | JP7392180B2 (zh) |
KR (1) | KR20230010764A (zh) |
CN (1) | CN113892139A (zh) |
TW (1) | TWI800832B (zh) |
WO (1) | WO2022204850A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117079690A (zh) * | 2021-03-29 | 2023-11-17 | 长江存储科技有限责任公司 | 存储器器件及其异步多面独立读取操作 |
CN113892139A (zh) | 2021-03-29 | 2022-01-04 | 长江存储科技有限责任公司 | 存储器器件及其异步多面独立读取操作 |
CN114641762A (zh) * | 2022-01-28 | 2022-06-17 | 长江存储科技有限责任公司 | 存储器、存储器的控制方法及存储器系统 |
TWI819648B (zh) * | 2022-06-10 | 2023-10-21 | 旺宏電子股份有限公司 | 積體電路結構以及記憶體元件的製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200739418A (en) * | 2005-11-28 | 2007-10-16 | Atmel Corp | Command decoder for microcontroller based flash memory digital controller system |
US20160005469A1 (en) * | 2008-02-04 | 2016-01-07 | Conversant Intellectual Property Management Inc. | Non-volatile memory device having configurable page size |
US20170309340A1 (en) * | 2016-04-26 | 2017-10-26 | Sandisk Technologies Llc | Independent Multi-Plane Read And Low Latency Hybrid Read |
CN112513988A (zh) * | 2020-11-06 | 2021-03-16 | 长江存储科技有限责任公司 | 伪异步多平面独立读取 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
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US5748547A (en) | 1996-05-24 | 1998-05-05 | Shau; Jeng-Jye | High performance semiconductor memory devices having multiple dimension bit lines |
US7149119B2 (en) * | 2004-09-30 | 2006-12-12 | Matrix Semiconductor, Inc. | System and method of controlling a three-dimensional memory |
WO2009145923A1 (en) | 2008-05-30 | 2009-12-03 | Aplus Flash Technology, Inc. | Nand string based flash memory device, array and circuit having parallel bit lines and source lines |
US7920431B2 (en) | 2008-06-02 | 2011-04-05 | Micron Technology, Inc. | Asynchronous/synchronous interface |
TWI553641B (zh) | 2013-12-09 | 2016-10-11 | 慧榮科技股份有限公司 | 資料儲存裝置及其模式偵測方法 |
US9910594B2 (en) | 2015-11-05 | 2018-03-06 | Micron Technology, Inc. | Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation |
JP6753746B2 (ja) | 2016-09-15 | 2020-09-09 | キオクシア株式会社 | 半導体記憶装置 |
KR102663804B1 (ko) * | 2016-11-30 | 2024-05-07 | 에스케이하이닉스 주식회사 | 반도체장치 |
US10331345B2 (en) | 2017-09-29 | 2019-06-25 | Intel Corporation | Method and apparatus for reducing silent data errors in non-volatile memory systems |
JP2020004465A (ja) | 2018-06-26 | 2020-01-09 | キオクシア株式会社 | 半導体記憶装置 |
JP2020016954A (ja) | 2018-07-23 | 2020-01-30 | キオクシア株式会社 | メモリシステム |
US11037626B2 (en) * | 2018-11-28 | 2021-06-15 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices including memory planes and memory systems including the same |
US10685722B1 (en) * | 2019-01-24 | 2020-06-16 | Western Digital Technologies, Inc. | Method and system for improving performance of a storage device using asynchronous independent plane read functionality |
US10877696B2 (en) | 2019-03-28 | 2020-12-29 | Intel Corporation | Independent NAND memory operations by plane |
US10957393B2 (en) * | 2019-06-27 | 2021-03-23 | Micron Technology, Inc. | Apparatus and methods for performing concurrent access operations on different groupings of memory cells |
CN113892139A (zh) | 2021-03-29 | 2022-01-04 | 长江存储科技有限责任公司 | 存储器器件及其异步多面独立读取操作 |
-
2021
- 2021-03-29 CN CN202180001096.1A patent/CN113892139A/zh active Pending
- 2021-03-29 KR KR1020227044597A patent/KR20230010764A/ko active Search and Examination
- 2021-03-29 WO PCT/CN2021/083507 patent/WO2022204850A1/en active Application Filing
- 2021-03-29 JP JP2022578906A patent/JP7392180B2/ja active Active
- 2021-05-17 TW TW110117642A patent/TWI800832B/zh active
- 2021-05-28 US US17/334,011 patent/US11763892B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200739418A (en) * | 2005-11-28 | 2007-10-16 | Atmel Corp | Command decoder for microcontroller based flash memory digital controller system |
US20160005469A1 (en) * | 2008-02-04 | 2016-01-07 | Conversant Intellectual Property Management Inc. | Non-volatile memory device having configurable page size |
US20170309340A1 (en) * | 2016-04-26 | 2017-10-26 | Sandisk Technologies Llc | Independent Multi-Plane Read And Low Latency Hybrid Read |
CN112513988A (zh) * | 2020-11-06 | 2021-03-16 | 长江存储科技有限责任公司 | 伪异步多平面独立读取 |
Also Published As
Publication number | Publication date |
---|---|
US11763892B2 (en) | 2023-09-19 |
JP2023531214A (ja) | 2023-07-21 |
JP7392180B2 (ja) | 2023-12-05 |
CN113892139A (zh) | 2022-01-04 |
TW202238392A (zh) | 2022-10-01 |
KR20230010764A (ko) | 2023-01-19 |
WO2022204850A1 (en) | 2022-10-06 |
US20220310173A1 (en) | 2022-09-29 |
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