TWI798670B - 堆疊式射頻電路拓撲 - Google Patents

堆疊式射頻電路拓撲 Download PDF

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TWI798670B
TWI798670B TW110111257A TW110111257A TWI798670B TW I798670 B TWI798670 B TW I798670B TW 110111257 A TW110111257 A TW 110111257A TW 110111257 A TW110111257 A TW 110111257A TW I798670 B TWI798670 B TW I798670B
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Taiwan
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die
integrated
package
substrate
pad
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TW110111257A
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TW202147551A (zh
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巴辛 諾里
馬文 馬貝
林廣模
母千里
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美商沃孚半導體有限公司
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Abstract

本發明揭示一種積體電路裝置封裝，其包含：一基板；一第一晶粒，其包括附接至該基板之主動電子組件；及封裝引線，其等經組態以在該第一晶粒與一外部裝置之間傳導電信號。至少一個整合式互連結構設置於該第一晶粒上而與該基板相對。該至少一個整合式互連結構自該第一晶粒延伸至附接至該基板之一鄰近晶粒及/或至該等封裝引線之至少一者，且提供其等之間之電連接。本發明亦論述相關裝置及功率放大器電路。

Description

堆疊式射頻電路拓撲
本發明係關於積體電路裝置，且更特定言之係關於積體電路裝置封裝之結構。
RF功率放大器用於諸如用於無線通信系統之基地台等之多種應用中。藉由RF功率放大器放大之信號通常包含具有具在百萬赫(MHz)至十億赫(GHz)範圍內之頻率之一經調變載波的信號。調變載波之基頻信號通常處於一相對較低頻率，且取決於應用，可高達300 MHz或更高。許多RF功率放大器設計利用半導體切換裝置作為放大裝置。此等切換裝置之實例包含功率電晶體裝置，諸如MOSFET (金屬氧化物半導體場效電晶體)、DMOS (雙擴散金屬氧化物半導體)電晶體、HEMT (高電子遷移率電晶體)、MESFET (金屬半導體場效電晶體)、LDMOS (橫向擴散金屬氧化物半導體)電晶體等。
RF放大器通常形成為半導體積體電路晶片。大多數RF放大器係以矽或使用諸如碳化矽(「SiC」)及III族氮化物材料之寬帶隙半導體材料(即，具有大於1.40 eV之一帶隙)來實施。如本文中所使用，術語「III族氮化物」指代在氮與元素週期表之III族中之元素(通常為鋁(Al)、鎵(Ga)及/或銦(In))之間形成之半導電化合物。該術語亦指代三元及四元化合物，諸如AlGaN及AlInGaN。此等化合物具有其中一莫耳之氮與總共一莫耳之III族元素結合之實驗式。
矽基RF放大器通常使用LDMOS電晶體來實施，且可以相對廉價的製造展現高度的線性。基於III族氮化物之RF放大器通常使用HEMT來實施，主要在需要高功率及/或高頻率操作之應用中，其中LDMOS電晶體放大器可具有固有效能限制。
RF電晶體放大器可包含一或多個放大級，其中各級通常實施為一電晶體放大器。為了增加輸出功率及電流處置能力，RF電晶體放大器通常實施為一「單位單元」組態，其中大量個別「單位單元」電晶體電氣並聯配置。一RF電晶體放大器可實施為一單一積體電路晶片或「晶粒」，或可包含複數個晶粒。當使用多個RF電晶體放大器晶粒時，其等可串聯及/或並聯連接。
RF放大器通常包含匹配電路，諸如經設計以改良主動電晶體晶粒(例如，包含MOSFET、HEMT、LDMOS等)與連接至其以用於基本操作頻率之RF信號之傳輸線之間的阻抗匹配之阻抗匹配電路，及經設計以至少部分終止可在裝置操作期間產生之諧波產物(諸如二階及三階諧波產物)之諧波終止電路。諧波產物之終止亦影響互調變失真產物之產生。
(若干) RF放大器電晶體晶粒以及阻抗匹配及諧波終止電路可圍封於一裝置封裝中。一晶粒或晶片可指代一小塊半導電材料或在其上製造電子電路元件之其他基板。積體電路封裝可指代將一或多個晶粒囊封於一支撐殼體或封裝中，該支撐殼體或封裝保護晶粒免受實體損壞及/或腐蝕，且支撐用於連接至外部電路之電接觸件。一積體電路裝置封裝中之輸入及輸出阻抗匹配電路通常包含提供經組態以將主動電晶體晶粒之阻抗匹配至一固定值之一阻抗匹配電路之至少一部分的LC網路。電引線可自封裝延伸以將RF放大器電連接至外部電路元件(諸如輸入及輸出RF傳輸線及偏壓電壓源)。
可藉由整合式被動裝置(IPD)實現許多功能區塊，諸如阻抗匹配電路、諧波濾波器、耦合器、平衡-不平衡轉換器(balun)及功率組合器/分配器。IPD包含被動電組件且一般使用標準晶圓製造技術(諸如薄膜及光微影處理)來製造。IPD可設計為可覆晶安裝或可線接合(wire bondable)組件。用於IPD之基板通常為薄膜基板(像矽、氧化鋁或玻璃)，此可容許易於與主動電晶體晶粒一起製造及封裝。
用於組裝RF功率裝置之一些習知方法可涉及將電晶體晶粒及一些匹配網路組件(例如，預匹配電容器，諸如MOS電容器)組裝於一CPC (銅、銅鉬、銅層壓結構)或銅凸緣上之一陶瓷或包覆模製封裝中。電晶體晶粒、電容器及輸入/輸出引線可用導線(諸如金及/或鋁線)互連。此一組裝程序可為緩慢的且循序的(例如，一次接合一個封裝)且組裝成本可較高(例如，歸因於金線及昂貴的線接合機之成本)。
根據本發明之一些實施例，一種積體電路裝置封裝包含：一基板；一第一晶粒，其包括附接至該基板之主動電子組件；及至少一個整合式互連結構，其在該第一晶粒上且與該基板相對。該至少一個整合式互連結構自該第一晶粒延伸至附接至該基板之一鄰近晶粒及/或朝向至少一個封裝引線，且提供其等之間之電連接。
在一些實施例中，該電連接可不具有一線接合。
在一些實施例中，該第一晶粒可包含在該第一晶粒之與該基板相對之一表面上之一第一接合墊，該第一接合墊電連接至該等主動電子組件之一或多者。該至少一個整合式互連結構可包含在該第一接合墊上之一接觸墊。
在一些實施例中，該至少一個整合式互連結構可為一重佈層上之一導電配線圖案。
在一些實施例中，該至少一個整合式互連結構可包含或提供用於由該第一晶粒之該等主動電子組件定義之一電路的一阻抗匹配網路之至少一部分。
在一些實施例中，該至少一個整合式互連結構可為包含一或多個被動電子組件之一被動裝置。
在一些實施例中，該整合式互連結構之該接觸墊可為在該被動裝置之面向該第一晶粒之該表面之一表面上的一第二接合墊，該第二接合墊電連接至該一或多個被動電子組件。該第二接合墊藉由該第二接合墊與該第一接合墊之間之一導電凸塊連接至該第一接合墊。
在一些實施例中，該第一晶粒之該等主動電子組件可定義一第一射頻(RF)放大器電路。該鄰近晶粒可為包含定義一第二RF放大器電路之主動電子組件的一第二主動晶粒。第一及第二功率放大器電路可藉由該被動裝置連接成一多級放大器配置。
在一些實施例中，該被動裝置可為包含至少一個電感器之一整合式被動裝置(IPD)。
在一些實施例中，該IPD可不具有主動電子組件。
在一些實施例中，該IPD可包含介於其之導電元件之間之一絕緣材料，以定義整合於其中之至少一個電容器。
在一些實施例中，該鄰近晶粒可為包含一或多個電容器及在該鄰近晶粒之與該基板相對之一表面上之至少一個電容器接合墊的一電容器晶粒。該至少一個整合式互連結構之該接觸墊可為一第一接觸墊，且該至少一個整合式互連結構可進一步包含在該至少一個電容器接合墊上之至少一個第二接觸墊。
在一些實施例中，該至少一個封裝引線可為一閘極引線且該第一接合墊可為一閘極墊。該鄰近晶粒可在該第一晶粒與該閘極引線之間，且該阻抗匹配網路可為用於該電路之一輸入阻抗匹配網路。
在一些實施例中，該至少一個封裝引線可為一汲極引線且該第一接合墊可為汲極墊。該鄰近晶粒可在該第一晶粒與該汲極引線之間，且該阻抗匹配網路可為用於該電路之一輸出阻抗匹配網路。
在一些實施例中，該等主動電子組件可為功率電晶體裝置。該第一晶粒可包含III族氮化物及/或碳化矽。
根據本發明之一些實施例，一種射頻(RF)功率放大器裝置封裝包含：一基板；一第一晶粒，其包含複數個電晶體單元，該第一晶粒在其之一底表面上之一源極墊及在其之與該基板相對之一頂表面處之一閘極或汲極墊處附接至該基板；封裝引線，其等經組態以在該第一晶粒之該閘極或汲極墊與一外部裝置之間傳導電信號；及一整合式互連結構，其在該第一晶粒上且與該基板相對。該整合式互連結構包含在該閘極或汲極墊上之一第一接觸墊，及在附接至該基板之一鄰近晶粒上及/或耦合至該等封裝引線之一者的至少一個第二接觸墊。
在一些實施例中，該整合式互連結構可提供自該第一晶粒之該閘極或汲極墊至該鄰近晶粒及/或至該等封裝引線之該者的電連接。該電連接可不具有一線接合。
在一些實施例中，該整合式互連結構可為一重佈層上之一導電配線圖案，或包含一或多個被動電子組件之一被動裝置。
在一些實施例中，該整合式互連結構可包含或提供用於由該第一晶粒之該等電晶體定義之一電路的一阻抗匹配網路之至少一部分。
在一些實施例中，該整合式互連結構之該第一接觸墊可為在該被動裝置之面向該第一晶粒之該頂表面之一表面上的一接合墊，該接合墊電連接至該一或多個被動電子組件。該接合墊可藉由該接合墊與該閘極或汲極墊之間之一導電凸塊連接至該閘極或汲極墊。
在一些實施例中，該鄰近晶粒可包含在其之與該基板相對之一表面上之至少一個接合墊。該整合式互連結構之該至少一個第二接觸墊可在該至少一個接合墊上。該鄰近晶粒可為包含一或多個電容器之一電容器晶粒，或可為包含定義一RF放大器電路之一級之複數個電晶體單元的一第二晶粒。
在回顧以下圖式及[實施方式]時，熟習此項技術者將明白根據一些實施例之其他裝置、設備及/或方法。除上述實施例之任何及所有組合之外，所有此等額外實施例亦意欲包含於本描述內，在本發明之範疇內且受隨附發明申請專利範圍保護。
優先權之主張
本申請案主張於2020年4月3日向美國專利商標局申請之美國臨時申請案第63/004,760號之優先權，該案之揭示內容以引用的方式併入本文中。
本發明之一些實施例可由在組裝及最佳化包含於一積體電路裝置封裝中之各種組件之參數時的困難而引起。例如，包含於一晶粒或IPD (在本文中大體上稱為一被動裝置或被動RF裝置)中之一些被動電子組件(例如，電感器或電容器)之效能可基於與一接地平面之近接性而受影響。特定言之，隨著電感器線圈之繞組與一接地連接凸緣(或其他接地結構)之間的一距離減小，電感器線圈之品質因數Q可減小。然而，因為晶粒通常為僅具有提供用於電連接(通常藉由接合線)至外部晶粒或裝置之導電接觸元件(在本文中亦稱為接觸墊、接合墊或墊)之一個表面的平面結構，所以增加被動組件與接地平面之間之距離可增加與包含於一主動電晶體晶粒(在本文中亦稱為一電晶體晶粒或主動晶粒)中之一或多個主動電子組件(例如，電晶體，諸如包含電晶體單元之功率電晶體裝置)的連接長度。增加的連接長度可降低或取消藉由被動組件尤其是以較高頻率提供之阻抗匹配網路之有效性。使用一分流電感器(「shunt-L」)拓撲之輸出預匹配網路可具挑戰性(例如，對於GaN晶粒產品)，此係因為長shunt-L接合線可引入比所需更多之電感，從而使阻抗匹配之品質以約50 fF/瓦特至70 fF/瓦特降級(例如，部分歸因於GaN中之較低汲極至源極電容(Cds ) /瓦特)，此同樣可導致較高損耗及降低的效能。輸入(例如，閘極)接合線與輸出(例如，汲極)接合線之間之耦合亦可導致增益損耗及不穩定性。
與可使用線接合環圈來實施輸入及輸出預匹配之一些習知RF功率裝置相反，本發明之實施例提供用於高功率應用之經封裝RF功率產品，其中組件之間(例如，電路層級組件之間，諸如一或多個主動電晶體晶粒之接合墊之間，及/或主動電晶體晶粒之接合墊與封裝之閘極及/或汲極引線之間)的連接係藉由一或多個結構實施，該一或多個結構包含在一層或基板上之導電組件，諸如不使用線接合之半導體晶片或晶粒(例如，一或多個被動裝置)，在本文中大體上稱為整合式互連結構。
一整合式互連結構或裝置(或「整合式互連件」)可大體上指代包含在一層或基板上之積體電路(諸如電阻器(包含傳輸線)、通孔、電感器及/或電容器)之一結構，例如，具有可代替接合線用於減少及/或避免相關寄生電感及製造問題之整合式跡線、通孔及/或電路的一介電基底結構。在本文中所描述之一些實施例中，整合式互連件可實施為被動裝置(包含具有諸如矽、氧化鋁或玻璃之薄膜基板之IPD)及/或導電配線結構(包含在一重佈層(RDL)層壓結構或其他基板上之導電線)。如上文所提及，IPD包含電感器及/或其他被動電組件，且可使用標準半導體處理技術(諸如薄膜及/或光微影處理)來製造。IPD可為可覆晶安裝或可線接合之組件，且可包含諸如矽、氧化鋁或玻璃之薄膜基板。一RDL結構指代具有導電層圖案及/或導電通孔之一基板或層壓板。RDL結構可使用半導體處理技術藉由以下來製造：在一基底材料上沈積導電及絕緣層及/或圖案，及藉由在結構內形成用於透過RDL結構傳輸信號之通孔及銅佈線圖案。
如本文中所描述，整合式互連件可用於提供至電晶體晶粒之輸入、輸出及/或級之間之連接以及提供可對(若干)電晶體晶粒之操作有用及/或必要之電路。例如，整合式互連件可提供經組態以減少主動電晶體晶粒之間，及/或與連接至封裝引線之一外部裝置之間之一阻抗失配的一阻抗。在特定實例中，可藉由整合式互連件(諸如IPD)來實施用於一主動電晶體晶粒之輸入及/輸出預匹配網路電路，從而導致極少或沒有線接合。在一些實施例中，包含面向一或多個電晶體晶粒之各自接觸件之各自接觸件的覆晶IPD可用於例如在多級放大器實施方案中使多個電晶體晶粒互連。即，在一些實施例中，整合式互連件可提供一互連功能及一阻抗匹配/諧波終止功能兩者，使得可減少或消除封裝中之線接合之使用。在一些實施例中，如本文中所描述之IPD可不具有主動組件。
在一些實施例中，將提供用於主動晶粒之阻抗匹配網路之IPD (在本文中亦稱為預匹配IPD)直接放置或堆疊於電晶體晶粒及/或電容器晶片之閘極及/或汲極墊之頂部上，因此減少或最小化互連相關損耗。被動組件與一附接表面(諸如一裝置封裝晶粒墊之接地連接凸緣或封裝之凸緣)之間之升高的高度或增加的距離(如藉由堆疊式配置提供，例如，在一100 µm厚主動電晶體晶粒之頂部上)可減少至接地之電容耦合，因此減少或最小化對被動組件之品質因數Q之負面影響(且在一些情況中增加該品質因數Q) (最小化損耗)，且導致更佳RF效能。再者，整合式互連件(例如，預匹配IPD)中之薄的低輪廓導電跡線可具有至輸出線或跡線之較低耦合。
額外被動組件(例如，針對特定應用)可包含於被動裝置中及/或在被動裝置正下方之封裝之附接表面上。例如，在一些實施例中，可將用於預匹配及/或諧波終止之電容器(例如，MOS電容器)放置於輸入預匹配IPD與附接表面之間。類似地，可針對改良視訊頻寬(VBM)將高密度輸出電容器放置於輸出預匹配IPD與附接表面之間，而提供用於容置高密度VBM電容器之一更大區域。在一些實施例中，被動裝置可包含整合於其中之電容器，諸如MIM (金屬-絕緣體-金屬)電容器。
因此，本發明之實施例可使用堆疊式晶片拓撲來極大地減少閘極及汲極接合線之間之耦合問題(其可導致增益損耗及不穩定性)。在一些實施例中，可消除或減少閘極及/或汲極接合線，且整合式互連件(例如，輸入及/或輸出IPD)中之低輪廓導電跡線可提供其等之間之很少耦合及/或至輸出線或跡線之較低耦合。再者，藉由在一高Q覆晶IPD中實施shunt-L及串聯連接電感，可在一較小區域中且以可管理損耗達成所需電感。
本發明之實施例可用於5G及基地台應用之RF功率產品中，以及用於雷達及/或單晶微波積體電路(monolithic microwave integrated circuit) (「MMIC」)類型應用中。例如，基於III族氮化物之RF放大器可實施為MMIC裝置，其中一或多個電晶體晶粒與其等相關聯阻抗匹配及諧波終止電路一起實施於一單一積體電路晶粒中。
圖1A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。如圖1A中所展示，本發明之一些實施例提供一RF功率裝置封裝100a，其包含組裝於一封裝基板101a上之一主動晶粒105及整合式互連件(被繪示為被動裝置110i、110o；統稱為110)。在圖1A之實例中，基板101a係一重佈層(RDL)層壓結構。RDL 101a可包含使用半導體處理技術製造之導電層。然而，將理解，基板101a不限於此；例如，基板101a可為一印刷電路板(例如，具有金屬跡線之一多層印刷電路板)、包含導電通孔及/或導電墊或用於主動晶粒105之任何其他適合安裝表面之一陶瓷基板。RDL 101a之底表面或底側包含在RDL 101a之一附接表面101s上之組件與諸如一外部電路板之一外部裝置(未展示)之間傳導電信號的封裝引線(特定言之，閘極102g、汲極102d及源極102s引線，統稱為封裝引線102)。附接表面101s可包含一或多個導電晶粒墊，在一些實施例中，該一或多個導電晶粒墊可為封裝100之組件提供一電接地。RDL 101a包含用於將信號自引線102傳輸至被動電子組件(諸如包含一或多個MOS電容器104或高密度電容器106之電容器晶片)及主動電晶體晶粒105之主動電子組件(諸如電晶體)的通孔及多層銅佈線。例如，主動晶粒105可包含例如定義一RF功率放大器之功率電晶體裝置。在一些實施例中，主動晶粒105可包含離散多級MMIC及/或多路徑(例如，多厄悌(Doherty))電晶體裝置。
本文中所描述之主動電晶體晶粒可以矽或使用諸如碳化矽(「SiC」)及III族氮化物材料之寬帶隙半導體材料來實施。在特定實施例中，主動晶粒可為基於III族氮化物(諸如氮化鎵(GaN))的，及/或基於碳化矽(SiC)的，包含在一半導體層結構之一上部中並聯連接之單位單元電晶體。術語「半導體層結構」可指代包含一或多個半導體層(諸如半導體基板及/或半導體磊晶層)之一結構。在所繪示實施例中，主動電晶體晶粒包含在一上表面上之一閘極墊及/或汲極墊，及在半導體層結構之鄰近附接表面之一下表面上的一源極墊。然而，將理解，此晶粒組態在本文中僅藉由實例繪示，且本文中所描述之實施例及/或拓撲可與除明確繪示之晶粒組態以外之晶粒組態一起使用。
由於RF放大器通常用於高功率及/或高頻率應用中，所以可在操作期間在(若干)電晶體晶粒內產生高熱量。若(若干)電晶體晶粒變得太熱，則RF放大器之效能(例如，輸出功率、效率、線性度、增益等)可劣化及/或(若干)電晶體晶粒可受損。因而，RF放大器通常安裝於可經最佳化或以其他方式組態用於熱移除之封裝中。在圖1A之實例中，源極引線102s包含或附接至提供導熱性(例如，一散熱器)之一導電結構103 (被繪示為一嵌入式導電塊或通孔)。特定言之，可用用於將熱量傳遞遠離電晶體晶粒105之電晶體之銅通孔之一高密度導電陣列103來填充(例如，大於約85%填充、完全填充或幾乎完全填充)在電晶體晶粒105下方之RDL 101a之一區段。例如，在一嵌入式封裝程序中，亦可用一嵌入式銅塊或硬幣來填充導電結構103。電晶體晶粒105及電容器晶片104、106運用晶粒附接材料107及技術(諸如共晶材料、預塗層(precoat) (例如，AuSn預塗層)、預成型件(pre-form)、燒結(例如，Ag燒結)等)附接至RDL 101a之附接表面101s。
仍參考圖1A，主動電晶體晶粒105 (特定言之，電晶體晶粒105之一頂側或表面上之接觸件或接合墊105p)與封裝引線102之間之一或多個連接係藉由各自整合式互連件(在此實例中，由IPD 110i及110o實施之被動裝置)實施，而其等之間沒有線接合。由被動裝置110提供之連接與主動晶粒105之底側或表面所附接至之附接表面101s或基板101a相對(而非在其內)。更特定言之，在電晶體晶粒105之與基板101相對之一表面上之接合墊105p連接至在IPD 110之面向電晶體晶粒105之一表面上之接合墊110p，且IPD之接合墊110p連接至封裝引線102。如上文所提及，(若干)被動裝置110可包含在一半導體或其他基板上之被動電子組件，諸如電阻器/傳輸線、電感器及/或電容器。
在圖1A中，被動裝置110之組件經組態以提供用於由主動晶粒105之電晶體定義之一電路(例如，一RF放大器電路)之輸入110i及輸出110o阻抗匹配網路，且被繪示為高Q IPD，但如本文中所描述之被動裝置不限於此。輸入阻抗匹配電路可將輸入至RF功率裝置封裝100a之RF信號之基本分量的阻抗與主動晶粒105之輸入處之阻抗匹配，輸出阻抗匹配電路可將自RF功率裝置封裝100a輸出之RF信號之基本分量的阻抗與連接至主動晶粒105之輸出之電路的阻抗匹配，且輸入及/或輸出諧波終止電路經組態以短路至可存在於主動晶粒105之輸入及/或輸出處之基本RF信號的接地諧波。
在圖1A之實例中，用於輸入及輸出預匹配網路之高Q IPD 110係包含在IPD 110之一表面上之各自接合墊110p之覆晶裝置。因此，IPD 110經「覆晶」於電晶體晶粒105及電容器晶片104、106之頂部上，使得IPD 110之表面上之接合墊110p分別與電晶體晶粒105及電容器晶片104、106之面向IPD 110之表面之表面上的接合墊105p及104p、106p對準。IPD 110可包含用於將接合墊110p連接至接合墊105p及104p、106p之導電凸塊111 (例如，導電環氧樹脂圖案或焊料凸塊，在一些實施例中，預附接至IPD 110)。可藉由研磨晶圓(對於晶粒或電容器晶片)及/或藉由使用不同厚度之預成型件107以對準元件104、105及106之高度，而將電容器晶片104、106及電晶體晶粒105之頂表面對準至相同高度。因而，封裝100a包含一堆疊式結構，其中元件104、105及106附接至基板101a與元件110之間之附接表面101s (其可提供至接地之電連接)。元件110提供元件104、105及106與同基板10a相對之引線102之間的電連接，而沒有在元件104、105及106與引線102之間延伸之各自接合線。
附接至RDL 101a之銅填隙片(copper shim) 112可用於將信號自IPD 110路由至RDL 101a以及至封裝100a之閘極及汲極引線102g及102d。在一些實施例中，包含通孔(例如，貫穿矽通孔(through silicon via) (TSV))之額外IPD可代替銅填隙片112用於將IPD 110連接至閘極及汲極引線102g及102d。
一封裝材料(被繪示為一塑膠包覆模製件(over mold) (OMP) 113)囊封晶粒105、110或以其他方式對其提供保護，同時提供對引線102之接取用於連接至在封裝100a外部之電路或裝置(在本文中大體上稱為外部裝置)。包覆模製件113實質上可包圍晶粒105、110，且可由一塑膠或塑膠聚合物化合物形成，藉此提供保護以免受外部環境影響。包覆模製型封裝之優點包含封裝之降低的總體高度或厚度，以及引線102之配置及/或引線102之間之間距的設計靈活性。在一些實施例中，如本文中所描述之包覆模製型封裝可具有約400微米(µm)至約700 µm之一高度或OMP厚度。在其他實施例中，晶粒105、110可包含於包含陶瓷材料之一敞開腔封裝(例如，一熱增強型封裝(TEPAC或T3PAC))中，該敞開腔封裝界定包圍晶粒105、110之一腔且可具有約1400微米(µm)至約1700 µm之一高度或厚度。
圖1B係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之另一實例之一橫截面視圖。如圖1B中所展示，一RF功率裝置封裝100b包含組裝於一基板101b上之主動及被動裝置105、110。封裝100b包含如圖1A中所展示之實施例中之組件及連接，但基板101b係提供附接表面101s、源極引線102s及用於將熱量傳遞遠離電晶體晶粒105之電晶體之導熱性(例如，一散熱器)的一導電結構103 (例如，銅塊)。再者，與圖1A相比，被動裝置110之接合墊110p藉由一整合式互連件(被繪示為導電配線結構114，例如，包含一RDL中之銅佈線層)而非銅填隙片112 (或具有TSV之IPD)連接至封裝引線102。替代地，在一些實施例中，被動裝置110之接合墊110p可直接連接至封裝引線102 (例如，藉由各自焊料凸塊111)，而在其等之間沒有導電配線結構114。與圖1A之基於層壓板之實施例相比，圖1B之實施例可被描述為基於引線框的。
圖1C係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之另一實例之一橫截面視圖。如圖1C中所展示，一RF功率裝置封裝100c類似於圖1A之實施例，但代替銅填隙片112 (或具有TSV之IPD)，封裝100c包含附接於第一RDL層101a之頂部上而與閘極引線102g相對及/或與汲極引線102d相對的第二RDL層101c。第二RDL層101c之高度或厚度經選擇或經組態以提供與輸入側處之電晶體晶粒105及MOS電容器晶片104之凸塊墊105p、104p對準或共面，且同樣與輸出側處之電晶體晶粒105及VBW電容器晶片106之凸塊墊105p、106p對準或共面的一接觸表面。因而，輸入110i及輸出110o覆晶IPD可放置於由第二RDL層101c提供之實質上共面之表面上，以將電晶體晶粒105之閘極及汲極墊105p與閘極引線102g及汲極引線102d (及/或與MOS電容器104及VBW電容器106)互連。額外第二RDL層101c及/或其他中間基板(雖然未繪示)亦可設置於附接表面101s與(若干)被動裝置110之間，以提供不同高度或厚度之組件之接觸墊之間的所要間隙或對準。
圖1D係圖1A、圖1B及圖1C中之實施例之一等效電路圖。輸入預匹配網路係藉由高Q IPD 110i及輸入電容器104實施，以提供基本頻率f0之一L-C匹配電路(例如，一低通L-C)，以及用於最佳終止諧波頻率(例如，2f0)之一shunt-L電感Ls匹配電路(例如，一高通Ls)。輸出預匹配網路係藉由輸出電容器106及高Q IPD 110o實施，以提供用於預匹配基本頻率f0之一shunt-L電感Ls匹配電路(例如，一高通Ls)。可選擇輸入110i及輸出110o IPD之各者中之串聯傳輸線110r以提供自電晶體晶粒105至閘極102g或汲極102d引線之適當阻抗變換。串聯傳輸線(例如，如藉由導電結構110r提供)可被視為板傳輸線匹配網路之一擴展，且電氣寬度可經選擇或經組態以達成用於阻抗匹配之所要特性阻抗。
圖2A及圖2B係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的積體電路裝置封裝之實例之橫截面視圖。如圖2A及圖2B中所展示，RF功率裝置封裝200a及200b各自包含組裝於一封裝基板201上之一主動晶粒105及一整合式互連件(被繪示為一IPD或其他被動裝置110i)。封裝200a及200b包含如圖1B中所展示之實施例中之組件及連接，其中基板201實施為提供用於將熱量傳遞遠離電晶體晶粒105之電晶體之附接表面201s、源極引線102s及導熱性(例如，一散熱器)的一導電結構103 (例如，銅塊)。在圖2A及圖2B之實施例中，被動裝置110僅在封裝200a、200b之輸入側處使用。例如，對於具有較小晶粒周邊(例如，小於約16 mm之總閘極寬度)及/或較低頻率操作(例如，小於約2.4 GHz)之實施方案，電晶體晶粒105之輸出阻抗可足夠高以與一RF電路板匹配至50歐姆，使得可不需要一封裝內輸出預匹配網路。由於在此等實施方案中可僅需要一輸入預匹配網路，故電晶體晶粒105之輸入藉由定義該預匹配網路之IPD 110i及MOS電容器104電連接至閘極引線102g。
更特定言之，電晶體晶粒105及MOS電容器晶片104之頂表面上之接合墊105p及104p藉由各自焊料凸塊111連接至在IPD 110i之一對向表面(facing surface)上之接合墊110p，而在其等之間沒有線接合。IPD 110i之接合墊110p藉由導電配線結構114 (例如，一RDL中之銅佈線層)連接至閘極引線102g。替代地，被動裝置110i之接合墊110p可直接連接至閘極引線102g，而在其等之間沒有導電配線結構114。電晶體晶粒105之輸出藉由導電配線結構(被繪示為圖2A中之一RDL 214中之銅佈線層或繪示為圖2B中之一線接合14)直接連接至汲極引線102d。
圖2C係表示圖2A及圖2B之實施例之一等效電路圖。類似於圖1A及圖1B之實施例中之輸入側，輸入預匹配網路係藉由高Q IPD 110i及輸入電容器104實施，以提供基本頻率f0之一L-C匹配電路(例如，一低通L-C)，以及用於最佳終止一或多個諧波頻率(例如，2f0)之一shunt-L電感Ls匹配電路(例如，一高通Ls)。可選擇輸入IPD 110i中之串聯傳輸線110r以提供自電晶體晶粒105至閘極引線102g之適當阻抗變換。傳輸線110r之電氣寬度亦可經組態以達成用於阻抗匹配之所要特性阻抗。
圖3A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。如圖3A中所展示，RF功率裝置封裝300包含組裝於一封裝基板301上之一主動晶粒105及一整合式互連件(被繪示為一IPD或其他被動裝置110o)。如在圖1B之實施例中，基板301係提供附接表面301s、源極引線102s及用於將熱量傳遞遠離電晶體晶粒105之電晶體之導熱性(例如，一散熱器)的一導電結構103 (例如，銅塊)。在圖3A之實施例中，提供至主動晶粒105及電容器晶片106之電連接之被動裝置110o僅設置於封裝300之輸出側處。更特定言之，電晶體晶粒105及高密度電容器晶片106之接合墊105p及106p藉由各自焊料凸塊111連接至IPD 110o之接合墊110p，而在其等之間沒有線接合。IPD 110o之接合墊110p藉由導電配線結構114 (例如，一RDL中之銅佈線層)連接至汲極引線102d。替代地，被動裝置110o之接合墊110p可直接連接至汲極引線102d，而在其等之間沒有導電配線結構114。
仍參考圖3A，閘極引線102g、電容器晶片104與電晶體晶粒105之輸入之間的連接係藉由呈導電配線結構314之形式之整合式互連件來實施，導電配線結構314被繪示為包含銅(或其他導電)佈線層及例如被繪示為一導電通孔或柱314v之一接觸墊的一RDL。更特定言之，在圖3A之實例中，用於輸入預匹配網路及諧波終止之電感直接實施於RDL 314之銅跡線及通孔中，且省略輸入IPD 110i。用於阻抗匹配之電感可在導電配線結構314中例如使用銅佈線或線圈追蹤(coil tracing)之窄條帶來達成，且可使用導電通孔314v連接至電晶體晶粒105及輸入電容器晶片104之接合墊105p及104p。例如，在一些實施例中，可使用現代嵌入式封裝組裝技術來沈積窄銅跡線(例如，寬度為約10微米)及通孔，以共同為RDL 314提供所需或所要電感。然而，與一IPD 110相比，RDL 314之跡線寬度及/或跡線及/或通孔之間距的容限可較不可控。
圖3B係表示圖3A之實施例之一等效電路圖。類似於圖1A及圖1B之實施例中之輸出側，輸出預匹配網路係藉由輸出電容器106及高Q IPD 110o實施以提供用於預匹配基本頻率f0之一shunt-L電感Ls匹配電路(例如，一高通Ls)。可選擇輸出IPD 110o中之串聯傳輸線110r以提供自電晶體晶粒105至汲極引線102d之適當阻抗變換。輸入預匹配網路係藉由導電配線結構314及輸入電容器104實施，以提供基本頻率f0之一L-C匹配電路(例如，一低通L-C)，以及用於最佳終止一或多個諧波頻率(例如，2f0)之一shunt-L電感Ls匹配電路(例如，一高通Ls)。同樣地，可選擇實施於導電配線結構314中之串聯傳輸線310r以提供自電晶體晶粒105至閘極引線102g之適當阻抗變換。
圖4係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。如圖4A中所展示，RF功率裝置封裝400包含組裝於一基板301上之一主動晶粒105及一整合式互連件(被繪示為一IPD或其他被動裝置110oc)。如在圖3A之實施例中，基板301係提供附接表面301s、源極引線102s及導熱性之一導電結構103 (例如，銅塊)。閘極引線102g、電容器晶片104與電晶體晶粒105之輸入之間的連接係藉由導電配線結構314實施，其中用於輸入預匹配網路及諧波終止之電感直接實施於配線結構314之導電跡線及通孔中。提供至主動晶粒105之電連接之被動裝置110oc僅設置於封裝400之輸出側處。
在圖4A中，輸出電容器晶片106 (例如，高密度電容器，其等可用於視訊頻寬)並未定位於輸出IPD 110oc下方；實情係，將輸出電容例如作為金屬-絕緣體-金屬(MIM)電容器C整合至覆晶輸出IPD 110oc中。在一些實施例中，可藉由在IPD 110oc之導電元件之一者與接合墊110p之一或多者之間提供一絕緣材料而形成MIM電容器C。至少一個導電通孔或柱410v用於將整合式電容器之一個端連接至(例如)如由導電結構103提供之封裝接地。在一些實施例中，(若干)導電通孔410v可藉由一RDL中之(若干)銅通孔實施。將電容整合至圖4A中所展示之被動裝置110oc中可用於本文中所描述之實施例之任何者中，且可產生一較高Q (較低損耗)輸出預匹配，此係因為覆晶IPD程序通常係用高電阻矽基板完成，該高電阻矽基板具有小於可放置於覆晶IPD下方之一MOS電容器之損耗。高密度視訊頻寬(VBW)電容器仍可自封裝400中之一不同位置連接至輸出預匹配IPD 110oc。
圖4B係表示圖4A之實施例之一等效電路圖。輸出預匹配網路係藉由一高Q IPD 110oc及一整合式輸出電容(例如，藉由MIM電容器C實施)實施以提供用於預匹配基本頻率f0之一shunt-L電感Ls匹配電路(例如，一高通Ls)。由IPD 110oc提供之整合式輸出電容C藉由導電通孔410v (其自身可提供某一電阻及電感)連接至封裝接地。可選擇輸出IPD 110oc中之串聯傳輸線110r以提供自電晶體晶粒105至汲極引線102d之適當阻抗變換。輸入預匹配網路係藉由導電配線結構314及輸入電容器104實施，以提供基本頻率f0之一L-C匹配電路(例如，一低通L-C)，以及一shunt-L電感Ls匹配電路(例如，一高通Ls)，且可同樣地選擇串聯傳輸線310r以提供自電晶體晶粒105至閘極引線102g之適當阻抗變換。
圖5A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。如圖5A中所展示，RF功率裝置封裝500包含組裝於一封裝基板501上之一主動晶粒105及一整合式互連件(被繪示為一IPD或其他被動裝置110oc)，封裝基板501被實施為提供附接表面501s、源極引線102s及導熱性之一導電結構103 (例如，銅塊)，如在本文中所描述之一些其他實施例中。同樣地，閘極引線102g、電容器晶片104與電晶體晶粒105之輸入之間的連接係藉由導電配線結構314實施，其中用於輸入預匹配網路及諧波終止之電感直接實施於配線結構314之導電跡線及通孔中。再者，類似於圖4A之實施例，提供至主動晶粒105之電連接之被動裝置僅設置於封裝500之輸出側處，且係藉由包含整合於其中之輸出電容之一覆晶IPD 110oc實施，其中至少一個導電通孔410v (例如，RDL中之銅通孔)將整合式電容器連接至封裝接地。
在圖5A之實施例中，在此實例中藉由將封裝汲極引線102d定位成鄰近於源極/熱引線102s且在源極/熱引線102s與用於輸出電容器之接地節點G中間，而縮短(與圖4A之實施例相比)自電晶體晶粒105之汲極墊105p至封裝汲極引線102d之串聯連接。因此，圖5A之實施例可為有利的，因為可將電晶體晶粒105之汲極墊105p與封裝汲極引線102d之間的電感減小至一非常低的值，此對於較高頻率操作(例如，高於3 GHz操作頻率)中之效能可為有幫助及/或關鍵的。
圖5B係表示圖5A之實施例之一等效電路圖，且關於由導電配線結構314及輸入電容器104提供之輸入預匹配網路，可類似於圖4B之等效電路。輸出預匹配網路係藉由覆晶IPD 110oc實施，覆晶IPD 110oc提供其中整合有輸出電容C且藉由導電通孔410v連接至接地引線G的一shunt-L電感Ls匹配電路(例如，一高通Ls)。
如圖5A及圖5B中所展示，由於汲極引線102d在導電結構103與輸出接地引線G之間離開封裝500，因此本文中所描述之實施例提供一封裝覆蓋區500f及PCB電路設計515i、515o以支援此拓撲。圖5C係繪示圖5A之實施例之封裝覆蓋區500f之一平面圖。如圖5C中所展示，至整合於輸出IPD 110oc中之輸出電容C之接地連接係藉由與源極/熱引線102s相對之多個(展示為三個)較小接地引線G實施，在接地引線G與源極/熱引線102s之間具有汲極引線102d。(若干)輸出接地引線G可與外部電路板515 (諸如，如圖5D中所展示之一RF電路板)中及至外部電路板515之對應接地通孔515v對準。
特定言之，圖5D係具有一透明封裝500之一俯視平面圖，其繪示圖5C之封裝覆蓋區500f之底側，且進一步繪示至外部電路板515之一輸入匹配電路板515i及一輸出匹配電路板515o之連接。在一些實施例中，輸入及輸出匹配電路板515i、515o可包含額外主動及/或被動電組件。接地引線G可足夠大(例如，就相對於覆蓋區500f之表面積而言)以進行製造，但足夠小以實質上不會使輸出匹配電路板515o之效能降級。
圖6A及圖6B係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的積體電路裝置封裝之實例之橫截面視圖。如圖6A及圖6B中所展示，RF功率裝置封裝600a及600b包含組裝於一基板101上之主動晶粒605i、605o及一整合式互連件(被繪示為一IPD或其他被動裝置610)。如在圖1B中，基板101實施為提供附接表面101s、源極引線102s及用於將熱量傳遞遠離電晶體晶粒605i、605o之電晶體之導熱性(例如，一散熱器)的一導電結構103 (例如，銅塊)，且由被動裝置610提供之連接與附接表面101s或基板101相對(而非在其內)。
在圖6A及圖6B之實施例中，主動晶粒605i、605o定義一多級封裝RF功率放大器裝置(藉由實例，展示為兩個級)。例如，主動晶粒605i可為用於實施驅動器級之一較小電晶體晶粒，且主動晶粒605o可為用於實施放大器之輸出或最後級之較大電晶體晶粒605o (例如，在周邊上比驅動器級電晶體晶粒605i大約7倍至10倍)。電晶體晶粒605i、605o附接至提供源極/熱引線102s之基板101/導電結構103之附接表面101s，其中級間電容器晶片604在附接表面101s上之晶粒605i、605o之間。一級間被動裝置610附接至兩個電晶體晶粒605i、605o且提供其等之間之電連接。
特定言之，如圖6A及圖6B中所展示，一IPD 610覆晶安裝於電晶體晶粒605i、605o及級間匹配電容器晶片604之頂部上，使得IPD 610之接合墊610p與電晶體晶粒605i、605o及電容器晶片604之接合墊605p及604p對準。特定言之，IPD 610之接合墊610p可接觸提供一驅動器汲極引線605d之驅動器級電晶體晶粒605i之一或多個接合墊605p，及提供一輸出閘極引線605g之輸出級電晶體晶粒605o之一或多個接合墊605p。IPD 610可包含用於將接合墊610p連接至接合墊605p及604p而在其等之間沒有線接合的導電凸塊111 (例如，在一些實施例中，預附接至IPD 610之導電環氧樹脂圖案或焊料凸塊)。可藉由研磨晶圓(對於晶粒或電容器晶片)及/或藉由使用不同厚度之預成型件107以對準元件604、605i、605o之高度以使用IPD 610進行連接，而將電容器晶片604及電晶體晶粒605i、605o之頂表面對準至相同高度。
在圖6A及圖6B之多級放大器中，IPD 610包含定義一級間匹配網路之被動組件，該級間匹配網路經組態以提供驅動器級電晶體晶粒605i之輸出與輸出級電晶體晶粒605o之輸入之間的阻抗匹配，即，將驅動器晶粒605i之負載與最後晶粒605o之輸入匹配。儘管參考兩個級605i及605o進行繪示，但將理解，多個輸入或輸出電晶體晶粒可存在於附接表面101s上，其中一個級之輸出藉由各自IPD 610連接至下一級之輸入。自封裝引線102g及102d至晶粒605i及605o之閘極及汲極接觸墊605p的連接可藉由各自導電配線結構(被繪示為圖6A中之RDL 614中之銅佈線層及導電通孔614v，及/或繪示為圖6B中之一線接合14)及/或藉由輸入/輸出阻抗匹配電路及/或諧波終止電路(例如，使用整合式互連件110i/110o)實施，如本文中所描述。
圖6C係表示圖6A及圖6B之實施例之一等效電路圖。如圖6C中所展示，級間匹配網路係藉由電容器604及被動裝置610實施以提供驅動器級電晶體晶粒605i之輸出處及最後級電晶體晶粒605o之輸入處的一shunt-L預匹配網路Ls，以及連接驅動器及最後級電晶體晶粒605i及605o之一串聯L-C-L網路。此拓撲可為一多級RF功率放大器產品提供一寬頻回應。將理解，圖6C中所展示之電晶體晶粒605i與605o之間之級間阻抗匹配網路僅作為實例，且根據本發明之實施例之提供兩個或更多個主動晶粒之間之電連接的級間被動裝置610可包含或實施其他網路拓撲。
圖7A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。如圖7A中所展示，一RF功率裝置封裝700包含組裝於一基板101上之主動晶粒605i、605o及一整合式互連件(被繪示為一IPD或其他被動裝置610c)。如在圖6A中，基板101實施為提供附接表面101s、源極引線102s及用於將熱量傳遞遠離電晶體晶粒605i、605o之電晶體之導熱性(例如，一散熱器)的一導電結構103 (例如，銅塊)，且主動晶粒605i、605o定義一多級封裝RF功率放大器裝置。一級間被動裝置610c附接(被繪示為覆晶安裝)至其之接合墊610p及兩個電晶體晶粒605i、605o之接合墊605p且提供其等之間之電連接。
在圖7A中，級間匹配電容器604未定位於級間IPD 610c下方，實情係，將電容整合至IPD 610c中例如作為MIM電容器。一或多個導電通孔610v將整合式電容器之端連接至(例如)如由導電結構103提供之封裝接地。在一些實施例中，(若干)導電通孔610v可藉由一RDL中之(若干)銅通孔實施。因而，IPD 610c包含整合於其中之匹配電容，以提供經組態以提供由電晶體晶粒605i及605o實施之兩個或更多個放大器級之間之阻抗匹配的一級間匹配網路。
圖7B係表示圖7A之實施例之一等效電路圖。如圖7B中所展示，類似於圖6C之實施例，級間匹配網路係藉由被動裝置610c實施，以提供具有在驅動器級電晶體晶粒605i之輸出及最後級電晶體晶粒605o之輸入之各者處之一MIM或其他整合式電容器C的一shunt-L預匹配網路Ls，以及連接驅動器及最後級電晶體晶粒605i及605o之一串聯L-C-L網路。
圖8A及圖9A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的積體電路裝置封裝之子組件之實例之橫截面視圖。如圖8A及圖9A中所展示，RF功率裝置封裝800及900各自包含組裝於一封裝基板201上之一主動晶粒105及一整合式互連件(被繪示為一IPD或其他被動裝置110i、110c)。封裝800及900包含如圖2A及圖2B中所展示之實施例中之組件及連接，其中基板201實施為提供附接表面201s、源極引線102s及導熱性以及(在一些實施例中)一接地連接的一導電結構103 (例如，銅塊)。被動裝置110i、110c僅設置於封裝800、900之輸入側處，以藉由焊料凸塊111提供主動晶粒105之一導電墊105p與封裝之一閘極引線102g之間的電連接而在其等之間沒有線接合。被動裝置110i、110c (展示為一覆晶IPD)實施用於由主動晶粒105實施之電晶體電路之一輸入預匹配網路，如在圖2A及圖2B之實施例中。
在圖8A中，用於輸入匹配網路之一電容器晶片104 (例如，MOS電容器)設置於附接表面201s上而鄰近電晶體晶粒105且在IPD 110i下方。電晶體晶粒105及電容器晶片104之接合墊105p及104p藉由各自焊料凸塊111連接至IPD 110i之接合墊110p，而在其等之間沒有線接合。
在圖9A中，將輸入電容器整合至覆晶輸入IPD 110c中例如作為金屬-絕緣體-金屬(MIM)電容器，且一或多個導電通孔110v (例如，一RDL中之(若干)銅通孔)用於將(若干)整合式電容器連接至(例如)如由導電結構103提供之封裝接地。特定言之，一整合式MIM電容器(cap)之一個端可藉由圍繞晶粒內建至層壓板中之銅通孔110v或柱連接至電接地銅塊103。電晶體晶粒105之輸入側處之預匹配或諧波終止所需的電感可部分或全部併入至銅通孔/柱中，以提供一高Q、低損耗電感。
在圖8A及圖9A中，IPD 110i、110c之接合墊110p直接連接至閘極引線102g，而在其等之間沒有導電配線結構。同樣地，電晶體晶粒105之輸出可直接連接至汲極引線102d。藉由用線接合或一RDL中之銅佈線將汲極及閘極引線102d及102g連接至封裝之引線，可將封裝800、900兩者用作一經封裝RF功率產品中之一子組件。汲極引線102d亦可在連接至封裝輸出引線之前連接至額外輸出預匹配網路(例如，藉由導電配線結構(諸如，如圖2A及圖2B中所展示之一RDL中之銅佈線或線接合)或藉由如圖1A及圖1B中所展示之IPD)。
圖8B及圖9B分別為表示圖8A及圖9A之實施例之等效電路圖。類似於圖2C之實施例，在IPD 110i、110c中實施電感器L、Ls之一配置以提供用於主動晶粒105之電晶體配置之一阻抗預匹配網路。特定言之，IPD 110i、110c及輸入電容器(藉由圖8B中之外部電容器晶片104 (例如，MOS電容器)；圖9B中之整合式電容器C (例如，MIM電容器)實施)提供基本頻率f0之一L-C匹配電路(例如，一低通L-C)，以及用於最佳終止一或多個諧波頻率(例如，2f0)之一shunt-L電感Ls匹配電路(例如，一高通Ls)。在圖9B中，將預匹配及諧波終止可能需要之電容整合至IPD 110c中。
圖10A及圖10B分別為繪示根據本發明之一些實施例之提供阻抗匹配及整合式互連件的高Q IPD 110、610之實例之平面圖及透視圖。在圖10A及圖10B之實例中，使用線圈電感器Ls來實施電晶體之適當預匹配所需之shunt-L電感的精確值。可最佳化線圈電感器Ls之形狀、寬度及總體設計以降低損耗。線圈電感器Ls之一個端在一凸塊或接觸墊110pl上終止，凸塊或接觸墊110pl可用導電凸塊(例如，111)預附接以用於附接至用於預匹配之電容器(例如，104)或用於改良視訊頻寬之高密度電容器(例如，106)。用於實施串聯電感器之串聯連接條帶L之寬度可經組態以提供自電晶體晶粒至汲極引線之所要阻抗變換。串聯連接條帶L可在凸塊或接觸墊110p之間延伸，且可被視為板傳輸線匹配網路之一擴展，且各串聯連接條帶L之寬度可經組態以提供所要特性阻抗。更一般而言，本文中所描述之被動裝置之任何者可包含串聯連接條帶L或可使用串聯連接條帶L實施，該等串聯連接條帶L耦合於接觸墊110p之間以提供一或多個主動晶粒105之接觸墊105p之間，及/或一主動晶粒105之接觸墊105p與一封裝引線102之間的電連接(除其等之間之阻抗變換之外)。同樣地，本文中所描述之被動裝置之任何者可包含線圈電感器Ls或可使用線圈電感器Ls實施，該等線圈電感器Ls經組態用於連接至電容器(例如，藉由接觸墊110pl連接至整合於其中之電容器或外部電容器)。
圖11及圖12係繪示根據本發明之進一步實施例之包含堆疊式拓撲結構的熱增強型積體電路裝置封裝之實例之橫截面視圖。為便於繪示，放大圖11及圖12中之特徵尺寸。如圖11及圖12中所展示，RF功率裝置封裝1100、1200包含類似於圖1A、圖1B及圖1C之封裝100a、100b及100c之組件104、105、106、110及連接，但安裝於一導電基底或凸緣1101、1201上且藉由熱增強型封裝之一蓋部件1113、1213而非一塑膠包覆模製件113保護。特定言之，圖11繪示根據本發明之實施例之熱增強型封裝之一第一實施方案(稱為一TEPAC封裝1100)且圖12繪示一第二實施方案(稱為一T3PAC封裝1200)。
圖11之TEPAC封裝1100可為包含一基底1101及一上外殼之一基於陶瓷之封裝，該上外殼可包含一蓋部件1113及側壁部件1104。蓋部件1113及/或側壁1104可包含陶瓷材料(例如，氧化鋁)且可界定包圍導電基底或凸緣1101上之組件104、105、106、110的一敞開腔。導電基底或凸緣1101提供用於組件104、105、106、110之一附接表面1101s，以及用於將藉由該等組件產生之熱量消散或以其他方式傳遞至封裝1100外部之導熱性(例如，一散熱器)兩者。
圖12之T3PAC封裝1200亦可為包含一基底1201以及具有一蓋部件1213及側壁部件1204之一上外殼的一基於陶瓷之封裝。同樣地，蓋部件1213及側壁1204界定包圍導電基底或凸緣1201上之組件104、105、106、110的一敞開腔，導電基底或凸緣1201同樣地提供一附接表面1201s及用於將熱量消散或以其他方式傳遞至封裝1200外部之導熱性(例如，一散熱器)兩者。在封裝1200中，蓋部件1213可為一陶瓷材料(例如，氧化鋁)，而側壁部件1204被繪示為印刷電路板(PCB)。
在圖11及圖12中，凸緣1101、1201可為一導電材料，例如，銅層/層壓板或一合金或其等之金屬基複合材料。在一些實施例中，凸緣1101可包含銅鉬(CuMo)層、CPC (Cu/MoCu/Cu)或其他銅合金，諸如銅鎢CuW，及/或其他層壓/多層結構。在圖11之實例中，凸緣1101被繪示為側壁1104及/或蓋部件1113所附接至之一基於CPC之結構。在圖12之實例中，凸緣1201被繪示為側壁1204及/或蓋部件1213例如藉由一導電膠1208所附接至之一基於銅鉬(RCM60)之結構。
在圖11及圖12中，主動晶粒105、被動裝置(例如，電容器晶片104及106)及整合式互連件(統稱為110)藉由各自導電晶粒附接材料層107附接至凸緣1101、1201之附接表面1101s、1201s。凸緣1101、1201亦提供封裝1100、1200之源極引線102s。閘極引線102g及汲極引線102d係藉由各自導電配線結構1114、1214提供，導電配線結構1114、1214附接至凸緣1101、1201且藉由各自側壁部件1104、1204支撐。
側壁部件1104、1204之厚度可導致組件104、105、106、110與封裝引線102g、102d之間相對於附接表面1101s、1201s之一高度差。例如，主動晶粒105及其上之整合式互連件110i、110o之組合高度相對於附接表面1101s可為約100 µm，而閘極及汲極引線102g及102d可與附接表面1101s分離達約635 µm之一距離。因此，在圖11及圖12之實例中，各自線接合14用於將封裝引線102g、102d連接至附接表面1101s、1201s上之被動RF組件104、106之接觸墊104p、106p。因而，輸入於引線102g上之一RF信號可傳遞通過線接合14而至輸入匹配電路110i、104且至RF電晶體放大器晶粒105之一閘極終端105p，且經放大之輸出RF信號可自RF電晶體放大器晶粒105之汲極終端105p傳遞至輸出匹配電路110o、106，且自該處至接合線14以透過引線102d輸出。然而，將瞭解，在其他實施例中，可省略線接合14，且可使用不同電連接。
根據本發明之實施例之包含堆疊式拓撲結構之積體電路裝置封裝可提供的進一步優點在於，與一些習知設計相比，堆疊式互連結構可容許更薄或高度減小之封裝。在包覆模製封裝實施例中(例如，如圖1至圖9中所展示)，在封裝之底部處之封裝引線的佈線亦可容許封裝靈活性。例如，可藉由基於經修改封裝覆蓋區修改電路板/PCB上之跡線的佈局來容納封裝引線之高度及/或間距之變化。熱增強型封裝實施例(例如，如圖11至圖12中所展示)可提供類似優點，但可需要封裝尺寸(例如，凸緣高度及/或封裝引線間距)相對於標準化尺寸之變化。
因此，在本發明之實施例中，藉由在組件之間實體地延伸之一或多個整合式互連結構(例如，導電配線結構及/或被動裝置，諸如IPD)而非藉由線接合來實施組件之間(例如，電路層級組件之間，諸如一或多個主動電晶體晶粒之接觸墊之間，及/或主動電晶體晶粒之接觸墊與封裝之閘極及/或汲極引線之間)的電連接。即，整合式互連件可提供一互連及一阻抗匹配/諧波終止功能兩者，使得可減少或消除封裝中線接合之使用。
如本文中所描述，本發明之一些實施例使用「翻轉於」電晶體及電容器之頂部上的高Q IPD。封裝之IPD在接地平面(例如，如藉由亦可界定主動晶粒之附接表面之導電結構提供)上方之額外高度導致較高Q及較低損耗預匹配。翻轉IPD下方之絕大部分空間可用於電容器，諸如通常在輸出上使用之高密度電容器。可在可用空間中使用較大值電容，因此改良裝置之視訊頻寬。為將RF信號自IPD連接回至RDL及閘極/汲極引線，可使用具有TSV之銅填隙片或IPD。可藉由將晶圓(晶粒或電容器)研磨至類似高度，或藉由使用不同厚度之預成型件以對準高度，而將MOS電容器及電晶體晶粒之頂部對準至相同高度。IPD可經組態用於預匹配基本頻率以及最佳終止一或多個諧波頻率兩者。
在本文中參考其中閘極及汲極墊(例如，105p)在半導體層結構之一頂側/上表面上且一源極墊在一底側/下表面上之實例以橫截面繪示電晶體晶粒(例如，105)。在一些實施例中，電晶體晶粒之一頂側金屬化結構可包含可藉由一或多個各自匯流排連接之複數個閘極、汲極及/或源極「指狀部」。
圖13係沿著圖1A之線A-A'穿過晶粒105之頂側金屬化結構之一部分取得之一剖面圖。如圖13中所展示，電晶體晶粒105包含一半導體層結構130，半導體層結構130具有設置於半導體層結構130之一上部中之複數個單位單元電晶體116。閘極指狀部152、汲極指狀部154及源極指狀部156 (及連接匯流排)可分別定義晶粒105之閘極、汲極及源極連接電極之部分。閘極指狀部152可由能夠與基於III族氮化物之半導體材料形成肖特基接觸(Schottky contact)之材料(諸如Ni、Pt、Cu、Pd、Cr、W及/或WSiN)形成。汲極指狀部154及/或源極指狀部156可包含可與基於III族氮化物之材料形成歐姆接觸之金屬(諸如TiAlN)。閘極指狀部152可藉由一閘極匯流排146彼此電連接，且汲極指狀部154可藉由一汲極匯流排148彼此電連接。為更佳繪示元件，未展示有助於將閘極、汲極及源極連接結構彼此隔離之一或多個介電質層。
圖13中亦展示單位單元電晶體116之一者。如所展示，單位單元電晶體116包含一閘極指狀部152、一汲極指狀部154及一源極指狀部156以及半導體層結構130之下層部分。由於閘極指狀部152電連接至一共同閘極匯流排146，汲極指狀部154電連接至一共同汲極匯流排148，且源極指狀部156經由導電源極通孔166及源極墊電連接在一起，故可見單位單元電晶體116全部並聯電連接在一起。
本發明之實施例可建置於基板或層壓板(例如，一重佈層(RDL)層壓板)上，且使用現代增強型晶圓級封裝技術分批組裝。可一次建置多個零件，從而減少組裝時間、成本及良率問題。另外，可減少或消除線接合程序，從而節省時間及成本。例如，使用有效地移除熱量之一高密度銅填充陣列或嵌入式銅塊(因為典型中空或部分填充之通孔對於高功率RF應用而言將不足以有效地移除熱量)，可有效地移除由電晶體晶粒產生之熱量且將其傳導至封裝外部之一散熱器。本發明之實施例可用於例如用於5G及基地台應用之各種蜂巢式基礎設施(CIFR) RF功率產品(包含但不限於5 W、10 W、20 W、40 W、60 W、80 W及不同頻帶)中。本發明之實施例亦可應用於雷達及單晶微波積體電路(MMIC)類型應用。
本文中已參考其中展示實例實施例之隨附圖式來描述各項實施例。然而，此等實施例可以不同形式體現且不應被解釋為限於本文中所闡述之實施例。實情係，提供此等實施例使得本發明係透徹的且完整的且向熟習此項技術者充分傳達本發明概念。將容易明白對本文中所描述之實例實施例以及一般原理及特徵之各種修改。在圖式中，層及區域之大小及相對大小未按比例展示，且在一些例項中可為清楚起見而被放大。
將理解，儘管術語「第一」、「第二」等在本文中可用於描述各種元件，但此等元件不應受此等術語限制。此等術語僅用於區分一個元件與另一元件。例如，在不脫離本發明之範疇之情況下，一第一元件可被稱為一第二元件，且類似地，一第二元件可被稱為一第一元件。如本文中所使用，術語「及/或」包含相關聯所列品項之一或多者之任何及全部組合。
本文中所使用之術語僅出於描述特定實施例之目的且並不意欲限制本發明。如本文中所使用，除非上下文另有清楚指示，否則單數形式「一」、「一個」及「該」亦意欲包含複數形式。進一步將理解，術語「包括(comprises)」、「包括(comprising)」、「包含(includes)」及/或「包含(including)」在於本文中使用時指定存在所陳述特徵、整數、步驟、操作、元件及/或組件，但並不排除存在或添加一或多個其他特徵、整數、步驟、操作、元件、組件及/或其等之群組。
除非另有定義，否則本文中所使用之所有術語(包含技術及科學術語)具有與本發明所屬技術之一般技術者所普遍理解相同之意義。進一步將理解，本文中所使用之術語應被解釋為具有與其等在本說明書及相關技術之內容背景中之意義一致之一意義，且將不會以一理想化或過於正式之意義進行解釋，除非本文中如此明確定義。
將理解，當一元件(諸如一層、區域或基板)被稱為「在另一元件上」、「附接至另一元件」或「延伸至另一元件上」時，其可直接在該另一元件上或亦可存在中介元件。相比之下，當一元件被稱為「直接在另一元件上」或「直接附接至另一元件」或「直接延伸至另一元件上」時，不存在中介元件。亦將理解，當一元件被稱為「連接」或「耦合」至另一元件時，其可直接連接或耦合至該另一元件或可存在中介元件。相比之下，當一元件被稱為「直接連接」或「直接耦合」至另一元件時，不存在中介元件。
本文中可使用諸如「下方」或「上方」或「上」或「下」或「水平」或「橫向」或「垂直」之相對術語來描述如圖中所繪示之一個元件、層或區域與另一元件、層或區域之一關係。將理解，除圖中所描繪之定向之外，此等術語亦意欲涵蓋裝置之不同定向。
本文中參考橫截面繪示描述本發明之實施例，該等橫截面繪示係本發明之理想化實施例(及中間結構)之示意性繪示。為清楚起見可放大圖式中之層及區域之厚度。另外，應預期由於例如製造技術及/或容限而引起之繪示之形狀之變動。因此，本發明之實施例不應被解釋為限於本文中所繪示之區域之特定形狀，而應包含例如由製造引起之形狀偏差。在所繪示之實施例中，藉由虛線繪示之元件可為選用的。
在各處，相同數字指代相同元件。因此，即使未在對應圖式中提及或描述相同或類似數字，亦可參考其他圖式對其等進行描述。再者，可參考其他圖式來描述未藉由元件符號表示之元件。
在圖式及說明書中，已揭示本發明之典型實施例，且儘管採用特定術語，但該等特定術語僅在一通用及描述性意義上使用而非出於限制目的，本發明之範疇在以下發明申請專利範疇中闡述。
14:線接合/接合線 100a:射頻(RF)功率裝置封裝 100b:射頻(RF)功率裝置封裝 100c:射頻(RF)功率裝置封裝 101:基板 101a:封裝基板/重佈層(RDL)/第一RDL層 101b:基板 101c:第二RDL層 101s:附接表面 102d:汲極引線/封裝引線 102g:閘極引線/封裝引線 102s:源極引線/熱引線 103:導電結構/高密度導電陣列/電接地銅塊 104:MOS電容器/元件/MOS電容器晶片/輸入電容器/輸入電容器晶片/被動射頻(RF)組件/輸入匹配電路 104p:接合墊/凸塊墊/接觸墊 105:主動晶粒/主動電晶體晶粒/元件/主動裝置/組件/射頻(RF)電晶體放大器晶粒 105p:接合墊/凸塊墊/閘極及汲極墊/導電墊/接觸墊/閘極終端/汲極終端 106:高密度電容器/元件/電容器晶片/電容器/輸出電容器/高密度電容器晶片/輸出電容器晶片/被動射頻(RF)組件/輸出匹配電路 106p:接合墊/凸塊墊/接觸墊 107:晶粒附接材料/預成型件/導電晶粒附接材料層 110:被動裝置/整合式被動裝置(IPD)/元件/晶粒/組件 110c:被動裝置/覆晶輸入整合式被動裝置(IPD) 110i:被動裝置/整合式被動裝置(IPD)/整合式互連件/輸入匹配電路 110o:被動裝置/整合式被動裝置(IPD)/輸出阻抗匹配網路/輸出覆晶IPD/輸出IPD/整合式互連件/輸出匹配電路 110oc:被動裝置/輸出整合式被動裝置(IPD)/覆晶輸出IPD/輸出預匹配IPD/覆晶IPD 110p:接合墊/接觸墊 110pl:接觸墊 110r:串聯傳輸線/導電結構 110v:導電通孔/銅通孔 111:導電凸塊/焊料凸塊 112:銅填隙片 113:塑膠包覆模製件(OMP) 114:導電配線結構 116:單位單元電晶體 130:半導體層結構 146:閘極匯流排 148:汲極匯流排 152:閘極指狀部 154:汲極指狀部 156:源極指狀部 166:導電源極通孔 200a:射頻(RF)功率裝置封裝 200b:射頻(RF)功率裝置封裝 201:封裝基板 201s:附接表面 214:重佈層(RDL) 300:射頻(RF)功率裝置封裝 301:封裝基板 301s:附接表面 310r:串聯傳輸線 314:導電配線結構/重佈層(RDL) 314v:導電通孔或柱 400:射頻(RF)功率裝置封裝 410v:導電通孔或柱 500:射頻(RF)功率裝置封裝 500f:封裝覆蓋區 501:封裝基板 501s:附接表面 515:外部電路板 515i:印刷電路板(PCB)電路設計/輸入匹配電路板 515o:印刷電路板(PCB)電路設計/輸出匹配電路板 515v:接地通孔 600a:射頻(RF)功率裝置封裝 600b:射頻(RF)功率裝置封裝 604:級間電容器晶片/級間匹配電容器晶片/元件/電容器/級間匹配電容器 604p:接合墊 605d:驅動器汲極引線 605g:輸出閘極引線 605i:主動晶粒/電晶體晶粒/驅動器級電晶體晶粒/元件/驅動器晶粒/級 605o:主動晶粒/電晶體晶粒/輸出級電晶體晶粒/元件/最後晶粒/級/最後級電晶體晶粒 605p:接合墊/閘極及汲極接觸墊 610:被動裝置/級間被動裝置/整合式被動裝置(IPD) 610c:被動裝置/級間被動裝置/級間整合式被動裝置(IPD) 610p:接合墊 610v:導電通孔 614:重佈層(RDL) 614v:導電通孔 700:射頻(RF)功率裝置封裝 800:射頻(RF)功率裝置封裝 900:射頻(RF)功率裝置封裝 1100:射頻(RF)功率裝置封裝/TEPAC封裝 1101:導電基底或凸緣 1101s:附接表面 1104:側壁部件/側壁 1113:蓋部件 1114:導電配線結構 1200:射頻(RF)功率裝置封裝/T3PAC封裝 1201:導電基底或凸緣 1201s:附接表面 1204:側壁部件/側壁 1208:導電膠 1213:蓋部件 1214:導電配線結構 C:金屬-絕緣體-金屬(MIM)電容器/整合式輸出電容/整合式電容器 G:接地節點/接地引線/輸出接地引線 L:電感器/串聯連接條帶
圖1A、圖1B及圖1C係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的積體電路裝置封裝之實例之橫截面視圖。
圖1D係圖1A、圖1B及圖1C之實施例之一等效電路圖。
圖2A及圖2B係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的積體電路裝置封裝之實例之橫截面視圖。
圖2C係圖2A及圖2B之實施例之一等效電路圖。
圖3A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。
圖3B係圖3A之實施例之一等效電路圖。
圖4A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。
圖4B係圖4A之實施例之一等效電路圖。
圖5A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。
圖5B係圖5A之實施例之一等效電路圖。
圖5C係繪示根據本發明之一些實施例之圖5A之實施例的一封裝覆蓋區之一仰視平面圖。
圖5D係繪示根據本發明之一些實施例之圖5C之實施例的封裝覆蓋區之一俯視平面圖。
圖6A及圖6B係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的積體電路裝置封裝之實例之橫截面視圖。
圖6C係圖6A及圖6B之實施例之一等效電路圖。
圖7A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的一積體電路裝置封裝之一實例之一橫截面視圖。
圖7B係圖7A之實施例之一等效電路圖。
圖8A及圖9A係繪示根據本發明之一些實施例之包含堆疊式拓撲結構的積體電路裝置封裝之子組件之實例之橫截面視圖。
圖8B及圖9B分別為圖8A及圖9A之實施例之等效電路圖。
圖10A及圖10B分別為繪示根據本發明之一些實施例之高Q IPD之實例的平面圖及透視圖。
圖11及圖12係繪示根據本發明之進一步實施例之包含堆疊式拓撲結構的熱增強型積體電路裝置封裝之實例之橫截面視圖。
圖13係穿過圖1A之頂側金屬化結構之一部分取得之一橫截面視圖。
100a:射頻(RF)功率裝置封裝
101a:封裝基板/重佈層(RDL)/第一RDL層
101s:附接表面
102d:汲極引線/封裝引線
102g:閘極引線/封裝引線
102s:源極引線/熱引線
103:導電結構/高密度導電陣列/電接地銅塊
104:MOS電容器/元件/MOS電容器晶片/輸入電容器/輸入電容器晶片/被動射頻(RF)組件/輸入匹配電路
104p:接合墊/凸塊墊/接觸墊
105:主動晶粒/主動電晶體晶粒/元件/主動裝置/組件/射頻(RF)電晶體放大器晶粒
105p:接合墊/凸塊墊/閘極及汲極墊/導電墊/接觸墊/閘極終端/汲極終端
106:高密度電容器/元件/電容器晶片/電容器/輸出電容器/高密度電容器晶片/輸出電容器晶片/被動射頻(RF)組件/輸出匹配電路
106p:接合墊/凸塊墊/接觸墊
107:晶粒附接材料/預成型件/導電晶粒附接材料層
110i:被動裝置/整合式被動裝置(IPD)/整合式互連件/輸入匹配電路
110o:被動裝置/整合式被動裝置(IPD)/輸出阻抗匹配網路/輸出覆晶IPD/輸出IPD/整合式互連件/輸出匹配電路
110p:接合墊/接觸墊
111:導電凸塊/焊料凸塊
112:銅填隙片
113:塑膠包覆模製件(OMP)

Claims (20)

  1. 一種積體電路裝置封裝，其包括：一基板；一第一晶粒，其包括附接至該基板之主動電子組件；及至少一個整合式互連結構，其在該第一晶粒上且與該基板相對，該至少一個整合式互連結構自該第一晶粒延伸到至少一個封裝引線或延伸到一或多個被動組件，且提供其等之間之電連接。
  2. 如請求項1之積體電路裝置封裝，其中該電連接不具有一線接合。
  3. 如請求項1之積體電路裝置封裝，其中：該第一晶粒包括在該第一晶粒之與該基板相對之一表面上之一第一接合墊，該第一接合墊電連接至該等主動電子組件之一或多者；及該至少一個整合式互連結構包括在該第一接合墊上之一接觸墊。
  4. 如請求項3之積體電路裝置封裝，其中該至少一個整合式互連結構包括在一重佈層上之一導電配線圖案。
  5. 如請求項3之積體電路裝置封裝，其中該至少一個整合式互連結構包括用於由該第一晶粒之該等主動電子組件定義之一電路的一阻抗匹配網路之至少一部分。
  6. 如請求項5之積體電路裝置封裝，其中該至少一個整合式互連結構包括包含一或多個被動電子組件之一被動裝置。
  7. 如請求項6之積體電路裝置封裝，其中該接觸墊係在該被動裝置之面向該第一晶粒之該表面之一表面上的一第二接合墊，該第二接合墊電連接至該一或多個被動電子組件，其中該第二接合墊藉由該第二接合墊與該第一接合墊之間之一導電凸塊連接至該第一接合墊。
  8. 一種積體電路裝置封裝，其包括：一基板；一第一晶粒，其包括附接至該基板之主動電子組件；及至少一個整合式互連結構，其在該第一晶粒上且與該基板相對，該至少一個整合式互連結構自該第一晶粒延伸至附接至該基板之一鄰近晶粒及/或朝向至少一個封裝引線，且提供其等之間之電連接；其中該第一晶粒之該等主動電子組件定義一第一射頻(RF)放大器電路，其中該鄰近晶粒包括定義一第二RF放大器電路之主動電子組件，且其中該等第一及第二功率放大器電路藉由該被動裝置連接成一多級放大器配置。
  9. 如請求項6之積體電路裝置封裝，其中該被動裝置包括包含至少一個電感器之一整合式被動裝置(IPD)且不具有主動電子組件。
  10. 如請求項9之積體電路裝置封裝，其中該IPD包括介於其之導電元件 之間之一絕緣材料，以定義整合於其中之至少一個電容器。
  11. 一種積體電路裝置封裝，其包括：一基板；一第一晶粒，其包括附接至該基板之主動電子組件；及至少一個整合式互連結構，其在該第一晶粒上且與該基板相對，該至少一個整合式互連結構自該第一晶粒延伸至附接至該基板之一鄰近晶粒及/或朝向至少一個封裝引線，且提供其等之間之電連接，其中：該鄰近晶粒包括一或多個電容器及在該鄰近晶粒之與該基板相對之一表面上的至少一個電容器接合墊；該至少一個整合式互連結構之該接觸墊係一第一接觸墊；及該至少一個整合式互連結構進一步包括在該至少一個電容器接合墊上之至少一個第二接觸墊。
  12. 如請求項11之積體電路裝置封裝，其中該至少一個封裝引線包括一閘極引線且該第一接合墊係一閘極墊，其中該鄰近晶粒在該第一晶粒與該閘極引線之間，且其中該至少一個整合式互連結構包括用於由該第一晶粒的該等主動電子組件定義的一電路之一輸入阻抗匹配網路的至少一部份。
  13. 如請求項11之積體電路裝置封裝，其中該至少一個封裝引線包括一汲極引線且該第一接合墊係一汲極墊，其中該鄰近晶粒在該第一晶粒與該汲極引線之間，且其中該至少一個整合式互連結構包括用於由該第一晶粒的該等主動電子組件定義的一電路之一輸出阻抗匹配網路的至少一部份。
  14. 如請求項1之積體電路裝置封裝，其中該等主動電子組件包括功率電晶體裝置，且其中該第一晶粒包括III族氮化物及/或碳化矽。
  15. 一種射頻(RF)功率放大器裝置封裝，其包括：一基板；一第一晶粒，其包括複數個電晶體單元，在其之一底表面上之一源極墊處附接至該基板且在其之與該基板相對之一頂表面處包括一閘極或汲極墊；封裝引線，其等經組態以在該第一晶粒之該閘極或汲極墊與一外部裝置之間傳導電信號；及一整合式互連結構，其在該第一晶粒上且與該基板相對，該整合式互連結構包括在該閘極或汲極墊上之一第一接觸墊，及在附接至該基板之一鄰近晶粒上及/或耦合至該等封裝引線之一者的至少一個第二接觸墊。
  16. 如請求項15之RF功率放大器裝置封裝，其中該整合式互連結構提供自該第一晶粒之該閘極或汲極墊至該鄰近晶粒及/或至該等封裝引線之該一者的電連接，其中該電連接不具有一線接合。
  17. 如請求項15之RF功率放大器裝置封裝，其中該整合式互連結構包括在一重佈層上之一導電配線圖案，或包含一或多個被動電子組件之一被動裝置。
  18. 如請求項17之RF功率放大器裝置封裝，其中該整合式互連結構包括用於由該第一晶粒之該等電晶體定義之一電路的一阻抗匹配網路之至少一部分。
  19. 如請求項18之RF功率放大器裝置封裝，其中該第一接觸墊係在該被動裝置之面向該第一晶粒之該頂表面之一表面上的一接合墊，該接合墊電連接至該一或多個被動電子組件，其中該接合墊藉由該接合墊與該閘極或汲極墊之間之一導電凸塊連接至該閘極或汲極墊。
  20. 如請求項17之RF功率放大器裝置封裝，其中該鄰近晶粒包括在其之與該基板相對之一表面上之至少一個接合墊，且該至少一個第二接觸墊在該至少一個接合墊上，其中：該鄰近晶粒包括一或多個電容器；或該鄰近晶粒包括定義一RF放大器電路之一級之複數個電晶體單元。
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