TWI780885B - 形成電晶體的方法 - Google Patents

形成電晶體的方法 Download PDF

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TWI780885B
TWI780885B TW110132360A TW110132360A TWI780885B TW I780885 B TWI780885 B TW I780885B TW 110132360 A TW110132360 A TW 110132360A TW 110132360 A TW110132360 A TW 110132360A TW I780885 B TWI780885 B TW I780885B
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Taiwan
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layer
dielectric layer
silicon
dielectric
stack
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TW110132360A
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TW202230520A (zh
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林文凱
張哲豪
志安 徐
盧永誠
陳思穎
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括進行原子層沉積(atomic layer deposition,ALD)製程以在晶圓上形成介電層。此ALD製程包含ALD循環，此ALD循環包括脈衝輸送卡利梭(calypso,(SiCl3)2CH2)、清除此calypso、脈衝輸送氨氣及清除此氨氣。此方法進一步包括對此介電層進行濕式退火製程，以及對此介電層進行乾式退火製程。

Description

形成電晶體的方法
本揭示內容是關於一種形成電晶體的方法。
在諸如電晶體之積體電路的形成中，介電層通常需具有高抗蝕刻性，以使得在蝕刻其他特徵時其不會損壞。因此，通常使用一些高k介電材料，諸如SiOCN、SiON、SiOC、SiCN等。然而，高k材料導致寄生電容增加。
根據一些實施方式，一種形成電晶體的方法，包含：進行原子層沉積(atomic layer deposition,ALD)製程以在晶圓上形成介電層，ALD製程包含ALD循環，ALD循環包含脈衝輸送(SiCl3)2CH2、清除(SiCl3)2CH2、脈衝輸送氨氣，以及清除氨氣；對介電層進行濕式退火製程；以及對介電層進行乾式退火製程。
根據一些實施方式，一種形成電晶體的方法包含：形成疊層，疊層包含：第一矽層及第二矽層；以及第一矽層與第二矽層之間的矽鍺層；使矽鍺層橫向凹陷以形成橫向凹槽；沉積介電層，其中介電層延伸至橫向凹槽中；使 介電層退火以降低介電層的k值；修整介電層以移除這些橫向凹槽外之介電層的第一部分，而這些凹槽內之介電層的第二部分保留為內間隔墊；移除矽鍺層；以及形成延伸至第一矽層與第二矽層之間的間隔墊中的閘極堆疊。
根據一些實施方式，一種形成電晶體的方法包含：形成疊層，疊層包含：複數個半導體奈米結構；以及複數個犧牲層，其中這些半導體奈米結構與這些犧牲層交替安置；使這些犧牲層橫向凹陷以形成橫向凹槽；以及沉積延伸至這些橫向凹槽中的介電層，其中使用(SiCl3)2CH2及氨氣作為前驅物來沉積介電層。
2A:第一層
2B:第二層
10:晶圓
20:基板
20':基板條
22:多層堆疊
22':堆疊
22A:犧牲層
22B:奈米結構
23:溝槽
24:半導體條
26:淺溝槽隔離區
26T:頂表面
28:突出鰭片
30:虛設閘極堆疊
32:虛設閘極介電質
34:虛設閘電極
36:硬遮罩
38:閘極間隔墊
38A:內層
38B:外層
41:橫向凹槽
42:凹槽
43:間隔層
44:內間隔墊
48:磊晶源極/汲極區
49:空隙
50:接觸蝕刻停止層
52:層間介電質
58:凹槽
62:閘極介電質
68:閘電極
70:閘極堆疊
74:閘極遮罩
76:層間介電質
78:矽化物區
80A:接觸插塞
80B:接觸插塞
82:奈米FET
110:基層
112/10:結構
114/10:結構
116/10:結構
118/10:結構
120/10:結構
122/10:結構
124:結構
126:ALD循環
130:製程
132:製程
134:製程
136:濕式退火製程
138:乾式退火製程
140:薄膜成熟製程
150:線
152:線
160:線
162:線
200:製程流程
202:製程
204:製程
206:製程
208:製程
210:製程
212:製程
214:製程
216:製程
218:製程
220:製程
222:製程
224:製程
226:製程
228:製程
230:製程
232:製程
234:製程
236:製程
238:製程
240:製程
A1:參考橫截面
A2:參考橫截面
B:參考橫截面
當結合隨附圖式閱讀時，根據以下詳細描述能最好地理解本揭示案的態樣。需注意，根據工業中的標準實務，各種特徵並未按比例繪製。事實上，為了討論的清晰起見，可任意增加或減少各種特徵的尺寸。
第1-4、5A、5B、6A、6B、7A、7B、8A、8B、9A、9B、9C、10A、10B、11A、11B、11C、12A、12B、13A、13B、14A、14B、15A、15B、16A、16B、17A、17B、17C、18A、18B及18C圖示出根據一些實施例之環繞式閘極(Gate All-Around,GAA)電晶體形成中之中間階段的橫截面圖。
第19圖示出根據一些實施例之SiOCN薄膜形成中的原子層沉積(Atomic Layer Deposition,ALD)循環及退火 製程。
第20圖示出根據一些實施例之卡利梭(calypso)的化學結構。
第21圖示出根據一些實施例之由兩個ALD循環形成的化學結構。
第22及23圖示出根據一些實施例之隨k值變化之一些介電材料的蝕刻速率。
第24圖示出根據一些實施例之用於形成GAA電晶體的製程流程。
第25圖示出根據一些實施例之用於沉積間隔層的製程流程。
以下揭示內容提供了許多不同的實施例或實例，用於實施本揭示內容的不同特徵。下面描述部件及佈置的特定實例以簡化本揭示案。當然，這些僅為實例且並非旨在為限制性的。例如，在隨後的描述中在第二特徵上方或上面形成第一特徵可包括其中第一及第二特徵直接接觸形成的實施例，且亦可包括其中附加特徵可形成於第一與第二特徵之間，使得第一及第二特徵可不直接接觸的實施例。此外，本揭示案可在各個實例中重複元件符號及/或字母。此重複係出於簡單及清晰的目的，且其本身並不規定所討論之各個實施例及/或配置之間的關係。
此外，為了便於描述，本文中可使用諸如「在下」、 「下面」、「下方」、「在上」、「上方」及其類似者的空間相對術語來描述一個元件或特徵與另一元件或特徵的關係，如圖所示。除了圖中描繪的定向之外，空間相對術語旨在涵蓋使用或操作中之元件的不同定向。裝置可以其他方式定向(旋轉90度或定向於其他定向)且可同樣相應地解釋本文使用的空間相對描述語。
提供一種具有降低的k值及改進的抗蝕刻性之內間隔墊的環繞式閘極(GAA)電晶體。亦提供一種形成GAA電晶體的方法。根據本揭示案的一些實施例，藉由使用calypso((SiCl3)2CH2)及氨氣(NH3)作為前驅物沉積介電薄膜來形成內間隔墊。執行沉積後成熟製程，其包括濕式退火製程及乾式退火製程。所得介電層具有降低的k值以及改進的對後續蝕刻及清洗製程的抗蝕刻性。介電薄膜亦可用於形成其他特徵，諸如閘極間隔墊。本文中討論的實施例將提供實例以使得能夠製造或使用本揭示案的標的物，且所屬技術領域具有通常知識者將容易理解在保持在不同實施例之預期範疇內的同時可進行的修改。在各種視圖及說明性實施例中，相同的元件符號用於指定相同的元件。儘管將方法實施例討論為以特定次序進行，但可以任何邏輯次序進行其他方法實施例。
第1-4、5A、5B、6A、6B、7A、7B、8A、8B、9A、9B、9C、10A、10B、11A、11B、11C、12A、12B、13A、13B、14A、14B、15A、15B、16A、16B、17A、17B、17C、18A、18B及18C圖示出根據本揭 示案之一些實施例之GAA電晶體形成中的中間階段之橫截面圖。對應的製程亦在第24圖所示的製程流程中示意性地反映出來。
參考第1圖，示出晶圓10的透視圖。晶圓10包括多層結構，此多層結構包含基板20上的多層堆疊22。根據一些實施例，基板20為半導體基板，其可為矽基板、矽鍺(SiGe)基板或其類似者，同時可使用其他基板及/或結構，諸如絕緣層上半導體(semiconductor-on-insulator,SOI)、應變SOI、絕緣層上矽鍺或其類似者。基板20可經摻雜為p型半導體，但在其他實施例中，其可經摻雜為n型半導體。
根據一些實施例，多層堆疊22經由一連串用於沉積交替材料的沉積製程形成。各別製程在第24圖所示的製程流程200中示出為製程202。根據一些實施例，多層堆疊22包含由第一半導體材料形成的第一層2A及由不同於第一半導體材料的第二半導體材料形成的第二層2B。
根據一些實施例，第一層2A的第一半導體材料包含SiGe、Ge、Si、GaAs、InSb、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或其類似者或由其形成。根據一些實施例，第一層2A(例如，SiGe)的沉積係經由磊晶生長進行，且對應的沉積方法可為氣相磊晶(Vapor-Phase Epitaxy,VPE)、分子束磊晶(Molecular Beam Epitaxy,MBE)、化學氣相沉積(Chemical Vapor deposition,CVD))、低壓CVD (Low Pressure CVD,LPCVD)、原子層沉積(ALD)、超高真空CVD(Ultra High Vacuum CVD,UHVCVD)、減壓CVD(Reduced Pressure CVD,RPCVD)或其類似者。根據一些實施例，第一層2A形成為約30Å與約300Å之間的範圍內的第一厚度。然而，可使用任何適合的厚度同時保持在實施例的範疇內。
一旦第一層2A沉積在基板20上，第二層2B則沉積在第一層2A上。根據一些實施例，第二層2B包括諸如Si、SiGe、Ge、GaAs、InSb、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、這些的組合或其類似者的第二半導體材料或由其形成，第二半導體材料不同於第一層2A的第一半導體材料。例如，根據其中第一層2A為矽鍺的一些實施例，第二層2B可由矽形成，反之亦然。應當理解，任何適合的材料組合可用於第一層2A及第二層2B。
根據一些實施例，使用與用於形成第一層2A的沉積技術相似的沉積技術在第一層2A上磊晶生長第二層2B。根據一些實施例，第二層2B形成為與第一層2A的厚度相似的的厚度。第二層2B亦可形成為與第一層2A不同的厚度。根據一些實施例，第二層2B可形成為例如約10Å與約500Å之間的範圍內的第二厚度。
一旦第二層2B形成在第一層2A上形成，重複沉積製程以形成多層堆疊22中的剩餘層，直至已形成多層堆疊22的期望最頂層。根據一些實施例，第一層2A具有彼 此相同或相似的厚度，且第二層2B具有彼此相同或相似的厚度。第一層2A亦可具有與第二層2B的厚度相同的厚度或不同的厚度。根據一些實施例，第一層2A在後續製程中經移除，且在整個描述中交替地被稱為犧牲層22A。根據替代實施例，第二層2B為犧牲性的，且在後續製程中經移除。
根據一些實施例，存在於多層堆疊22上形成的一些襯墊氧化物層及硬遮罩層(未示出)。這些層經圖案化，且用於多層堆疊22的後續圖案化。
參考第2圖，在蝕刻製程中圖案化多層堆疊22及下層基板20的部分，從而形成溝槽23。各別製程在第24圖所示的製程流程200中示出為製程204。溝槽23延伸至基板20中。多層堆疊的剩餘部分在下文中被稱為多層堆疊22’。在多層堆疊22’之下，留下了基板20的一些部分，且此些部分在下文中被稱為基板條20’。多層堆疊22’包括犧牲層22A及奈米結構22B。犧牲層22A可交替地被稱為半導體層，且奈米結構22B可交替地被稱為半導體層。多層堆疊22’的部分及下層基板條20’被統稱為半導體條24。
在上述實施例中，GAA電晶體結構可藉由任何適合的方法圖案化。例如，可使用一或多種微影製程使結構圖案化，此些微影製程包括雙重圖案化或多重圖案化製程。大體上，雙重圖案化或多重圖案化製程結合微影及自對準製程，從而允許產生具有例如比使用單個直接微影製程可 獲得的間距更小之間距的圖案。例如，在一個實施例中，犧牲層形成在基板上方且使用微影製程圖案化。使用自對準製程在圖案化犧牲層旁邊形成間隔墊。隨後移除犧牲層，且隨後可使用剩餘間隔墊來使GAA結構圖案化。
第3圖示出隔離區的形成，隔離區在整個描述中亦被稱為淺溝槽隔離(Shallow Trench Isolation,STI)區26。各別製程在第24圖所示的製程流程200中示出為製程206。STI區26可包括襯底氧化物(未示出)，此襯底氧化物可為經由基板20之表面層的熱氧化形成的熱氧化物。襯底氧化物亦可為使用例如ALD、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition,HDPCVD)、CVD或其類似者形成的沉積氧化矽層。STI區26亦可包括襯底氧化物上的介電材料，其中可使用可流動化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)、旋塗、HDPCVD或其類似者形成介電材料。隨後可進行諸如化學機械拋光(Chemical Mechanical Polish,CMP)製程或機械研磨製程的平坦化製程以平整介電材料的頂表面，且介電材料的剩餘部分為STI區26。
隨後使STI區26凹陷，使得半導體條24的頂部突出高於STI區26之剩餘部分的頂表面26T以形成突出鰭片28。突出鰭片28包括多層堆疊22'及基板條20'的頂部。STI區26的凹陷可經由乾式蝕刻製程來進行，其中例如NF3和NH3用作蝕刻氣體。在蝕刻製程期間，可能 會產生電漿。亦可包括氬氣。根據本揭示案的替代實施例，STI區26的凹陷經由濕式蝕刻製程來進行。例如，蝕刻化學品可包括HF。
參考第4圖，在(突出)鰭片28的頂表面及側壁上形成虛設閘極堆疊30及閘極間隔墊38。各別製程在第24圖所示的製程流程200中示出為製程208。虛設閘極堆疊30可包括虛設閘極介電質32及虛設閘極介電質32上的虛設閘電極34。可藉由氧化突出鰭片28的表面部分以形成氧化物層或藉由沉積諸如氧化矽層的介電層來形成虛設閘極介電質32。可例如使用多晶矽或非晶矽來形成虛設閘電極34，且亦可使用其他材料，諸如非晶碳。虛設閘極堆疊30中的每一者亦可包括虛設閘電極34上的一個(或複數個)硬遮罩36。硬遮罩36可由氮化矽、氧化矽、碳氮化矽、氧碳氮化矽或其多層形成。虛設閘極堆疊30可跨越單個或複數個突出鰭片28及突出鰭片28之間的STI區26。虛設閘極堆疊30亦具有與突出鰭片28的縱向方向垂直的縱向方向。虛設閘極堆疊30的形成包括形成虛設閘極介電層，在虛設閘極介電層上沉積虛設閘電極層，沉積一或多個硬遮罩層，以及隨後經由圖案化製程使形成的層圖案化。
接著，在虛設閘極堆疊30的側壁上形成閘極間隔墊38。根據本揭示案的一些實施例，閘極間隔墊38由諸如氮化矽(SiN)、氧化矽(SiO2)、碳氮化矽(SiCN)、氧氮化矽(SiON)、氧碳氮化矽(SiOCN)或其類似者的介電 材料形成，且可具有單層結構或包括複數個介電層的多層結構。閘極間隔墊38的形成製程可包括沉積一個或複數個介電層，且隨後在介電層上進行各向異性蝕刻製程。介電層的剩餘部分為閘極間隔墊38。
根據替代實施例，可使用如第19圖所示的製程形成閘極間隔墊38的一或多層，且閘極間隔墊38的所得層包含參考第19至21圖所討論的材料。例如，閘極間隔墊38可由其中的SiOCNH形成或包括其中的SiOCNH。形成製程的細節將在後續段落中討論。
第5A及5B圖示出第4圖所示結構的橫截面圖。第5A圖示出第4圖中的參考橫截面A1-A1，此橫截面切貫突出鰭片28之未被閘極堆疊30及閘極間隔墊38覆蓋的部分，且垂直於閘極長度方向。亦示出位於突出鰭片28之側壁上的鰭片閘極間隔墊38。第5B圖示出第4圖中的參考橫截面B-B，此參考橫截面平行於突出鰭片28的縱向方向。
參考第6A及6B圖，不直接位於虛設閘極堆疊30及閘極間隔墊38下方之突出鰭片28的部分經由蝕刻製程凹陷以形成凹槽42。各別製程在第24圖所示的製程流程200中示出為製程210。例如，可使用C2F6、CF4、SO2、HBr、Cl2及O2的混合物，HBr、Cl2、O2及CH2F2的混合物或其類似者進行乾式蝕刻製程以蝕刻多層半導體堆疊22’及下層基板條20’。凹槽42的底部至少與多層半導體堆疊22'的底部齊平或可低於(如第6B圖所示)多 層半導體堆疊22'的底部。蝕刻可為各向異性的，使得面向凹槽42之多層半導體堆疊22'的側壁為垂直且筆直的，如第6B圖所示。
參考第7A及7B圖，犧牲層22A經橫向凹陷以形成橫向凹槽41，橫向凹槽41自相應上層及下層奈米結構22B的邊緣凹陷。各別製程在第24圖所示的製程流程200中示出為製程212。犧牲層22A的橫向凹陷可經由濕式蝕刻製程達成，此濕式蝕刻製程使用對犧牲層22A的材料(例如，矽鍺(SiGe))比對奈米結構22B及基板20的材料(例如，矽(Si))更具選擇性的蝕刻劑。例如，在犧牲層22A由矽鍺形成且奈米結構22B由矽形成的實施例中，可使用諸如鹽酸(HCl)的蝕刻劑來進行濕式蝕刻製程。濕式蝕刻製程可使用浸漬製程、噴塗製程、旋塗製程或其類似者來進行，且可使用任何適合製程溫度(例如，在約400℃與約600℃之間)及適合製程時間(例如，在約100秒與約1,000秒之間)來進行。根據替代實施例，犧牲層22A的橫向凹陷經由各向同性乾式蝕刻製程或乾式蝕刻製程及濕式蝕刻製程的組合來進行。
第8A及8B圖示出其中包含SiOCNH之間隔層43的沉積。各別製程在第24圖所示的製程流程200中示出為製程214。間隔層43經沉積為共形層，且具有相對低的k值，此k值可處於約3.4至約4.2的範圍。因此，間隔層43有時可形成為低k介電層(當其k值低於約3.8時)，這取決於形成製程。間隔層43的厚度可處於約4nm 與約6nm之間的範圍內。
第19圖示出用於沉積間隔層43之製程214的一些細節，其中示出間隔層43的一些實例中間化學結構。應當理解，第19圖中所示(且參考第19圖討論)的製程及結構為示意性的，且亦可能產生其他反應機制及結構。第19圖中所示的中間結構使用元件符號112、114、116、118、120及122來識別，以將不同步驟產生的結構彼此區分。晶圓10包括基層110，基層110可代表暴露的特徵，包括第8A及8B圖中的基板20、犧牲層22A及奈米結構22B。第19圖中的初始結構被稱為結構112。在所示實例中，基層110被示為包括矽，此矽可呈結晶矽、非晶矽、多晶矽、SiGe或其類似者的形式。基層110亦可包括其他類型的含矽化合物，諸如氧化矽、氮化矽、氧碳化矽、氧氮化矽或其類似者，此些含矽化合物可形成閘極間隔墊38及硬遮罩36。根據本揭示案的一些實施例，由於形成天然氧化物及暴露於濕氣，在含矽基層110的表面形成Si-OH鍵。
再次參考第19圖，進行第一ALD循環以沉積如第8B圖中的間隔層43。參考製程130，將calypso((SiCl3)2CH2)引入/脈衝輸送至ALD腔室中，在此ALD腔室中置放晶圓10(第8A及8B圖)。各別製程示出為如第25圖所示的製程130。calypso具有化學式(SiCl3)2CH2，且第20圖示出calypso分子的化學結構。化學結構表明，calypso分子包含與兩個矽原子鍵結的氯 原子，此些矽原子與一個碳原子鍵結形成Si-C-Si鍵。當將calypso脈衝輸送至ALD腔室時，可將晶圓10加熱至例如約300℃與約600℃之間的範圍內的溫度。結構112(第19圖)中所示的OH鍵斷裂，且矽原子連同與其鍵結的氯原子與氧原子鍵結以形成O-Si-Cl鍵。亦形成Si-C-Si(C在CH2中)以形成連接兩個Si-O鍵的橋結構。所得結構被稱為結構114。根據本揭示案的一些實施例，當引入calypso時不開啟電漿。calypso氣體可在ALD腔室中保持約20秒與約25秒之間的時間段。根據一些實施例，ALD腔室的壓力可處於約100Pa與約150Pa之間的範圍內。
接著，自ALD腔室清除calypso。各別製程亦示出為如第25圖所示的製程130。接著，進一步參考第19圖，進行製程132，且將包括氮原子及/或氫原子的製程氣體脈衝輸送至ALD腔室中。例如，可脈衝輸送氨氣(NH3)。各別製程在如第25圖所示的製程214中示出為製程132。隨著氨氣的引入/脈衝輸送，晶圓10的溫度亦保持例如約300℃與約600℃之間的範圍內的高溫。根據本揭示案的一些實施例，當引入氨氣時不開啟電漿。在氨氣的脈衝輸送期間，ALD腔室可具有約800Pa與約1,000Pa之間的範圍內的壓力。
結構114與氨氣反應。所得結構被稱為結構116，如第19圖所示。在反應期間，結構114中的一些Si-Cl鍵斷裂，使得NH2分子可能與矽原子鍵結。氨氣可在ALD 腔室中保持約5秒與約15秒之間的範圍內的時間段，且隨後自ALD腔室中清除。各個清除製程在如第25圖所示的製程214中亦示出為製程210。
在上述製程中，製程130及132的組合可被稱為ALD循環126，其中ALD循環126使得原子層生長，此原子層包括矽原子及對應的鍵結氯原子、NH2及CH2基團。
可重複ALD循環126(第25圖)以增加間隔層43的厚度。第21圖示出實例結構124，其中示出間隔層43的附加層，更多的calypso分子附接到下層結構。重複ALD循環直至間隔層43達到諸如約4nm與約6nm之間的範圍內的期望厚度。
根據一些實施例，在ALD循環之後，晶圓10可經歷真空破壞(第19圖中的製程134)，且暴露於空氣。各別製程示出為如第25圖所示的製程134。根據一些實施例，間隔層43暴露於濕氣(H2O)導致一些Si-N鍵(Si-NH2)斷裂，且矽原子與OH基團鍵結。因此形成結構118(第19圖)。根據替代實施例，不發生真空破壞，且將晶圓10保持在ALD腔室中。因此，沉積層將保持具有如第19圖中的結構116及第21圖中的結構124所表示的結構。
接著，參考第19圖，進行薄膜成熟製程140。在第25圖中示出各別製程。薄膜成熟製程140包括濕式退火製程136(第19圖)。各別製程亦示出為如第25圖所 示的濕式退火製程136。在濕式退火製程136中，沉積結構在爐中退火，水蒸汽(H2O)被引入爐中。濕式退火製程可在一個大氣壓的壓力下進行，然而其亦可在低於一個大氣壓的壓力下在製程腔室(諸如用於沉積間隔層43的ALD腔室)中進行。濕式退火製程導致更多的Si-N鍵(Si-NH2)斷裂，且矽原子與OH基團鍵結。濕式退火製程之後，亦可能留下一些NH2分子。濕式退火製程可在約300℃與約500℃之間的範圍內的溫度下進行。濕式退火製程的持續時間可處於約0.5小時與約6小時之間的範圍內。所得結構亦可由結構120表示，如第19圖所示。
根據替代實施例，進行氧化製程，而不進行濕式退火製程，在此氧化製程中氧氣(O2)用作製程氣體。氧化製程亦可在壓力為一個大氣壓的爐中或在壓力低於一個大氣壓的製程腔室(諸如ALD腔室)中進行。氧化製程可在約300℃與約500℃之間的範圍內的溫度下進行。氧化的持續時間可處於約0.5小時與約6小時之間的範圍內。在氧化製程中，氧亦可取代NH2的NH部分(其與Si原子鍵結)以形成Si-OH鍵，且所得結構亦可用結構120表示。
在濕式退火製程或氧化製程之後，進行乾式退火製程138，此亦為薄膜成熟製程的一部分，如第19圖所示。各別製程在如第25圖所示的製程214中亦示出為乾式退火製程138。在乾式退火製程中，諸如氮氣(N2)、氬氣或其類似者的無氧製程氣體可用於帶走產生的H2O蒸汽。乾式退火製程的溫度可高於濕式退火製程的溫度。根據本揭 示案的一些實施例，乾式退火製程在約400℃與約600℃之間的範圍內的溫度下進行。乾式退火製程可持續約0.5小時與約6小時之間的範圍內的時間段。壓力可為約1個大氣壓。
如第19圖所示的結構122代表乾式退火製程之後形成的實例結構。結構122包括連接在一起的兩個相鄰結構120。根據一些實施例，第一結構120中的第一Si-OH鍵及第二結構120中的第二Si-OH鍵均斷裂，從而產生Si-O-Si鍵142及H2O分子。H2O分子被帶走，且因此所得乾式退火製程亦被稱為除濕製程。此外，一些Si-CH2-Si鍵(其包括Si-C-Si鍵)與H2O分子(在空氣中或由除濕製程產生)反應形成Si-OH鍵及Si-CH3鍵。所得薄膜為間隔層43，其亦在第8A及8B圖中示出。Si-CH3鍵的形成導致所得間隔層43的k值降低。例如，在進行薄膜成熟製程140之前，沉積態間隔層43的k值可處於約4.5與約6.0之間的範圍內，且在薄膜成熟製程之後，沉積間隔層43的k值可處於約3.4與約4.2之間的範圍內。根據其中間隔層43具有低於約3.8(且可在約3.5與3.8之間的範圍內)之k值的一些實施例，間隔層43為低k介電層。由於相對少量的氫，間隔層43亦被稱為SiOCNH層或SiOCN層。
如前所述，第19圖所示的製程亦可用於在閘極間隔墊38中形成一或多層。例如，閘極間隔墊38可包括與虛設閘極堆疊30接觸的內層38A(第8A圖)及外層38B。 內層38A及外層38B中的一或兩者可藉由使用如第19圖所示的製程沉積介電層來形成，隨後為各向異性蝕刻製程以移除介電層的水平部分，從而留下介電層的垂直部分作為閘極間隔墊。使用如第19圖所示的製程形成閘極間隔墊38可降低k值，且減小閘極與源極/汲極區之間的寄生電容。另一方面，所得閘極間隔墊38亦具有改進的抗蝕刻性，這有助於元件可靠度。例如，在虛設閘極堆疊30的後續移除中，內層38A暴露於蝕刻化學品及清洗化學品，且內層38A的改進的抗蝕刻性有利地使得對閘極間隔墊38的損壞減少。
根據一些實施例，根據本揭示案的實施例形成的介電薄膜(諸如間隔層43、第8B圖或閘極間隔墊38)可具有降低的密度及降低的k值。例如，密度可處於約1.7g/cm3與約2.0g/cm3之間的範圍內，這低於由SiOCN、SiON、SiOC、SiCN或其類似者形成之習知介電薄膜的密度(2.0g/cm3)。如前所述，k值可處於約3.4與約4.2之間的範圍內，且低於習知介電薄膜的k值。介電薄膜可具有約25%及與35%之間的範圍內的矽原子百分比、約8%與約18%之間的範圍內的碳原子百分比、約30%與約60%之間的範圍內的氧原子百分比，以及約5%與約25%之間的範圍內的氮原子百分比。介電薄膜中亦存在一些氫(例如，原子百分比處於約1原子百分比與約5原子百分比之間的範圍內)，且因此所得薄膜為SiOCNH薄膜。
返回參考第8A及8B圖，間隔層43可為共形層，其延伸至橫向凹槽41(第7B圖)中。接著，進行蝕刻製程(亦被稱為間隔墊修整製程)以修整側向凹槽41之外的間隔層43的部分，從而留下側向凹槽41中之間隔層43的部分。各別製程在第24圖所示的製程流程200中示出為製程216。間隔層43的剩餘部分被稱為內間隔墊44。第9A及9B圖示出根據一些實施例之內間隔墊44的橫截面圖。間隔層43的蝕刻可經由濕式蝕刻製程來進行，其中蝕刻化學品可包括H2SO4、稀HF、氨溶液(NH4OH，氨的水溶液)或其類似者或其組合。
根據替代實施例，如第9A和9B圖所示的修整製程可在用於沉積間隔層43的ALD循環126之後且在如第19圖所示的薄膜成熟製程140之前進行，而非在此薄膜成熟製程之後進行。
儘管內間隔墊44的內側壁及外側壁在第9B圖中經示意性地示出為筆直的，但內間隔墊44的外側壁可為凹面的或凸面的。作為實例，第9C圖示出一實施例的放大視圖，在此實施例中，犧牲層22A的側壁為凹面的，內間隔墊44的外側壁為凹面的，且內間隔墊44自奈米結構22B的相應側壁凹陷。內間隔墊44可用於防止對後續形成的源極/汲極區(諸如磊晶源極/汲極區48)造成損壞，此損壞可能由用於形成替代閘極結構的後續蝕刻製程(第14B圖)引起。
在後續製程中，可進行預清洗製程以移除形成在包 括奈米結構22B及基板20之半導體材料之表面上的氧化物。各別製程在第24圖所示的製程流程200中示出為製程218。預清洗製程可使用SiCONi(NF3及NH3)、Certas(HF及NH3)、HF(氣體)、HF溶液或其類似者來進行。由於存在交聯鍵Si-O-Si，內間隔墊44對預清洗製程具有更多抗性(與具有相似k值的習知介電材料相比)。
參考第10A及10B圖，磊晶源極/汲極區48形成在凹槽42中。各別製程在第24圖所示的製程流程200中示出為製程220。根據一些實施例，磊晶源極/汲極區48可對用作對應GAA電晶體之通道的奈米結構22B施加壓力，從而提高效能。取決於所得電晶體為p型電晶體還是n型電晶體，p型或n型雜質可隨著磊晶的進行原位摻雜。例如，當所得電晶體為p型電晶體時，可使矽鍺硼(SiGeB)、矽硼(SiB)或其類似者生長。相反，當所得電晶體為n型電晶體時，可使矽磷(SiP)、矽碳磷(SiCP)或其類似者生長。在用磊晶源極/汲極區48填充凹槽42之後，磊晶源極/汲極區48的進一步磊晶生長使得磊晶源極/汲極區48水平擴展，且可形成小面。磊晶源極/汲極區48的進一步生長亦可使得相鄰磊晶源極/汲極區48彼此合併。可產生空隙(氣隙)49(第10A圖)。
在磊晶製程之後，磊晶源極/汲極區區48可進一步植入p型或n型雜質以形成源極及汲極區，此些源極及汲極區亦使用元件符號48表示。根據本揭示案的替代實施 例，當磊晶源極/汲極區48在磊晶期間原位摻雜p型或n型雜質時，跳過植入製程，且磊晶源極/汲極區48亦為源極/汲極區。
第11A、11B及11C圖至第18A、18B及18C圖中的後續圖式符號可具有後接字母A、B或C的相應數字。圖式符號帶有字母A的圖表示對應的圖顯示的參考橫截面與第4圖中的參考橫截面A2-A2相同，圖式符號帶有字母B的圖表示對應的圖顯示的參考橫截面與第4圖中的參考橫截面B-B相同，且圖式符號帶有字母C的圖表示對應的圖顯示的參考橫截面與第4圖中的參考橫截面A1-A1相同。
第11A、11B及11C圖示出在形成接觸蝕刻停止層(Contact Etch Stop Layer,CESL)50及層間介電質(Inter-Layer Dielectric,ILD)52之後的結構的橫截面圖。各別製程在第24圖所示的製程流程200中示出為製程222。CESL 50可由氧化矽、氮化矽、碳氮化矽或其類似者形成，且可使用CVD、ALD或其類似者形成。ILD 52可包括使用例如FCVD、旋塗、CVD或任何其他適合的沉積方法形成的介電材料。ILD 52可由含氧介電材料形成，此介電材料可為使用作為前驅物的四乙基原矽酸鹽(Tetra Ethyl Ortho Silicate,TEOS)、磷矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass, BPSG)、未摻雜矽酸鹽玻璃(Undoped Silicate Glass,USG)或其類似者形成的氧化矽基材料。
第12A及12B圖至第16A及16B圖示出用於形成替代閘極堆疊的製程。在第12A及12B圖中，進行諸如CMP製程或機械研磨製程的平坦化製程以平整ILD 52的頂表面。各別製程在第24圖所示的製程流程200中示出為製程224。根據一些實施例，平坦化製程可移除硬遮罩36以暴露虛設閘電極34，如第12A圖所示。根據替代實施例，平坦化製程可暴露硬遮罩36且停止於硬遮罩36上。根據一些實施例，在平坦化製程之後，虛設閘電極34(或硬遮罩36)、閘極間隔墊38及ILD 52的頂表面在製程波動內為齊平的。
接著，在一或多個蝕刻製程中移除虛設閘電極34(及硬遮罩36，若剩餘)，從而形成凹槽58，如第13A及13B圖所示。各別製程在第24圖所示的製程流程200中示出為製程226。亦移除凹槽58中之虛設閘極介電質32的部分。根據一些實施例，經由各向異性乾式蝕刻製程移除虛設閘電極34及虛設閘極介電質32。例如，可使用以比ILD 52更快的速率選擇性地蝕刻虛設閘電極34的反應氣體來進行蝕刻製程。各凹槽58暴露及/或覆蓋多層堆疊22’的部分，此些部分包括後續完成的奈米FET中的未來通道區。多層堆疊22’的部分位於磊晶源極/汲極區48的相鄰對之間。
隨後移除犧牲層22A以在奈米結構22B之間延伸 凹槽58，且所得結構示於第14A及14B圖中。各別製程在第24圖所示的製程流程200中示出為製程228。可藉由使用對犧牲層22A的材料具有選擇性的蝕刻劑進行諸如濕式蝕刻製程的各向同性蝕刻製程來移除犧牲層22A，而與犧牲層22A相比，奈米結構22B、基板20、STI區26保持相對未蝕刻。根據其中犧牲層22A包括例如SiGe且奈米結構22B包括例如Si或SiC的一些實施例，四甲基氫氧化銨(tetra methyl ammonium hydroxide,TMAH)、氫氧化銨(NH4OH)或其類似者可用於移除犧牲層22A。
參考第15A及15B圖，形成閘極介電質62。各別製程在第24圖所示的製程流程200中示出為製程230。根據一些實施例，每一閘極介電質62包括界面層及界面層上的高k介電層。界面層可由氧化矽形成或包含氧化矽，其可經由諸如ALD或CVD的共形沉積製程來沉積。根據一些實施例，高k介電層包含一或多個介電層。例如，高k介電層可包括鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛及其組合的金屬氧化物或矽酸鹽。
參考第16A及16B圖，形成閘電極68。在形成中，首先在高k介電層上形成導電層，且填充凹槽58的剩餘部分。各別製程在第24圖所示的製程流程200中示出為製程232。閘電極68可包括含金屬材料，諸如TiN、TaN、TiAl、TiAlC、鈷、釕、鋁、鎢、其組合及/或其多層。例如，儘管在第16A及16B圖中示出單層閘電極 68，但閘電極68可包括任意數量的層、任意數量的功函數層及可能的填充材料。閘極介電質62及閘電極68亦填充相鄰奈米結構22B之間的空間，且填充底部奈米結構22B及下層基板條20'之間的空間。在填充凹槽58之後，進行諸如CMP製程或機械研磨製程的平坦化製程以移除閘極介電質及閘電極68之材料的過剩部分，此些過剩部分位於ILD 52的頂表面上。閘電極68及閘極介電質62統稱為所得奈米FET的閘極堆疊70。
在第17A、17B及17C圖所示的製程中，使閘極堆疊70凹陷，從而直接在閘極堆疊70上及閘極間隔墊38的相對部分之間形成凹槽。包含諸如氮化矽、氧氮化矽或其類似者之一或多層介電材料的閘極遮罩74填充在每一凹槽中，隨後進行平坦化製程以移除在ILD 52上延伸之介電材料的過剩部分。各別製程在第24圖所示的製程流程200中示出為製程234。
如第17A、17B及17C圖進一步說明，ILD 76沉積在ILD 52上及閘極遮罩74上。各別製程在第24圖所示的製程流程200中示出為製程236。在形成ILD 76之前，可沉積或可不沉積蝕刻停止層(未示出)。根據一些實施例，ILD 76經由FCVD、CVD、PECVD或其類似者形成。ILD 76由介電材料形成，此介電材料可選自氧化矽、PSG、BSG、BPSG、USG或其類似者。
在第18A、18B及18C圖中，ILD 76、ILD 52、CESL 50及閘極遮罩74經蝕刻以形成暴露磊晶源極/汲 極區48及/或閘極堆疊70之表面的凹槽(由接觸插塞80A及80B佔據)。可經由使用諸如RIE、NBE或其類似者的各向異性蝕刻製程進行蝕刻來形成凹槽。根據一些實施例，可經由使用第一蝕刻製程蝕刻穿透ILD 76及ILD 52、使用第二蝕刻製程蝕刻穿透閘極遮罩74以及可能使用第三蝕刻製程蝕刻穿透CESL 50來形成凹槽。儘管第18B圖示出接觸插塞80A及80B處於相同的橫截面中，但在各個實施例中，接觸插塞80A及80B可形成在不同的橫截面中，從而降低彼此短路的風險。
在形成凹槽之後，在磊晶源極/汲極區48上形成矽化物區78(第18B及18C圖)。各別製程在第24圖所示的製程流程200中示出為製程238。根據一些實施例，經由首先沉積能夠與下層磊晶源極/汲極區48的半導體材料(例如，矽、矽鍺、鍺)反應的金屬層(未示出)以形成矽化物及/或鍺化物區，隨後進行熱退火製程以形成矽化物區78來形成矽化物區78。金屬可包括鎳、鈷、鈦、鉭、鉑、鎢或其類似者。隨後例如由蝕刻製程移除沉積金屬的未反應部分。
隨後在矽化物區78上形成接觸插塞80B。此外，接觸插塞80A(亦可稱為閘極接觸插塞)亦形成於凹槽中，且位於閘電極68上且接觸閘電極68。各別製程在第24圖所示的製程流程200中示出為製程240。接觸插塞80A及80B可各包含一或多層，諸如阻障層、擴散層及填充材料。例如，根據一些實施例，接觸插塞80A及80B各包 括阻障層及導電材料，且電耦合至下層導電特徵(例如，所示實施例中的閘極堆疊70或矽化物區78)。阻障層可包括鈦、氮化鈦、鉭、氮化鉭或其類似者。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳或其類似者。可進行諸如CMP製程的平坦化製程以自ILD 76的表面移除過剩材料。由此形成奈米FET 82。
藉由採用本揭示案的製程形成諸如內間隔墊或閘極間隔墊的介電薄膜，介電薄膜雖然具有降低的k值，但仍具有期望的抗蝕刻性。第22及23圖示出隨k值變化之介電薄膜的蝕刻速率。第22圖示出在如第9B圖所示之製程中的間隔墊修整及預清洗製程期間間隔層43(第8B圖)的蝕刻速率。線150示出使用習知沉積製程形成之介電材料(諸如SiOCN、SiON、SiOC、SiCN)的蝕刻速率。線152示出採用本揭示案製程形成之介電材料的蝕刻速率。觀察到，比較由具有相同蝕刻速率的線150及152表示的介電材料，由線152表示的k值具有比線150的k值顯著更低的k值。換言之，當形成具有相同k值的兩種材料時，其中一種使用習知沉積製程形成，而另一種使用本揭示案製程形成，使用本揭示案製程形成的材料具有顯著更低的蝕刻速率，這指示更高的抗蝕刻性。需注意，由於製程時間可能會延長，因此降低的蝕刻速率不會損害間隔墊修整製程。
第23圖示出在如第14B圖所示的製程中移除犧牲層22A期間間隔層43(第8B圖)的蝕刻速率。線160 示出使用習知沉積製程形成之介電材料(諸如SiOCN、SiON、SiOC、SiCN)的蝕刻速率。線162示出採用本揭示案製程形成之介電材料的蝕刻速率。觀察到，比較由具有相同蝕刻速率的線160及162表示的介電材料，由線162表示的k值具有比線160的k值顯著更低的k值。第23圖亦揭示根據本揭示案的實施例形成的介電薄膜具有較低的k值及較高的抗蝕刻性。在對樣品矽晶圓進行的一些實驗中，具有使用習知沉積製程形成之間隔層43的樣品在移除犧牲層22A期間具有18.8Å的損失。作為比較，根據本揭示案的實施例形成的三個樣品具有8.4Å至約14.7Å範圍內的損失，均顯著小於習知材料的損失。
本揭示案的實施例具有一些有利特徵。藉由採用本揭示案實施例的前驅物及薄膜成熟製程來形成介電薄膜，減少了介電薄膜的k值，且提高了其抗蝕刻性。
根據本揭示案的一些實施例，一種方法包含進行ALD製程以在晶圓上形成介電層，此ALD製程包含ALD循環，此ALD循環包含脈衝輸送calypso((SiCl3)2CH2)；清除此calypso；脈衝輸送氨氣；以及清除此氨氣；對此介電層進行濕式退火製程；以及對此介電層進行乾式退火製程。在一實施例中，此方法進一步包含重複ALD循環以增加介電層的厚度。在一實施例中，此方法進一步包含形成包含複數個半導體奈米結構以及複數個犧牲層的疊層，其中此些半導體奈米結構與此些犧牲層交替安置；使此些犧牲層橫向凹陷以形成橫向凹槽，其中 介電層延伸至此些橫向凹槽中；以及修整此介電層以移除此些凹槽外之此介電層的部分。在一實施例中，此方法進一步包含在修整之後，移除複數個犧牲層；以及形成延伸至此些犧牲層留下之空間中的閘極堆疊。在一實施例中，介電層在電晶體的閘極堆疊上形成，且此方法進一步包含進行各向異性蝕刻製程以由此介電層形成閘極間隔墊。在一實施例中，使用水蒸汽來進行濕式退火製程。在一實施例中，濕式退火製程在第一溫度下進行，而乾式退火製程在高於第一溫度的第二溫度下進行。在一實施例中，濕式退火製程在約300℃與約500℃之間的範圍內的第一溫度下進行，且乾式退火製程在約400℃與約600℃之間的範圍內的第二溫度下進行。在一實施例中，使用氮氣(N2)作為製程氣體來進行乾式退火製程。
根據本揭示案的一些實施例，一種方法包含形成包含第一矽層及第二矽層的疊層；以及此第一矽層與此第二矽層之間的矽鍺層；使此矽鍺層橫向凹陷以形成橫向凹槽；沉積介電層，其中此介電層延伸至此橫向凹槽中；使此介電層退火以降低此介電層的k值；修整此介電層以移除此些橫向凹槽外之此介電層的第一部分，而此些凹槽內之此介電層的第二部分保留為內間隔墊；移除此矽鍺層；以及形成延伸至此第一矽層與此第二矽層之間的間隔墊中的閘極堆疊。在一實施例中，介電層經由原子層沉積製程沉積，將calypso((SiCl3)2CH2)及氨氣用作前驅物。在一實施例中，此方法進一步包含在沉積介電層之後，對此介電 層進行濕式退火製程及乾式退火製程。在一實施例中，在對介電層進行濕式退火製程及乾式退火製程之後，對此介電層進行修整。在一實施例中，在對介電層進行濕式退火製程及乾式退火製程之前，對此介電層進行修整。在一實施例中，濕式退火製程在第一溫度下進行，而乾式退火製程在高於第一溫度的第二溫度下進行。
根據本揭示案的一些實施例，一種方法包含形成包含複數個半導體奈米結構以及複數個犧牲層的疊層，其中此些半導體奈米結構與此些犧牲層交替安置；使此些犧牲層橫向凹陷以形成橫向凹槽；以及沉積延伸至此些橫向凹槽中的介電層，其中使用calypso((SiCl3)2CH2)及氨氣作為前驅物來沉積此介電層。在一實施例中，此方法進一步包含使介電層退火。在一實施例中，退火包含濕式退火製程及乾式退火製程。在一實施例中，使用原子層沉積來沉積介電層。在一實施例中，此方法進一步包含移除複數個犧牲層；以及形成延伸至半導體奈米結構之間的間隔墊中的閘極堆疊。
前文概述了若干實施例的特徵，以便熟習此項技術者可更好地理解本揭示案的態樣。熟習此項技術者應當理解，其可容易地使用本揭示案作為設計或修改其他製程及結構的基礎，以實現與本文介紹的實施例相同的目的及/或達成與本文介紹的實施例相同的優點。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭示案的精神及範疇，且在不脫離本揭示案的精神及範疇的情況下，其可在本文 中進行各種變化、替換及變更。
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Claims (10)

  1. 一種形成電晶體的方法，包含：進行一原子層沉積(atomic layer deposition,ALD)製程以在一晶圓上形成一介電層，該ALD製程包含一ALD循環，該ALD循環包含：脈衝輸送(SiCl3)2CH2；清除該(SiCl3)2CH2；脈衝輸送氨氣；以及清除該氨氣；對該介電層進行一濕式退火製程；以及對該介電層進行一乾式退火製程。
  2. 如請求項1所述之方法，進一步包含：形成一疊層，該疊層包含：複數個半導體奈米結構；以及複數個犧牲層，其中該些半導體奈米結構與該些犧牲層交替安置；使該些犧牲層橫向凹陷以形成橫向凹槽，其中該介電層延伸至該些橫向凹槽中；以及修整該介電層以移除該些凹槽外之該介電層的部分。
  3. 如請求項2所述之方法，進一步包含：在該修整之後，移除該些犧牲層；以及形成延伸至該些犧牲層留下之空間中的一閘極堆疊。
  4. 如請求項1所述之方法，其中該介電層在一電晶體的一閘極堆疊上形成，且該方法進一步包含進行一各向異性蝕刻製程以由該介電層形成一閘極間隔墊。
  5. 如請求項1所述之方法，其中該濕式退火製程在一第一溫度下進行，且該乾式退火製程在高於該第一溫度的一第二溫度下進行。
  6. 一種形成電晶體的方法，包含：形成一疊層，該疊層包含：一第一矽層及一第二矽層；以及該第一矽層與該第二矽層之間的一矽鍺層；使該矽鍺層橫向凹陷以形成一橫向凹槽；將(SiCl3)2CH2及氨氣用作前驅物，經由一原子層沉積製程沉積一介電層，其中該介電層延伸至該橫向凹槽中；使該介電層退火以降低該介電層的k值；修整該介電層以移除該些橫向凹槽外之該介電層的第一部分，而該些凹槽內之該介電層的第二部分保留為內間隔墊；移除該矽鍺層；以及形成延伸至該第一矽層與該第二矽層之間的間隔墊中的一閘極堆疊。
  7. 如請求項6所述之方法，進一步包含在沉積該介電層之後，對該介電層進行一濕式退火製程及一乾式退火製程。
  8. 如請求項7所述之方法，其中該濕式退火製程在一第一溫度下進行，且該乾式退火製程在高於該第一溫度的一第二溫度下進行。
  9. 一種形成電晶體的方法，包含：形成一疊層，該疊層包含：複數個半導體奈米結構；以及複數個犧牲層，其中該些半導體奈米結構與該些犧牲層交替安置；使該些犧牲層橫向凹陷以形成橫向凹槽；以及沉積延伸至該些橫向凹槽中的一介電層，其中使用(SiCl3)2CH2及氨氣作為前驅物來沉積該介電層。
  10. 如請求項9所述之方法，進一步包含使該介電層退火。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190267463A1 (en) * 2018-02-28 2019-08-29 International Business Machines Corporation Low-k dielectric inner spacer for gate all around transistors
US20190280088A1 (en) * 2018-03-07 2019-09-12 International Business Machines Corporation Low contact resistance nanowire fets
TW202002028A (zh) * 2018-06-15 2020-01-01 台灣積體電路製造股份有限公司 半導體裝置的形成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687409B2 (en) * 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US9184089B2 (en) * 2013-10-04 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanism of forming a trench structure
US10037912B2 (en) * 2016-12-14 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US10249730B1 (en) * 2017-12-11 2019-04-02 International Business Machines Corporation Controlling gate profile by inter-layer dielectric (ILD) nanolaminates
US10453824B1 (en) * 2018-05-08 2019-10-22 International Business Machines Corporation Structure and method to form nanosheet devices with bottom isolation
US10692773B2 (en) * 2018-06-29 2020-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Forming nitrogen-containing low-K gate spacer
CN111211088B (zh) * 2018-11-21 2023-04-25 台湾积体电路制造股份有限公司 半导体器件及其形成方法
EP3711091A4 (en) * 2018-12-17 2021-11-24 SanDisk Technologies LLC THREE-DIMENSIONAL STORAGE DEVICE WITH TENSIONED VERTICAL SEMICONDUCTOR CHANNELS AND PROCESS FOR THEIR PRODUCTION

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190267463A1 (en) * 2018-02-28 2019-08-29 International Business Machines Corporation Low-k dielectric inner spacer for gate all around transistors
US20190280088A1 (en) * 2018-03-07 2019-09-12 International Business Machines Corporation Low contact resistance nanowire fets
TW202002028A (zh) * 2018-06-15 2020-01-01 台灣積體電路製造股份有限公司 半導體裝置的形成方法

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