TWI772188B - Perforation forming method of a multilayer circuit board, manufacturing method of a multilayer circuit board, multilayer circuit board and multilayer circuit board manufacturing system - Google Patents

Abstract

The invention discloses a perforation forming method of a multilayer circuit board, a manufacturing method of a multilayer circuit board, a multilayer circuit board and a multilayer circuit board manufacturing system. The perforation forming method of a multilayer circuit board includes: preparation step: preparing a core board set, which includes a plurality of core boards, each core board has a marking unit, and each marking unit does not overlap each other in the longitudinal direction; scanning step: scanning the core board set to obtain the coordinates of each marking unit; calculation step: use the coordinates to calculate the deformation amount of each core board; forming step: form at least one through hole in the core board set according to each deformation amount and the perforation position information of the circuit board , so that the core board set is composed of a multi-layer circuit board.

Description

Multilayer circuit board perforation forming method, multilayer circuit board manufacturing method, multilayer circuit board and multilayer circuit board manufacturing system

The invention relates to a perforation forming method for a circuit board, a circuit board manufacturing method, a circuit board and a circuit board manufacturing system, in particular to a perforation forming method for a multi-layer circuit board, a multi-layer circuit board manufacturing method, a multi-layer circuit board and a multi-layer circuit board manufacturing system .

The existing common multi-layer circuit boards are formed by pressing multiple chips to each other, and there are related circuits that are electrically connected to each other between the core boards, and the multi-layer circuit boards usually have at least one plated through hole (Plated Through Hole). , PTH) or commonly known as vias. The forming method of the plated through hole or the commonly known via hole is as follows: forming a through hole in the multilayer circuit board, and then electroplating a conductive layer in the through hole.

As shown in FIG. 1 , as the wire diameters of the lines on each core board become smaller, the diameters of the through-holes also decrease. Therefore, using the related manufacturing process of the existing multilayer circuit board P, it is easy to cause the through-holes H to exceed the The core board is pre-configured with the allowable error range R of the through-holes (commonly known as deflection in the industry), which may lead to the damage of the lines in the core board, etc., thereby leading to the problem of lowering the manufacturing yield of the multilayer circuit board.

The invention discloses a perforation forming method for a multi-layer circuit board, a method for manufacturing the multi-layer circuit board, a multi-layer circuit board and a multi-layer circuit board manufacturing system, which are mainly used to improve the conventional multi-layer circuit board manufacturing method. The problem of setting position, which leads to the problem of lowering the manufacturing yield of the multilayer circuit board.

One embodiment of the present invention discloses a perforation forming method for a multi-layer circuit board, which includes: a preparation step: preparing a multi-layer core board group. The two core boards on the opposite sides of the core board group are defined as the first core board, the remaining core boards are defined as the second core board, at least one second core board has at least three marking units, and any marking unit is in a longitudinal direction. The direction does not completely overlap with any marking unit, and the longitudinal direction is parallel to a normal line of a surface of the first core board; a scanning step: use a scanning device to scan the multi-layer core board group to obtain a mark of each marking unit. Coordinates; a calculation step: using a processing device to calculate a deformation amount of the second core board with the marking unit according to the coordinates corresponding to each marking unit and a preset circuit board size information; a forming step: controlling a perforation forming The equipment forms at least one through hole in the multilayer core board group according to a deformation amount of each first core board, a deformation amount of each second core board with marking unit and a circuit board perforation position information, and the through hole penetrates through each first core board board and each second core board, so that the multi-layer core board is composed into a multi-layer circuit board.

One embodiment of the present invention discloses a method for manufacturing a multilayer circuit board, which includes: a core board marking step: forming at least three marking units on at least one wide side of a plurality of core boards; a combining step: placing a plurality of core boards They are fixed to each other to form a multi-layer core board group, and any marking unit of the multi-layer core board group does not completely overlap with any marking unit in a longitudinal direction, and the longitudinal direction is parallel to a normal line of a surface of the core board; a Scanning step: using a scanning device to scan the multi-layer core board group to obtain the coordinates of each marking unit; a calculating step: using a processing device according to the coordinates corresponding to each marking unit of each core board and a preset circuit board Dimension information to calculate a deformation amount of each core board; a forming step: control a perforation forming equipment, according to the deformation amount and a circuit board perforation position information, form at least one consistent perforation in the multi-layer core board group, and the through hole penetrates each core board ; A conductive layer forming step: forming a conductive layer in at least one through hole, so that the multi-layer core board is formed into a multi-layer circuit board.

One of the embodiments of the present invention discloses a multilayer circuit board, which is manufactured by the method for manufacturing a multilayer circuit board of the present invention.

One embodiment of the present invention discloses a multi-layer circuit board manufacturing system, which includes a processing device, a scanning device, and a perforation forming apparatus, and the processing device can execute the multi-layer circuit board manufacturing method of the present invention.

To sum up, the perforation forming method of the multilayer circuit board, the method for manufacturing the multilayer circuit board, the multilayer circuit board and the manufacturing system for the multilayer circuit board of the present invention can be greatly reduced by the design of the marking unit, etc. The probability of occurrence of position problems can be effectively improved, and the manufacturing yield of multilayer circuit boards can be effectively improved.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention, but these descriptions and drawings are only used to illustrate the present invention, rather than make any claims to the protection scope of the present invention. limit.

In the following description, if it is indicated to refer to a specific figure or as shown in a specific figure, it is only used for emphasis in the subsequent description, and most of the related content mentioned appears in the specific figure, However, it is not limited that only the specific drawings may be referred to in this subsequent description.

Please refer to FIG. 2 to FIG. 5 together. FIG. 2 is a schematic flow chart of a method for punching a multilayer circuit board according to the present invention. FIG. 3 is a schematic diagram of a multilayer circuit board according to the method for punching a multilayer circuit board according to the present invention. An exploded schematic view of the multilayer circuit board of the perforation forming method of the multilayer circuit board of the present invention, and FIG. 5 is an image obtained after the scanning device scans the multilayer circuit board of the present invention.

The perforation forming method of the multilayer circuit board of the present invention comprises the following steps:

A preparation step S11: prepare a multi-layer core board group, the multi-layer core board group is composed of a plurality of core boards arranged on top of each other, and the two core boards located on the opposite sides of the multi-layer core board group are defined as the first core board , the rest of the core boards are defined as the second core board, and at least a part of the second core board has at least three marking units, and any marking unit in a longitudinal direction (for example, the Z-axis direction in FIG. 3 ) is not associated with any marking unit Completely overlapping, the longitudinal direction is parallel to a normal line of a surface of the first core board (for example, the wide side 11A of the first core board 11 );

A scanning step S12: use a scanning device (such as an X-ray scanning device) to scan the multi-layer core board group to obtain the coordinates of each marking unit;

A calculation step S13: using a processing device to calculate a deformation amount of the second core board with the marking units according to the coordinates corresponding to the marking units and a predetermined circuit board size information; and

A forming step S14 : controlling a perforation forming equipment (such as a laser perforating equipment), according to the deformation amount of a first core board, the deformation amount of the second core board and a circuit board perforation position information, to form a multi-layer core board group Perforated at least consistently. Wherein, the through holes are arranged through each of the first core boards and each of the second core boards.

As shown in FIG. 3 and FIG. 4 , it is shown as the multi-layer core board group 100 described in the preparation step S11 . For example, the multi-layer core board group 100 may include four core boards, two of which are defined as two first core boards 11 and 12 , and the other two core boards are defined as two second core boards 13 and 14 . The two second core boards 13 and 14 are located between the two first core boards 11 and 12 , and the dimensions of the respective core boards are approximately the same. It should be noted that, this is only for illustrative purposes, and the multi-layer core board group 100 includes only 4 core boards as an example. That is, the number of the second core plates included in the multi-layer core plate group 100 may be more than two layers. The manner in which the plurality of core boards included in the multi-layer core board group 100 are fixed to each other is not limited here.

One of the wide side surfaces 11A and 12A of each of the first core boards 11 and 12 may have a circuit area A1 and a non-circuit area A2. At least one circuit may be formed on the circuit area A1. The circuit is commonly known as PCB layout. One of the wide sides 13A and 14A of each of the second core boards 13 and 14 may have a circuit area A1 and a non-circuit area A2, and at least one circuit is formed on the circuit area A1, and the circuit is commonly known as a PCB. layout.

In one specific embodiment, one of the second core boards 13 may be provided with four marking units 131, 132, 133, 134 in the non-circuit area A2, and the four marking units 131, 132, 133, 134 may be Roughly arranged at the four corners of a virtual rectangle B1, the other second core board 14 may be provided with four marking units 141, 142, 143, 144 in the non-circuit area A2, and the four marking units 141, 142, 143 and 144 may be approximately disposed at four corners of a virtual rectangle B2. In practical applications, the shape of the virtual rectangle B1 is a proportional reduction of the shape of the second core board 13 , and the shape of the virtual rectangle B2 is a proportional reduction of the shape of the second core board 14 .

The marking units 131 , 132 , 133 , and 134 may be structures formed on the surface of the second core board 13 , and the marking units 131 , 132 , 133 , and 134 may be structures that do not penetrate the second core board 13 . The marking units 141 , 142 , 143 , and 144 may be structures formed on the surface of the second core board 14 , and the marking units 141 , 142 , 143 , and 144 may be structures that do not penetrate the second core board 14 . Of course, in special applications, each marking unit may also be a perforation penetrating through the second core board. In addition, each second core board may include three or five or more marking units. The specific shape and size of the marking unit can be changed according to requirements, and the figure shown in the figure is only an exemplary aspect.

It is worth mentioning that in FIG. 4 , four marking units 131 , 132 , 133 , 134 of one of the second core boards 13 are arranged on the wide side 13A of the second core board 13 facing the first core board 11 . The four marking units 141 , 142 , 143 and 144 of the other second core board 14 are arranged on the wide side 14A facing the other second core board 13 as an example, but each of the second core boards 13 and 14 includes The four marking units 131 , 132 , 133 , 134 , 141 , 142 , 143 and 144 may also be arranged on different broad sides.

As shown in FIG. 4 , the shapes of the two virtual rectangles B1 and B2 are reduced by the shapes of the second core boards 13 and 14 in different proportions, and the sizes of the two virtual rectangles B1 and B2 are different. In this way, As shown in FIG. 5 , in the image obtained after the scanning device scans the multilayer core board group 100 , the marking units 131 , 132 , 133 , 134 , 141 , 142 , 143 , and 144 belong to different second core boards 13 and 14 respectively They are arranged without overlapping each other, that is, in the image obtained after the scanning device scans the multi-layer core board group 100 , the marking units are arranged in a staggered manner from each other.

According to the above, as shown in FIG. 5 , in the image obtained after the scanning device scans the multilayer core board 100 , the two marking units 131 and 132 of the second core board 13 and the two marking units 132 of the second core board 14 are The two marking units 141, 142 may be located on the same virtual axis C1, and the other two marking units 133, 134 of the second core board 13 and the other two marking units 143, 143 of the second core board 14 may be located on different On a virtual axis C2, the marking units 131, 132, 141, 142 do not overlap each other on the virtual axis C1, and the marking units 133, 134, 143, 144 do not overlap each other on the virtual axis C2.

The scanning device is not limited to the X-ray scanning device, any scanning device with penetrating light belongs to the applicable scope of the scanning device mentioned herein, or any scanning device that can be used to scan the multi-layer core board assembly 100 to The scanning device for taking the coordinates of each marking unit also belongs to the applicable scope of the scanning device referred to in the present invention.

As shown in FIG. 5 , after the scanning step S12, the scanning device will The coordinates corresponding to each of the marking units 131, 132, 133, 134, 141, 142, 143, and 144 can be obtained, and in the calculation step S13, the processing device can utilize the same second core board 13 (14 ) of the four marking units 131, 132, 133, 134 (141, 142, 143, 144) to calculate the current size of the second core board 13 (14), and then the processing device can use the current size and a current size A preset size of each second core board 13 (14) included in the preset circuit board size information is compared and calculated, whereby the processing device can calculate the size of each second core board 13 (14). The amount of deformation (for example, the amount of expansion and contraction).

In the forming step S14, the deformation amount (ie, the expansion and contraction value) of each first core plate can be obtained in various ways. camera), respectively capture the images of the two first core boards to obtain two captured images, and then use the two captured images and the pre-stored images of the standard first core board (or the images of the first core board). The predetermined size data) are compared, whereby the processing device can calculate the deformation amount of each first core board.

In one specific embodiment, in the preparation step S11, one of the wide side surfaces 11A of one of the first core boards 11 may have four auxiliary marking units 111, 112, 113, 114, and four auxiliary marking units 111, 112, 113, 114 are arranged at the four corners of a virtual rectangle B3; one of the wide side surfaces 12A of the other first core board 12 may have four auxiliary marking units 121, 122, 123, 124, four Auxiliary marking units 121, 122, 123, 124 are arranged at four corners of a virtual rectangle B4; (Z-axis direction as shown in FIG. 3), does not completely overlap with any auxiliary marking unit or marking unit. The shape of the virtual rectangle B3 is proportionally reduced from the shape of the first core board 11 , the shape of the virtual rectangle B4 is proportionally reduced from the shape of the first core board 12 , and the virtual rectangle B3 and the size of the virtual rectangle B4 are different.

As shown in FIG. 5 , in the image obtained after the scanning device scans the multilayer core assembly 100 , the auxiliary marking units 111 , 112 , 121 , 122 and the marking units 131 , 132 , 141 , 142 may be located on the same axis C1 , and The auxiliary marking units 113, 114, 123, 124 and the marking units 133, 134, 143, 144 may be located on the same axis C2.

In the case where each of the first core boards 11 and 12 is provided with auxiliary marking units, in the scanning step S12, the scanning device can obtain the coordinates of each auxiliary marking unit, and in the calculation step, the processing device can also be based on The coordinates corresponding to each auxiliary marking unit are used to calculate the current size of each first core board 11 and 12, and the processing device can use the current size of each first core board and each first core board contained in the preset circuit board size information. A preset size of the core plates 11 and 12 is compared and calculated, whereby the processing device can calculate the deformation amount (for example, the expansion and contraction amount) of each of the first core plates 11 and 12 .

According to the above, through the design of arranging four marking units on each second core board, the processing device will be able to calculate the expansion and shrinkage value of each second core board in the calculation step S13, and thus, the processing device executes the forming step S14 At this time, according to the deformation amount of each first core board and the deformation amount of each second core board (that is, the expansion and contraction value), it can be determined whether to modify at least one predetermined perforation position coordinate included in the perforation position information of the circuit board. , it will be ensured that the through holes formed on the multi-layer core board group 100 will not exceed the allowable error range of the first core board or any second core board.

To sum up, the perforation forming method of the multilayer circuit board of the present invention can be effectively improved, and the conventional manufacturing method of the multilayer circuit board is prone to the problem that the through hole deviates from the tolerance range of at least one of the core boards.

It should be noted that, in practical applications, the relevant personnel may only form marking units or auxiliary marking units on the core boards that are prone to deformation according to the characteristics of each core board. One of the core boards is provided with marking units or auxiliary marking units, and the multilayer circuit board may be that only part of the second core board is provided with marking units, and the remaining core boards are not provided with marking units or auxiliary marking units.

In addition, in this embodiment, it is taken as an example that a single wide side face of each core board is provided with a marking unit or an auxiliary marking unit, but in different embodiments, each core board may also be provided with two wide sides respectively. There is a marking unit or an auxiliary marking unit, so that the processing device can use all the marking units on the same core board to calculate the mutual deformation of the two wide sides of the core board (ie the layer deviation commonly known in the industry).

Please refer to FIG. 6 and FIG. 7 together. FIG. 6 is a schematic flowchart of the method for manufacturing a multilayer circuit board of the present invention, and FIG. 7 is a multilayer circuit board manufactured by the method for manufacturing a multilayer circuit board of the present invention. The multi-layer circuit board manufacturing method of the present invention comprises the following steps:

A core board marking step S21 : forming at least three marking units on at least one wide side of a plurality of core boards (ie each of the aforementioned first core boards and each of the second core boards);

A combining step S22: fixing a plurality of core boards to each other to form a multi-layer core board group 100 (as shown in FIG. 3), any marking unit of the multi-layer core board group (ie the aforementioned marking unit and auxiliary marking unit) In a longitudinal direction (eg, the Z-axis direction shown in FIG. 3 ), it does not completely overlap with any marking unit, and the longitudinal direction corresponds to a surface of the multilayer core board group (eg, the wide side 11A of the first core board 11). normals are parallel to each other;

A scanning step S23: using a scanning device to scan the multi-layer core board group to obtain the coordinates of each marking unit;

A calculation step S24: using a processing device to calculate a deformation amount of each core board according to the coordinates corresponding to each marking unit of each core board and a predetermined circuit board size information; and

A forming step S25 : controlling a perforation forming device, according to the deformation amount and a circuit board perforation position information, to form at least one through hole in the multi-layer core board group, and the through hole penetrates each core board;

A conductive layer forming step S26 : forming a conductive layer in at least one of the through holes, so that the multi-layer core board is formed into a multi-layer circuit board 200 .

As shown in FIG. 3 , in the core board marking step S21 , four auxiliary marking units 111 , 112 , 113 , 114 , 121 , 122 are respectively formed on the wide sides 11A and 12A of the first core boards 11 and 12 . , 123 , 124 , and four marking units 131 , 132 , 133 , 134 , 141 , 142 , 143 , and 144 are formed on the wide side surfaces 13A and 14A of the second core boards 13 and 14 , respectively.

In the combining step S22, a plurality of core boards may be fixed to each other by means of bonding or the like according to requirements. Contents such as the longitudinal direction described in the combining step S22 are the same as those described in the foregoing embodiments, and are not repeated here. The scanning step S23 , the calculating step S24 and the forming step S25 in this embodiment are the same as the scanning step S12 , the calculating step S13 and the forming step S14 in the previous embodiment, and will not be repeated here.

The conductive layer forming step S26 may be, for example, by using electroplating technology to form the conductive layer 202 in the through holes, thereby making at least one through hole 201 a Plated Through Hole (PTH) or commonly known as conduction Vias, the material of the conductive layer 202 can be, for example, copper, but not limited thereto, and after the conductive layer forming step S26, the through-holes 201 without the conductive layer 202 are formed into electroless through-holes (Non Plating Through Hole, NPTH).

The above-mentioned method for manufacturing a multilayer circuit board of the present invention is only described with respect to the biggest difference between the present invention and the conventional method for manufacturing a multilayer circuit board. In practical applications, the method for manufacturing a multilayer circuit board of the present invention may also be: Other different process steps can be added according to requirements. For example, after the conductive layer forming step S26, an automatic optical inspection (AOI) step can also be added, so that automatic optical inspection equipment can be used to perform inspection on the multilayer circuit board. Inspection; between the combining step S22 and the scanning step S23, a blackening step or a browning step can also be added, so as to use a blackening device or a browning device to remove impurities on the surface of the circuit board, after the conductive layer forming step S26 , an exposure step can also be added to form blind holes on the surface of the multilayer circuit board by using exposure equipment, and an automatic optical inspection step can also be added after the exposure step.

Please refer to FIG. 8 , which is a schematic block diagram of the multilayer circuit board manufacturing system of the present invention. The multi-layer circuit board manufacturing system 300 of the present invention includes a processing device 301 , a scanning device 302 and a through-hole forming device 303 . The processing device 301 is electrically connected to the scanning device 302 and the perforation forming equipment 303 , and the processing device 301 can execute the above-mentioned method for manufacturing a multilayer circuit board of the present invention to manufacture the multilayer circuit board 200 (as shown in FIG. 7 ). For the detailed description of the scanning device 302 and the perforation forming apparatus 303, please refer to the foregoing description, and details are not repeated here. In practical applications, the multi-layer circuit board manufacturing system 300 may also include blackening/browning equipment, exposure equipment, automatic optical inspection equipment, and the like according to requirements.

To sum up, the perforation forming method for a multilayer circuit board, the method for manufacturing a multilayer circuit board, the manufacturing system for a multilayer circuit board, and the multilayer circuit board of the present invention can make the through holes formed in the multilayer circuit board through the design of a plurality of marking units and the like. , it is not easy to occur that the through hole is not located within the allowable error range of the position where the through hole is originally intended to be provided in the core board (ie, the problem of commonly known as deflection), so that the production yield of the multilayer circuit board can be improved.

In addition, the marking unit or the auxiliary marking unit can be formed together with the related equipment when the circuit is formed on the core board, therefore, the manufacturing complexity of the multi-layer circuit board will not be increased.

The above descriptions are only preferred feasible embodiments of the present invention, which do not limit the scope of the present invention. Therefore, any equivalent technical changes made by using the contents of the description and drawings of the present invention are included in the protection scope of the present invention. .

100: Multilayer core board group 11: The first core board 111: Auxiliary marking unit 112: Auxiliary marking unit 113: Auxiliary marking unit 114: Auxiliary marking unit 11A: Wide side 12: The first core board 121: Auxiliary marking unit 122: Auxiliary marking unit 123: Auxiliary marking unit 124: Auxiliary marking unit 12A: Wide side 13: Second core board 131: marker unit 132: marker unit 133: Tag Unit 134: marker unit 13A: Wide side 14: Second core board 141: Tag Unit 142: marker unit 143: Tag Unit 144: marker unit 14A: Wide side 200: Multilayer circuit board 201: Through hole 202: Conductive layer 300: Multilayer Circuit Board Manufacturing Systems 301: Processing device 302: Scanning Device 303: Perforation forming equipment A1: Line area A2: Non-Line Area B1: virtual rectangle B2: virtual rectangle B3: virtual rectangle B4: virtual rectangle C1: virtual axis C2: Virtual axis P: Multilayer circuit board H: through hole R: allowable error range S11～S14: Process steps S21～S26: Process steps

FIG. 1 is a partial schematic diagram of a conventional multilayer circuit board.

FIG. 2 is a schematic flow chart of a method for forming a perforation of a multilayer circuit board according to the present invention.

3 is a schematic diagram of a multi-layer core board group of the perforation forming method of the multi-layer circuit board of the present invention.

FIG. 4 is an exploded schematic view of the multi-layer core board group of the perforation forming method of the multi-layer circuit board of the present invention.

FIG. 5 is an image obtained after the scanning device scans the multi-layer core board group of the present invention.

FIG. 6 is a schematic flowchart of the method for manufacturing a multilayer circuit board of the present invention.

FIG. 7 is a schematic diagram of the multilayer circuit board of the present invention.

8 is a schematic block diagram of the multilayer circuit board manufacturing system of the present invention.

S11~S14: Process steps

Claims (10)

A perforation forming method for a multilayer circuit board, comprising: A preparation step: prepare a multi-layer core board group, the multi-layer core board group is composed of a plurality of core boards arranged on top of each other, and the two core boards located on the opposite sides of the multi-layer core board group define It is the first core board, the other core boards are defined as the second core board, at least one of the second core boards has at least three marking units, and any one of the marking units is not associated with any one of the marking units in a longitudinal direction. The cells are completely overlapped, and the longitudinal direction is parallel to a normal to a surface of the first core board; A scanning step: using a scanning device to scan the multi-layer core board group to obtain the coordinates of each of the marking units; a calculation step: using a processing device to calculate a deformation amount of the second core board with the marking unit according to the coordinates corresponding to each of the marking units and a predetermined circuit board size information; and A forming step: controlling a perforation forming device, according to a deformation amount of each of the first core boards, the deformation amount of each of the second core boards with the marking unit, and a circuit board perforation position information, in At least one through hole is formed in the multi-layer core board group, and the through hole penetrates through each of the first core boards and each of the second core boards, so that the multi-layer core board composition is a multi-layer circuit board. The perforation forming method for a multilayer circuit board according to claim 1, wherein, in the preparation step, each of the second core boards has four of the marking units, and each of the second core boards includes a circuit area and a non-circuit area, wherein at least one circuit is formed in the circuit area, and each of the marking units included in each of the second core boards is disposed in the non-circuit area. The perforation forming method for a multilayer circuit board according to claim 1, wherein, in the preparation step, at least one of the first core boards has at least three auxiliary marking units, and any one of the auxiliary marking units is located in the The longitudinal direction does not completely overlap with any one of the auxiliary marking units or any of the marking units; in the scanning step, the scanning device also obtains the coordinates of each of the auxiliary marking units, and in the calculation step wherein, the processing device further calculates the deformation amount of the first core board with the auxiliary marking units according to the coordinates corresponding to each of the auxiliary marking units and the predetermined circuit board size information. The perforation forming method for a multilayer circuit board according to claim 3, wherein each of the first core boards is provided with four auxiliary marking units, and the four auxiliary marking units are located at four corners of a virtual rectangle , the shape of the virtual rectangle is a proportional reduction of the shape of the first core board, and the shape of the different virtual rectangles is the shape of the first core board reduced in different proportions. Each described second core board is provided with four described marking units, four described marking units are located at the four corners of a virtual rectangle, and the appearance of the described virtual rectangle where the four described marking units are located It is a proportional reduction of the shape of the second core board, and the shape of the virtual rectangle where the four different marking units are located is the shape of the second core board reduced in different proportions. . A method for manufacturing a multilayer circuit board, comprising: A core board marking step: forming at least three marking units on at least one wide side of a plurality of core boards; A combining step: fixing a plurality of the core boards to each other to form a multi-layer core board group, and any one of the marking units in the multi-layer core board group does not completely overlap with any one of the marking units in a longitudinal direction , the longitudinal direction is parallel to a normal line of a surface of the core board; A scanning step: using a scanning device to scan the multi-layer core board group to obtain the coordinates of each of the marking units; a calculation step: using a processing device to calculate a deformation of each of the core boards according to the coordinates corresponding to each of the marking units of each of the core boards and a predetermined circuit board size information; and a forming step: controlling a perforation forming device to form at least one through hole in the multi-layer core board group according to each of the deformation amounts and a position information of a circuit board perforation, and the through hole penetrates each of the core boards; A conductive layer forming step: forming a conductive layer in at least one of the through holes, so that the multi-layer core board is composed of a multi-layer circuit board. The method for manufacturing a multilayer circuit board according to claim 5, wherein, in the core board marking step, at least one circuit is formed in a circuit area of each of the core boards, and at least one circuit is formed in a circuit area of each of the core boards The non-line areas form four of the marked cells. The method for manufacturing a multilayer circuit board according to claim 5, wherein each of the core boards is provided with four marking units, and the four marking units are located at four corners of a virtual rectangle, and the The outer shape is a proportional reduction of the outer shape of the core board, and the different virtual rectangle shapes are formed by reducing the outer shape of the core board in different proportions. The method for manufacturing a multilayer circuit board according to claim 5, wherein each of the marking units does not penetrate the core board. A multilayer circuit board, which is produced by the method for manufacturing a multilayer circuit board according to any one of claims 5 to 8. A multilayer circuit board manufacturing system comprising a processing device, a scanning device and a perforation forming apparatus, the processing device can execute the multilayer circuit board manufacturing method according to any one of claims 5 to 8.

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