CN115776768A - Multilayer circuit board, method and system for manufacturing the same, and method for forming through-hole in the same - Google Patents

Abstract

The invention discloses a perforation forming method of a multilayer circuit board, a manufacturing method of the multilayer circuit board, the multilayer circuit board and a manufacturing system of the multilayer circuit board. The perforation forming method of the multilayer circuit board comprises the following steps: the preparation method comprises the following steps: preparing a multilayer core plate group which comprises a plurality of core plates, wherein each core plate comprises marking units, and the marking units are not mutually overlapped in the longitudinal direction; a scanning step: scanning the multilayer chip set to obtain the coordinates of each marking unit; a calculation step: calculating the deformation of each core plate by using the coordinates; a forming step: and forming at least one through hole in the multilayer core board group according to the deformation and the punching position information of the circuit board, so that the multilayer core board is formed into the multilayer circuit board.

Description

Multilayer circuit board, method and system for manufacturing the same, and method for forming through-hole in the same

Technical Field

The present invention relates to a method for forming a through hole in a circuit board, a method for manufacturing a circuit board, and a system for manufacturing a circuit board, and more particularly, to a method for forming a through hole in a multilayer circuit board, a method for manufacturing a multilayer circuit board, and a system for manufacturing a multilayer circuit board.

Background

A conventional multi-layer circuit board is formed by laminating a plurality of core boards, each core board has a circuit electrically connected to each other, and the multi-layer circuit board usually has at least one Plated Through Hole (PTH) or a commonly known via Hole (via). The formation of plated through holes or what is commonly referred to as via holes is: firstly, forming a through hole on the multilayer circuit board, and then electroplating a conductive layer in the through hole.

As shown in fig. 1, as the line diameter of the circuit on each core board becomes smaller, the diameter of the through hole is also reduced, and therefore, with the related manufacturing process of the conventional multilayer circuit board P, a problem (commonly referred to as partial breakage in the art) that the through hole H exceeds the allowable error range R of the core board where the through hole is to be provided tends to occur, which may cause the circuit in the core board to be broken, and the like, thereby causing a problem of lowering the manufacturing yield of the multilayer circuit board.

Disclosure of Invention

The invention discloses a perforation forming method of a multilayer circuit board, a manufacturing method of the multilayer circuit board, the multilayer circuit board and a manufacturing system of the multilayer circuit board, which are mainly used for improving the problem that a through hole is easy to exceed the original preset position of a core plate in the existing manufacturing method of the multilayer circuit board, so that the manufacturing yield of the multilayer circuit board is reduced.

One embodiment of the present invention discloses a method for forming a through hole of a multi-layer circuit board, which comprises: a preparation step: preparing a multilayer core plate group, wherein the multilayer core plate group is formed by a plurality of core plates which are arranged in an overlapped mode, two core plates which are positioned on two opposite sides of the multilayer core plate group are defined as first core plates, the other core plates are defined as second core plates, at least one second core plate is provided with at least three marking units, any marking unit is not completely overlapped with any marking unit in a longitudinal direction, and the longitudinal direction is parallel to a normal line of one surface of the first core plate; a scanning step: scanning the multilayer core plate group by using a scanning device to obtain a coordinate of each marking unit; a calculation step: calculating a deformation of the second core board with the marking units by using a processing device according to the coordinates corresponding to the marking units and preset circuit board size information; a forming step: and controlling a perforation forming device to form at least one through hole in the multi-layer core board set according to the deformation of each first core board, the deformation of each second core board with the marking unit and the perforation position information of the circuit board, wherein the through hole penetrates through each first core board and each second core board, so that the multi-layer core boards form the multi-layer circuit board.

One embodiment of the present invention discloses a method for manufacturing a multilayer circuit board, which comprises: a core plate marking step: forming at least three marking units on at least one wide side surface of the core boards; a combination step: fixing a plurality of core plates to form a multilayer core plate group, wherein any marking unit of the multilayer core plate group is not completely overlapped with any marking unit in a longitudinal direction, and the longitudinal direction is parallel to a normal line of one surface of the core plate; a scanning step: scanning the multi-layer core plate group by using a scanning device to obtain a coordinate of each marking unit; a calculation step: calculating a deformation of each core board by using a processing device according to the coordinate corresponding to each marking unit of each core board and preset circuit board size information; a forming step: controlling a perforation forming device to form at least one through hole in the multi-layer core plate group according to the deformation and the position information of the circuit board perforation, wherein the through hole penetrates through each core plate; a conductive layer forming step: forming a conductive layer in at least one through hole, so that the multi-layer core board is formed into a multi-layer circuit board.

One embodiment of the invention discloses a multilayer circuit board which is manufactured by the manufacturing method of the multilayer circuit board.

One embodiment of the invention discloses a multi-layer circuit board manufacturing system, which comprises a processing device, a scanning device and a perforation forming device, wherein the processing device can execute the multi-layer circuit board manufacturing method.

In summary, the perforation forming method of the multi-layer circuit board, the manufacturing method of the multi-layer circuit board, the multi-layer circuit board and the manufacturing system of the multi-layer circuit board of the present invention can greatly reduce the occurrence probability of the problem that the through hole exceeds the original predetermined position of the core plate through the design of the marking unit, etc., and can effectively improve the manufacturing yield of the multi-layer circuit board.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for illustration purposes only and are not intended to limit the scope of the invention in any way.

Drawings

FIG. 1 is a schematic diagram of a multi-layer circuit board via formation after a conventional fabrication process;

FIG. 2 is a schematic flow chart of a method for forming through holes in a multi-layer circuit board according to the present invention;

FIG. 3 is a schematic view of a multilayer core plate assembly of the method for via formation of a multilayer circuit board of the present invention;

FIG. 4 is an exploded view of a multilayer core plate assembly of the method for forming a via hole in a multilayer circuit board of the present invention;

FIG. 5 is an image of a multi-layer core board set of the present invention scanned by a scanner;

FIG. 6 is a schematic flow chart of a method for manufacturing a multilayer circuit board according to the present invention;

FIG. 7 is a schematic view of a multilayer circuit board of the present invention;

FIG. 8 is a block diagram of a multi-layered circuit board manufacturing system according to the present invention.

Description of the symbols

100: multilayer core plate group

11: first core plate

111: auxiliary marking unit

112: auxiliary marking unit

113: auxiliary marking unit

114: auxiliary marking unit

11A: broad side

12: first core plate

121: auxiliary marking unit

122: auxiliary marking unit

123: auxiliary marking unit

124: auxiliary marking unit

12A: broad side

13: second core board

131: marking unit

132: marking unit

133: marking unit

134: marking unit

13A: broad side

14: second core plate

141: marking unit

142: marking unit

143: marking unit

144: marking unit

14A: broad side

200: multilayer circuit board

201: through hole

202: conductive layer

300: multilayer circuit board manufacturing system

301: processing apparatus

302: scanning device

303: perforation forming apparatus

A1: line area

A2: non-line area

B1: virtual rectangle

B2: virtual rectangle

B3: virtual rectangle

B4: virtual rectangle

C1: virtual axis

C2: virtual axis

P: multilayer circuit board

H: through hole

R: tolerance error range

Detailed Description

In the following description, reference is made to or shown in the accompanying drawings for the purpose of illustrating the subject matter described herein, and in which is shown by way of illustration only, and not by way of limitation, specific reference may be made to the following description.

Referring to fig. 2 to 5, fig. 2 is a schematic flow chart of a method for forming a through hole of a multilayer circuit board according to the present invention, fig. 3 is a schematic view of a multilayer circuit board according to the method for forming a through hole of a multilayer circuit board according to the present invention, fig. 4 is an exploded schematic view of a multilayer circuit board according to the method for forming a through hole of a multilayer circuit board according to the present invention, and fig. 5 is an image obtained by scanning the multilayer circuit board according to the present invention with a scanning device.

The perforation forming method of the multilayer circuit board comprises the following steps:

a preparation step S11: preparing a multilayer core plate group, wherein the multilayer core plate group is composed of a plurality of core plates which are arranged in an overlapped mode, two core plates which are positioned on two opposite sides of the multilayer core plate group are defined as first core plates, the rest core plates are defined as second core plates, at least one part of the second core plates are provided with at least three marking units, any marking unit is not completely overlapped with any marking unit in a longitudinal direction (such as the Z-axis direction in figure 3), and the longitudinal direction is parallel to a normal line of one surface (such as the wide side surface 11A of the first core plate 11) of the first core plate;

a scanning step S12: scanning the multi-layer core plate group by using a scanning device (such as an X-ray scanning device) to obtain a coordinate of each marking unit;

a calculating step S13: calculating a deformation of the second core board with the marking units by using a processing device according to the coordinates corresponding to the marking units and preset circuit board size information; and

a forming step S14: controlling a perforation forming device (such as a laser perforation device) to form at least one through hole in the multi-layer core board set according to the deformation of the first core board, the deformation of the second core board and the perforation position information of the circuit board. The through holes penetrate through the first core plates and the second core plates.

As shown in fig. 3 and 4, the multilayer core board set 100 described in the preparation step S11 is shown. The multi-layer core board set 100 may include 4 core boards, for example, two of the core boards are defined as two first core boards 11 and 12, the other two core boards are defined as two second core boards 13 and 14, the two second core boards 13 and 14 are located between the two first core boards 11 and 12, and the sizes of the core boards are substantially the same. It should be noted that, for convenience, the multilayer core board group 100 only includes 4 core boards, and in practical applications, the multilayer core board group 100 may include more than 10 core boards, that is, the number of the second core boards included in the multilayer core board group 100 may be more than 2. The manner in which the plurality of core plates included in the multilayer core plate group 100 are fixed to each other is not limited herein.

One of the wide side surfaces 11A, 12A of each first core board 11, 12 may have a circuit area A1 and a non-circuit area A2, at least one circuit may be formed on the circuit area A1, and the circuit in the circuit area A1 is commonly called a PCB layout. One of the wide side surfaces 13A, 14A of each of the second core boards 13, 14 may have a circuit area A1 and a non-circuit area A2, where at least one circuit is formed on the circuit area A1, and the circuit is commonly referred to as a PCB layout.

In one embodiment, one of the second core boards 13 may be provided with four marking units 131, 132, 133 and 134 in the non-circuit area A2, the four marking units 131, 132, 133 and 134 may be substantially disposed at four corners of a virtual rectangle B1, the other one of the second core boards 14 may be provided with four marking units 141, 142, 143 and 144 in the non-circuit area A2, and the four marking units 141, 142, 143 and 144 may be substantially disposed at four corners of a virtual rectangle B2. In practical applications, the shape of the virtual rectangle B1 is an equal scaling down of the shape of the second core board 13, and the shape of the virtual rectangle B2 is an equal scaling down of the shape of the second core board 14.

Each of the marking units 131, 132, 133, 134 may be a structure formed on the surface of the second core plate 13, and each of the marking units 131, 132, 133, 134 is a structure that does not penetrate through the second core plate 13. Each of the marking units 141, 142, 143, 144 may be a structure formed at a surface of the second core plate 14, and each of the marking units 141, 142, 143, 144 is a structure that does not penetrate the second core plate 14. Of course, in a particular application, the individual marking elements may also be perforations through the second core plate. In addition, each second core board may also include three or more than five marking units. The specific shape and size of the marking cells may vary according to requirements, and are shown in the drawings as an exemplary embodiment.

It should be noted that, in fig. 4, the four marking units 131, 132, 133, and 134 of one of the second core plates 13 are disposed on the wide side 13A of the second core plate 13 facing the first core plate 11, and the four marking units 141, 142, 143, and 144 of the other second core plate 14 are disposed on the wide side 14A facing the other second core plate 13, but the four marking units 131, 132, 133, 134, 141, 142, 143, and 144 included in each of the second core plates 13 and 14 may also be disposed on different wide sides.

As shown in fig. 4, the outlines of the two virtual rectangles B1, B2 are formed by reducing the outlines of the second core boards 13, 14 in different proportions, and the sizes of the two virtual rectangles B1, B2 are different, so that, as shown in fig. 5, in the image obtained after the scanning device scans the multi-layer core board set 100, the marking units 131, 132, 133, 134, 141, 142, 143, 144 belonging to different second core boards 13, 14 are not overlapped with each other, that is, the marking units are arranged in a staggered manner with each other in the image obtained after the scanning device scans the multi-layer core board set 100.

As described above, as shown in fig. 5, in the image obtained after the scanning device scans the multi-layer core board set 100, two of the marking units 131 and 132 of the second core board 13 and two of the marking units 141 and 142 of the second core board 14 may be located on the same virtual axis C1, two of the other marking units 133 and 134 of the second core board 13 and two of the other marking units 143 and 143 of the second core board 14 may be located on another virtual axis C2, the marking units 131, 132, 141 and 142 are not overlapped with each other on the virtual axis C1, and the marking units 133, 134, 143 and 144 are not overlapped with each other on the virtual axis C2.

The scanning device is not limited to an X-ray scanning device, and any scanning device having a penetrating light is applicable to the scanning device described herein, or any scanning device that can scan the multi-layered core board assembly 100 to obtain the coordinates of each marking unit is also applicable to the scanning device described herein.

As shown in fig. 5, by providing the plurality of marking units 131, 132, 133, 134, 141, 142, 143, 144 of the second core boards 13, 14, after the scanning step S12, the scanning device can obtain the coordinates corresponding to the marking units 131, 132, 133, 134, 141, 142, 143, 144, and in the calculating step S13, the processing device can calculate a current size of the second core board 13 (14) by using the four marking units 131, 132, 133, 134 (141, 142, 143, 144) provided in the same second core board 13 (14), and then the processing device can compare and calculate the current size with a predetermined size of each second core board 13 (14) included in predetermined circuit board size information, so that the processing device can calculate the deformation amount (for example, expansion and contraction amount) of each second core board 13 (14).

In the forming step S14, the deformation (i.e. the expansion/contraction value) of each first core board can be obtained in various manners, for example, the processing device can first control the image extraction device (e.g. various cameras) to respectively extract the images of the two first core boards to obtain two extracted images, and then compare the two extracted images with the pre-stored image of the standard first core board (or the predetermined size data of the first core board), so that the processing device can calculate the deformation of each first core board.

In one embodiment, in the step S11, one of the wide sides 11A of one of the first core boards 11 may have four auxiliary mark units 111, 112, 113, and 114, and the four auxiliary mark units 111, 112, 113, and 114 are disposed at four corners of a virtual rectangle B3; one of the wide sides 12A of the other first core 12 may have four auxiliary mark units 121, 122, 123, 124, where the four auxiliary mark units 121, 122, 123, 124 are disposed at four corners of a virtual rectangle B4; any one of the auxiliary mark units 111, 112, 113, 114, 121, 122, 123, 124 does not completely overlap with any one of the auxiliary mark units or the mark unit in the longitudinal direction (the Z-axis direction shown in fig. 3). The shape of the virtual rectangle B3 is formed by reducing the shape of the first core board 11 in equal proportion, the shape of the virtual rectangle B4 is formed by reducing the shape of the first core board 12 in equal proportion, and the sizes of the virtual rectangle B3 and the virtual rectangle B4 are different.

As shown in fig. 5, in an image obtained after the scanning device scans the multi-layer core assembly 100, the auxiliary marking units 111, 112, 121, and 122 and the marking units 131, 132, 141, and 142 may be located on the same axis C1, and the auxiliary marking units 113, 114, 123, and 124 and the marking units 133, 134, 143, and 144 may be located on the same axis C2.

In the scanning step S12, the scanning device may obtain coordinates of each auxiliary mark unit, and in the calculating step, the processing device may further calculate a current size of each first core board 11, 12 according to the coordinates corresponding to each auxiliary mark unit, and the processing device may compare and calculate the current size of each first core board and a preset size of each first core board 11, 12 included in the preset circuit board size information, so that the processing device may calculate a deformation amount (e.g., an expansion/contraction amount) of each first core board 11, 12.

As described above, by designing four marking units on each second core board, the processing device can calculate the expansion/contraction value of each second core board in the calculating step S13, so that when the processing device executes the forming step S14, it can determine whether to modify at least one predetermined punching position coordinate included in the punching position information of the circuit board according to the deformation amount of each first core board and the deformation amount (i.e., the expansion/contraction value) of each second core board, thereby ensuring that the through holes formed on the multilayer core board set 100 do not exceed the allowable error range of the first core board or any second core board.

In summary, the method for forming through holes of a multi-layer circuit board of the present invention can effectively improve the problem that the through holes are easily deviated from the tolerance range of at least one of the core boards in the conventional method for manufacturing the multi-layer circuit board.

It should be noted that, in practical applications, related personnel may form the mark unit or the auxiliary mark unit only on the core board which is easy to deform according to different characteristics of each core board, that is, the multilayer circuit board may not have a mark unit or an auxiliary mark unit on each core board, but the multilayer circuit board may have only a part of the second core boards provided with the mark unit, and the rest of the core boards are not provided with the mark unit or the auxiliary mark unit.

In addition, in the embodiment, the marking unit or the auxiliary marking unit is provided on a single wide side of each core board, but in different embodiments, each core board may also have two wide sides provided with the marking unit or the auxiliary marking unit, so that the processing device may calculate the deformation amount (i.e., layer deviation) between the two wide sides of the core board by using all the marking units on the same core board.

Referring to fig. 6 and 7 together, fig. 6 is a flow chart illustrating a method for manufacturing a multilayer circuit board according to the present invention, and fig. 7 is a multilayer circuit board manufactured by the method for manufacturing a multilayer circuit board according to the present invention. The manufacturing method of the multilayer circuit board comprises the following steps:

a core plate marking step S21: forming at least three marking units on at least one wide side surface of a plurality of core boards (i.e. each first core board and each second core board);

a combining step S22: fixing a plurality of core boards to form a multi-layer core board assembly 100 (as shown in fig. 3), wherein any marking unit (i.e., the aforementioned marking unit and the auxiliary marking unit) of the multi-layer core board assembly does not completely overlap with any marking unit in a longitudinal direction (e.g., the Z-axis direction shown in fig. 3), and the longitudinal direction is parallel to a normal of a surface (e.g., the wide side surface 11A of the first core board 11) of the multi-layer core board assembly;

a scanning step S23: scanning the multilayer core plate group by using a scanning device to obtain a coordinate of each marking unit;

a calculating step S24: calculating a deformation of each core board by using a processing device according to the coordinate corresponding to each marking unit of each core board and preset circuit board size information; and

a forming step S25: controlling a perforation forming device to form at least one through hole in the multi-layer core plate group according to the deformation and the perforation position information of the circuit board, wherein the through hole penetrates through each core plate;

a conductive layer forming step S26: a conductive layer is formed in at least one of the through holes, so that the multi-layer core board is formed into a multi-layer circuit board 200.

As shown in fig. 3, in the core plate marking step S21, four auxiliary marking units 111, 112, 113, 114, 121, 122, 123, 124 are respectively formed on the wide side surfaces 11A, 12A of the first core plates 11, 12, and four marking units 131, 132, 133, 134, 141, 142, 143, 144 are respectively formed on the wide side surfaces 13A, 14A of the second core plates 13, 14.

In the combining step S22, the plurality of core boards may be fixed to each other by means of bonding or the like as required. The contents of the longitudinal direction and the like in the combining step S22 are the same as those described in the foregoing embodiments, and are not described again here. The scanning step S23, the calculating step S24 and the forming step S25 in this embodiment are the same as the scanning step S12, the calculating step S13 and the forming step S14 in the previous embodiments, and are not repeated herein.

The conductive layer forming step S26 may be, for example, forming the conductive layer 202 in the Through holes by using an electroplating technique, so that at least one Through Hole 201 becomes a Plated Through Hole (PTH) or a commonly known Through Hole (via), the material of the conductive layer 202 may be, for example, copper, but not limited thereto, and after the conductive layer forming step S26, the Through Hole 201 without the conductive layer 202 formed becomes an unplated Through Hole (NPTH).

The manufacturing method of the multilayer circuit board of the present invention is described only for the greatest difference between the present invention and the existing manufacturing method of the multilayer circuit board, and in the practical application, the manufacturing method of the multilayer circuit board of the present invention may further add other different process steps according to the requirements, for example, after the conductive layer forming step S26, an Automatic Optical Inspection (AOI) step may be added to inspect the multilayer circuit board by using an automatic Optical Inspection apparatus; a blackening step or a browning step may be added between the combining step S22 and the scanning step S23 to remove impurities on the surface of the circuit board by using a blackening apparatus or a browning apparatus, an exposure step may be added after the conductive layer forming step S26 to form blind holes on the surface of the multilayer circuit board by using an exposure apparatus, and an automatic optical inspection step may be added after the exposure step.

Referring to FIG. 8, a block diagram of a multi-layer circuit board manufacturing system according to the present invention is shown. The multi-layer circuit board manufacturing system 300 of the present invention comprises a processing device 301, a scanning device 302 and a via forming apparatus 303. The processing device 301 is electrically connected to the scanning device 302 and the hole-forming device 303, and the processing device 301 can perform the aforementioned method for manufacturing a multi-layer circuit board 200 (as shown in fig. 7). For a detailed description of the scanning device 302 and the perforation forming apparatus 303, please refer to the foregoing description, and further description is omitted here. In practical applications, the multi-layer circuit board manufacturing system 300 may further include a blackening/browning device, an exposure device, an automatic optical inspection device, and the like according to requirements.

In summary, the perforation forming method, the manufacturing system and the multi-layer circuit board of the multi-layer circuit board according to the present invention can make the through holes formed in the multi-layer circuit board not easily occur within the tolerance range (also known as the offset problem) of the position of the core board where the through holes are originally predetermined by designing the plurality of marking units, thereby improving the production yield of the multi-layer circuit board.

In addition, the marking unit or the auxiliary marking unit can be formed together when related equipment forms circuits on the core board, so that the manufacturing complexity of the multilayer circuit board is not increased.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, so that all the modifications made by the equivalent techniques using the contents of the present specification and the attached drawings are included in the protection scope of the present invention.

Claims (10)

1. A method of via formation for a multilayer circuit board, comprising:

the preparation method comprises the following steps: preparing a multilayer core plate group, wherein the multilayer core plate group is composed of a plurality of core plates which are arranged in an overlapped mode, two core plates which are positioned on two opposite sides of the multilayer core plate group are defined as first core plates, the other core plates are defined as second core plates, at least one second core plate is provided with at least three marking units, any marking unit is not completely overlapped with any marking unit in a longitudinal direction, and the longitudinal direction is parallel to a normal line of the surface of the first core plate;

a scanning step: scanning the multilayer chip group by using a scanning device to obtain the coordinates of each marking unit;

a calculation step: calculating the deformation of the second core board with the marking units by using a processing device according to the coordinates corresponding to the marking units and preset circuit board size information; and

a forming step: and controlling perforation forming equipment to form at least one through hole in the multilayer core board set according to the deformation of each first core board, the deformation of each second core board with the marking unit and the perforation position information of the circuit board, wherein the through hole penetrates through each first core board and each second core board, so that the multilayer core boards are combined into the multilayer circuit board.

2. The method of punching a multilayer circuit board according to claim 1, wherein in the preparing step, each of the second core boards has four of the marking units, each of the second core boards includes a wiring region in which at least one wiring is formed and a non-wiring region in which each of the marking units included in each of the second core boards is disposed.

3. A multilayer circuit board perforation forming method according to claim 1, wherein in said preparation step, at least one of said first core boards has at least three auxiliary marking units, any one of said auxiliary marking units does not completely overlap with any one of said auxiliary marking units or any one of said marking units in said longitudinal direction; in the scanning step, the scanning device further obtains coordinates of each auxiliary marking unit, and in the calculating step, the processing device further calculates the deformation amount of the first core board with the auxiliary marking units according to the coordinates corresponding to each auxiliary marking unit and the preset circuit board size information.

4. The method of claim 3, wherein each of the first core boards is provided with four auxiliary mark units, the four auxiliary mark units are located at four corners of a virtual rectangle, the shape of the virtual rectangle is an equal scaling down of the shape of the first core board, and the shape of the different virtual rectangle is a scaling down of the shape of the first core board; each second core board is provided with four marking units, the four marking units are positioned at four corners of a virtual rectangle, the appearance of the virtual rectangle in which the four marking units are positioned is reduced in equal proportion to the appearance of the second core board, and the appearance of the virtual rectangle in which the four different marking units are positioned is reduced in different proportion to the appearance of the second core board.

5. A method of manufacturing a multilayer circuit board, comprising:

core plate marking: forming at least three marking units on at least one wide side surface of the plurality of core plates;

the combination step is as follows: fixing a plurality of the core plates to each other to form a multilayer core plate group, wherein any one of the marking units of the multilayer core plate group does not completely overlap with any one of the marking units in a longitudinal direction, and the longitudinal direction is parallel to a normal line of a surface of the core plate;

a scanning step: scanning the multilayer chip group by using a scanning device to obtain the coordinates of each marking unit;

and (3) calculating: calculating the deformation of each core board by using a processing device according to the coordinates corresponding to each marking unit of each core board and the preset circuit board size information; and

a forming step: controlling a hole forming device to form at least one through hole in the multilayer core plate group according to each deformation and the position information of the circuit board through holes, wherein the through hole penetrates through each core plate;

a conductive layer forming step: and forming a conductive layer in at least one through hole so that the multilayer core board is formed into a multilayer circuit board.

6. The method of manufacturing a multi-layered circuit board according to claim 5, wherein in the core marking step, at least one wiring is formed in the wiring area of each core, and four marking units are formed in the non-wiring area of each core.

7. The method of claim 5, wherein each of the core boards is provided with four of the marking units, the four marking units are located at four corners of a virtual rectangle, the shape of the virtual rectangle is an equal scale reduction of the shape of the core board, and the shape of the different virtual rectangle is a different scale reduction of the shape of the core board.

8. The method of manufacturing a multilayer circuit board according to claim 5, wherein each of the marking units does not penetrate the core board.

9. A multilayer circuit board produced by the multilayer circuit board production method as claimed in any one of claims 5 to 8.

10. A multilayer circuit board manufacturing system comprising a processing device capable of executing the multilayer circuit board manufacturing method according to any one of claims 5 to 8, a scanning device, and a punch forming apparatus.

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