TWI386126B - Method for cutting copper-clad laminate - Google Patents

Method for cutting copper-clad laminate Download PDF

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TWI386126B
TWI386126B TW97125450A TW97125450A TWI386126B TW I386126 B TWI386126 B TW I386126B TW 97125450 A TW97125450 A TW 97125450A TW 97125450 A TW97125450 A TW 97125450A TW I386126 B TWI386126 B TW I386126B
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Taiwan
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identification mark
copper
clad substrate
circuit board
warp
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TW97125450A
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Chinese (zh)
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TW201004509A (en
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Tao Ming Liao
Wen Tsun Chen
Chia Hung Shen
Shin Chih Liaw
Cheng Hsien Lin
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Zhen Ding Technology Co Ltd
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Description

覆銅基板裁切方法 Copper clad substrate cutting method

本發明涉及電路板製造技術,尤其涉及一種覆銅基板裁切方法。 The present invention relates to a circuit board manufacturing technology, and in particular, to a copper clad substrate cutting method.

隨著電子產業之飛速發展,作為電子產品基本構件之電路板製作技術顯得越來越重要,線路與孔之製作要求亦越來越精細。電路板具有單面板、雙面板以及多層板之分,均由覆銅基板經裁切、鑽孔、蝕刻、曝光、顯影等一系列製程製作而成。具體可參閱C.H.Steer等人於Proceedings of the IEEE,Vol.39,No.2(2002年8月)中發表之“Dielectric characterization of printed circuit board substrates”一文。 With the rapid development of the electronics industry, the circuit board manufacturing technology, which is the basic component of electronic products, is becoming more and more important, and the requirements for the production of lines and holes are becoming more and more refined. The circuit board has single-panel, double-panel and multi-layer boards, which are all made by a series of processes such as cutting, drilling, etching, exposure and development of the copper-clad substrate. For details, see "Dielectric characterization of printed circuit board substrates" by C. H. Steer et al., Proceedings of the IEEE, Vol. 39, No. 2 (August 2002).

電路板加工製作過程中,通常需要將大尺寸之覆銅基板裁切成若干小尺寸之電路板單元。覆銅基板之主要組成材料包括玻纖布以及銅箔。其中,玻纖布作為銅箔之載體,係由玻璃纖維以平織法製造而成。 In the process of manufacturing a circuit board, it is usually necessary to cut a large-sized copper-clad substrate into a plurality of small-sized circuit board units. The main constituent materials of the copper-clad substrate include fiberglass cloth and copper foil. Among them, the glass fiber cloth is used as a carrier of the copper foil, and is made of glass fiber by a plain weave method.

然而,由於玻纖布自身之纖維結構於經緯方向之排佈密度與方式不同,造成覆銅基板於經緯方向具有不同結構,進而使得覆銅基板於經緯方向之漲縮率不同。因而,為保證裁板品質,先前覆銅基板於裁切時採用單一之排版方式,該單一之排版方式使得覆銅基板具有較大之餘料無法利用,具有較低之覆銅基板利用率,從而增加電路板製作成本。 However, since the fiber structure of the fiberglass cloth itself is different in the distribution in the warp and weft direction, the copper-clad substrate has different structures in the warp and weft directions, and the copper-clad substrate has different shrinkage rates in the warp and weft directions. Therefore, in order to ensure the quality of the panel, the previous copper-clad substrate adopts a single typesetting method during cutting, and the single typesetting method makes the copper-clad substrate have a large residual material and cannot be utilized, and has a low utilization ratio of the copper-clad substrate. Thereby increasing the manufacturing cost of the board.

有鑑於此,提供一種能提高覆銅基板利用效率之覆銅基 板裁切方法實屬必要。 In view of this, a copper-clad type capable of improving the utilization efficiency of a copper-clad substrate is provided. The board cutting method is really necessary.

以下將以具體實施例說明一種可提高覆銅基板利用效率之覆銅基板裁切方法。 Hereinafter, a copper clad substrate cutting method capable of improving the utilization efficiency of a copper-clad substrate will be described with reference to specific embodiments.

一種覆銅基板裁切方法,其包括以下步驟:提供覆銅基板,其具有經向與緯向;對覆銅基板進行排版,並使得排版後之覆銅基板包括長度方向平行於覆銅基板經向之複數第一電路板單元與長度方向平行於覆銅基板緯向之複數第二電路板單元;於第一電路板單元製作第一經緯向識別記號,於第二電路板單元製作第二經緯向識別記號;裁切覆銅基板以得到複數具有第一經緯向識別記號之第一電路板單元與複數具有第二經緯向識別記號之第二電路板單元;以及分別將複數第一電路板單元與複數第二電路板單元進行堆疊。 A copper-clad substrate cutting method, comprising the steps of: providing a copper-clad substrate having a warp direction and a weft direction; and patterning the copper-clad substrate, and causing the copper-clad substrate after the layout to include the length direction parallel to the copper-clad substrate a plurality of first circuit board units and a plurality of second circuit board units whose longitudinal direction is parallel to the latitudinal direction of the copper-clad substrate; a first warp and weft identification mark is formed in the first circuit board unit, and a second longitude and longitude is produced in the second circuit board unit Identifying a mark; cutting a copper clad substrate to obtain a plurality of first circuit board units having a first warp and weft identification mark; and a plurality of second circuit board units having a second warp and weft identification mark; and respectively dividing the plurality of first circuit board units Stacking with a plurality of second circuit board units.

相較於先前技術,本技術方案之覆銅基板裁切方法具有如下優點:首先,於覆銅基板上進行長度方向平行於覆銅基板經向之第一電路板單元與長度方向平行於覆銅基板緯向之第二電路板單元之混合排版,有效利用覆銅基板之面積,節省覆銅基板材料與成本;其次,利用經緯方向識別記號對電路板單元進行標記,避免電路板單元經緯方向之顛倒;再次,於第一電路板單元製作第一經緯向識別記號,於第二電路板單元製作第二經緯向識別記號,可有效區分第一電路板單元與第二電路板單元,避免兩者混合而造成後續製程中出現漲縮不一致、線路錯位以及孔位偏差等不良。 Compared with the prior art, the copper-clad substrate cutting method of the present invention has the following advantages: first, the first circuit board unit whose longitudinal direction is parallel to the copper-clad substrate and the length direction is parallel to the copper-clad on the copper-clad substrate The hybrid layout of the second circuit board unit in the latitudinal direction of the substrate effectively utilizes the area of the copper-clad substrate to save the material and cost of the copper-clad substrate; secondly, the circuit board unit is marked by the identification symbol of the warp and weft direction to avoid the warp and weft direction of the circuit board unit Reversing; again, creating a first warp and weft identification mark on the first circuit board unit, and making a second warp and weft identification mark on the second circuit board unit, which can effectively distinguish the first circuit board unit from the second circuit board unit, thereby avoiding both Mixing causes inconsistency in the expansion and contraction, line misalignment, and hole position deviation in subsequent processes.

下面將結合實施例與附圖對本技術方案之覆銅基板裁切方法作進一步之詳細說明。 The copper-clad substrate cutting method of the present technical solution will be further described in detail below with reference to the embodiments and the accompanying drawings.

本技術方案實施例提供之覆銅基板裁切方法包括以下步驟: The copper-clad substrate cutting method provided by the embodiment of the present technical solution includes the following steps:

第一步,提供覆銅基板10,其具有經向與緯向。 In the first step, a copper clad substrate 10 is provided having a warp direction and a weft direction.

覆銅基板10可為玻纖布基覆銅基板、紙基覆銅基板、複合基覆銅基板、芳醯胺纖維無紡布基覆銅基板以及合成纖維基覆銅基板等。 The copper-clad substrate 10 may be a fiberglass-based copper-clad substrate, a paper-based copper-clad substrate, a composite copper-clad substrate, an alimentamide-based nonwoven fabric-based copper-clad substrate, or a synthetic fiber-based copper-clad substrate.

請參閱圖1,本實施例中,該覆銅基板10為矩形,該矩形覆銅基板10之原始尺寸較大,需裁切成複數小尺寸電路板單元以便於後續加工製造,進而形成電路板成品。該電路板單元通常亦為矩形。 Referring to FIG. 1 , in the embodiment, the copper-clad substrate 10 has a rectangular shape. The rectangular copper-clad substrate 10 has a large original size and needs to be cut into a plurality of small-sized circuit board units for subsequent processing and manufacturing, thereby forming a circuit board. Finished product. The board unit is also typically rectangular.

第二步,根據預定電路板單元20之尺寸對覆銅基板10進行排版,並使得排版後之覆銅基板10包括長度方向平行於覆銅基板10經向之複數第一電路板單元22與長度方向平行於覆銅基板10緯向之複數第二電路板單元24。 In the second step, the copper clad substrate 10 is typeset according to the size of the predetermined circuit board unit 20, and the copper clad substrate 10 after the layout is arranged to include the plurality of first circuit board units 22 and the length direction parallel to the copper clad substrate 10. The direction is parallel to the plurality of second circuit board units 24 in the weft direction of the copper clad substrate 10.

請參閱圖2,建立直角坐標系XOY,其中Y軸方向代表覆銅基板10之經向,X軸方向代表覆銅基板10之緯向。本實施例中,該覆銅基板10之長度方向即長邊平行於Y軸方向,寬度方向即短邊平行於X軸方向。 Referring to FIG. 2, a Cartesian coordinate system XOY is established, wherein the Y-axis direction represents the warp direction of the copper-clad substrate 10, and the X-axis direction represents the weft direction of the copper-clad substrate 10. In the present embodiment, the longitudinal direction of the copper clad substrate 10, that is, the long side is parallel to the Y-axis direction, and the width direction, that is, the short side is parallel to the X-axis direction.

對覆銅基板10進行排版時,以使覆銅基板10可排佈最多電路板單元20為佳。本實施例中,於覆銅基板10上排佈九個第一電路板單元22以及兩個第二電路板單元24。 When the copper clad substrate 10 is typeset, it is preferable that the copper clad substrate 10 can arrange the most circuit board units 20. In the present embodiment, nine first circuit board units 22 and two second circuit board units 24 are arranged on the copper clad substrate 10.

具體地,首先,於覆銅基板10上根據電路板單元20之尺寸沿X軸方向依次排佈第一組之三個第一電路板單元22,該第一電路板單元22之長度方向平行於Y軸方向,寬度方向平行於X軸方向。其次,於上述第一組三個第一電路板單元22之下方再沿X軸方向依次排佈第二組之三個第一電路板單元22。再次,於上述第二組三個電路板單元之下方再沿X軸方向依次排佈第三組之三個第一電路板單元22。最後,由於覆銅基板10於排佈九個第一電路板單元22後還有很大之餘料,該餘料於Y軸方向之長度小於電路板單元20之長度,而大於電路板單元20之寬度。因此,可於覆銅基板10之餘料沿X軸方向依次排佈兩個第二電路板單元24,該第二電路板單元24之長度方向平行於X軸方向,寬度方向平行於Y軸方向。從而,按照圖2之方式進行排版時,可有效利用覆銅基板10之面積。 Specifically, first, three first circuit board units 22 of the first group are sequentially arranged on the copper clad substrate 10 in the X-axis direction according to the size of the circuit board unit 20, and the length direction of the first circuit board unit 22 is parallel to In the Y-axis direction, the width direction is parallel to the X-axis direction. Next, a second group of three first circuit board units 22 are sequentially arranged in the X-axis direction below the first group of three first circuit board units 22. Thirdly, three third circuit board units 22 of the third group are sequentially arranged in the X-axis direction below the second group of three circuit board units. Finally, since the copper clad substrate 10 has a large remaining material after the nine first circuit board units 22 are arranged, the length of the residual material in the Y-axis direction is smaller than the length of the circuit board unit 20, and larger than the circuit board unit 20 The width. Therefore, two second circuit board units 24 can be sequentially arranged in the X-axis direction on the remaining material of the copper clad substrate 10, the length direction of the second circuit board unit 24 is parallel to the X-axis direction, and the width direction is parallel to the Y-axis direction. . Therefore, when the layout is performed in the manner of FIG. 2, the area of the copper clad substrate 10 can be effectively utilized.

當然,相鄰電路板單元20之間應預留一定間隙。本實施例中,該間隙約為0.5mm~2mm,以避免裁切時對相鄰電路板單元20產生影響。 Of course, a certain gap should be reserved between adjacent circuit board units 20. In this embodiment, the gap is about 0.5 mm to 2 mm to avoid affecting adjacent circuit board units 20 during cutting.

另外,亦可於覆銅基板10先排佈第二電路板單元24,再排佈第一電路板單元22,僅需最大限度地利用覆銅基板10之面積即可。 In addition, the second circuit board unit 24 may be arranged first on the copper clad substrate 10, and the first circuit board unit 22 may be arranged, and only the area of the copper clad substrate 10 may be utilized to the maximum extent.

第三步,於第一電路板單元22製作第一經緯向識別記號,於第二電路板單元24製作第二經緯向識別記號。 In the third step, the first warp and weft identification mark is formed on the first circuit board unit 22, and the second warp and weft identification mark is created on the second circuit board unit 24.

請參閱圖3,利用機械加工、雷射加工或化學蝕刻等方法於該第一電路板單元22上製作第一經緯向識別記號,於 該第二電路板單元24上製作第二經緯向識別記號。該第一經緯向識別記號與第二經緯向識別記號可為一個或複數通孔。當第一經緯向識別記號與第二經緯向識別記號為一個通孔時,該通孔之橫截面可為不等腰三角形,該不等腰三角形之長邊對應第一電路板單元22之長度方向,短邊對應第一電路板單元22之寬度方向;於第二電路板單元24亦製作一個通孔,該通孔之橫截面亦為不等腰三角形,該不等腰三角形之長邊對應第二電路板單元24之長度方向,短邊對應第二電路板單元24之寬度方向。或者僅於第一電路板單元22製作不等腰三角形通孔,第二電路板單元24不製作不等腰三角形通孔,以識別第一電路板單元22與第二電路板單元24。 Referring to FIG. 3, a first warp and weft identification mark is formed on the first circuit board unit 22 by machining, laser processing, or chemical etching. A second warp and weft identification mark is formed on the second circuit board unit 24. The first warp and weft identification mark and the second warp and weft identification mark may be one or a plurality of through holes. When the first warp and weft direction identification mark and the second warp and weft direction identification mark are one through hole, the cross section of the through hole may be an isosceles triangle, and the long side of the isosceles triangle corresponds to the length of the first circuit board unit 22 In the direction, the short side corresponds to the width direction of the first circuit board unit 22; and the second circuit board unit 24 also forms a through hole, the cross section of the through hole is also an isosceles triangle, and the long side of the unequal waist triangle corresponds to The length direction of the second circuit board unit 24 corresponds to the width direction of the second circuit board unit 24. Alternatively, the unequal waist through hole is formed only in the first circuit board unit 22, and the second circuit board unit 24 does not make the unequal waist through hole to identify the first circuit board unit 22 and the second circuit board unit 24.

當第一經緯向識別記號與第二經緯向識別記號為複數通孔時,該第一經緯向識別記號包括第一識別記號2202與第二識別記號2222,該第二經緯向識別記號包括第三識別記號2402、第四識別記號2422與第五識別記號2424。該第一識別記號2202、第二識別記號2222、第三識別記號2402、第四識別記號2422與第五識別記號2424可為圓形通孔、方形通孔或五邊形通孔等。本實施例中,該第一識別記號2202、第二識別記號2222、第三識別記號2402、第四識別記號2422與第五識別記號2424均為圓形通孔,其直徑均約為1mm。 When the first warp and weft identification mark and the second warp and weft identification mark are plural through holes, the first warp and weft identification mark includes a first identification mark 2202 and a second identification mark 2222, and the second warp and weft identification mark includes the third The identification mark 2402, the fourth identification mark 2422, and the fifth identification mark 2424. The first identification mark 2202, the second identification mark 2222, the third identification mark 2402, the fourth identification mark 2422, and the fifth identification mark 2424 may be circular through holes, square through holes, or pentagonal through holes. In this embodiment, the first identification mark 2202, the second identification mark 2222, the third identification mark 2402, the fourth identification mark 2422, and the fifth identification mark 2424 are all circular through holes, each having a diameter of about 1 mm.

具體地,於該第一電路板單元22定義出相對之第一端部220與第二端部222,該第一端部220與第二端部222為第一電路板單元22相對之兩長邊或兩短邊所在之兩區域。 本實施例中,以第一電路板單元22兩短邊所在之兩區域分別作為第一端部220與第二端部222。該第一識別記號2202位於第一端部220之頂角區域,該第二識別記號2222位於第二端部222之中間區域。 Specifically, the first circuit board unit 22 defines an opposite first end portion 220 and a second end portion 222. The first end portion 220 and the second end portion 222 are opposite to each other by the first circuit board unit 22 The two areas where the side or the two short sides are located. In this embodiment, the two regions where the two short sides of the first circuit board unit 22 are located serve as the first end portion 220 and the second end portion 222, respectively. The first identification mark 2202 is located at a top corner area of the first end portion 220, and the second identification mark 2222 is located at an intermediate portion of the second end portion 222.

類似地,該第二電路板單元24具有相對之第三端部240與第四端部242。該第三識別記號2402位於第三端部240之頂角區域,該第四識別記號2422位於第四端部242之頂角區域,其與第三識別記號2402相對;該第五識別記號2424位於第四端部242之中間區域。優選地,該第三識別記號2402與第四識別記號2422之Y軸座標相同,該第四識別記號2422與第五識別記號2424之X軸座標相同,即第三識別記號2402與第四識別記號2422位於同一緯度,第四識別記號2422與第五識別記號2424位於同一經度。 Similarly, the second circuit board unit 24 has opposing third and second ends 240, 242. The third identification mark 2402 is located at a top corner area of the third end portion 240, and the fourth identification mark 2422 is located at a top corner area of the fourth end portion 242 opposite to the third identification mark 2402; the fifth identification mark 2424 is located The middle portion of the fourth end portion 242. Preferably, the third identification mark 2402 is the same as the Y-axis coordinate of the fourth identification mark 2422, and the fourth identification mark 2422 is the same as the X-axis coordinate of the fifth identification mark 2424, that is, the third identification mark 2402 and the fourth identification mark. 2422 is located at the same latitude, and fourth identification mark 2422 is at the same longitude as fifth identification mark 2424.

從而,操作人員僅需根據第一識別記號2202、第二識別記號2222、第三識別記號2402、第四識別記號2422以及第五識別記號2424之相對位置與數量關係即可識別電路板單元20之經緯方向,並能對第一電路板單元22與第二電路板單元24進行區分,以避免後續疊板時出現顛倒與混亂。 Therefore, the operator only needs to identify the circuit board unit 20 according to the relative position and quantity relationship of the first identification mark 2202, the second identification mark 2222, the third identification mark 2402, the fourth identification mark 2422, and the fifth identification mark 2424. In the warp and weft direction, the first circuit board unit 22 and the second circuit board unit 24 can be distinguished to avoid the reverse and chaos in the subsequent stacking.

當然,該經緯向識別記號之開設並不限於以上所描述之方式,僅需可幫助操作人員識別電路板單元20之經緯方向以及將第一電路板單元22與第二電路板單元24區分開之經緯向識別記號均於本方法保護範圍內。 Of course, the opening of the warp and weft identification mark is not limited to the manner described above, and only needs to help the operator to recognize the warp and weft direction of the circuit board unit 20 and distinguish the first circuit board unit 22 from the second circuit board unit 24. The warp and weft identification marks are all within the protection range of the method.

第四步,裁切覆銅基板10以得到第一電路板單元22與第 二電路板單元24。 In the fourth step, the copper clad substrate 10 is cut to obtain the first circuit board unit 22 and the first Two circuit board units 24.

利用裁切裝置(圖未示)對覆銅基板10進行裁切後,還可進一步分別將第一電路板單元22與第二電路板單元24進行分類堆疊加工製作。分類製作之前,可利用第一電路板單元22之第一經緯向識別記號與第二電路板單元24之第二經緯向識別記號將第一電路板單元22與第二電路板單元24進行區分並堆疊,如圖4所示,以方便進行後續製程。 After the copper clad substrate 10 is cut by a cutting device (not shown), the first circuit board unit 22 and the second circuit board unit 24 may be further divided and fabricated. Before the classification is made, the first circuit board unit 22 and the second circuit board unit 24 can be distinguished by using the first warp and weft identification mark of the first circuit board unit 22 and the second warp and weft identification mark of the second circuit board unit 24. Stacking, as shown in Figure 4, to facilitate subsequent processing.

堆疊作業完成後,再將電路板單元進行鑽孔、鍍銅、蝕刻、曝光以及顯影等一系列製程,以製造電路板成品。 After the stacking operation is completed, the circuit board unit is subjected to a series of processes such as drilling, copper plating, etching, exposure, and development to manufacture a finished circuit board.

本技術方案之覆銅基板裁切方法可有效利用覆銅基板10之面積。例如,當提供之覆銅基板10之尺寸為72mm×48mm,預定設計之電路板單元20之尺寸為17.5mm×15.6mm時,採用本技術方案之覆銅基板裁切方法進行排版時,最後能裁切得到十一個電路板單元20,具有較高之覆銅基板10利用率。 The copper-clad substrate cutting method of the present invention can effectively utilize the area of the copper-clad substrate 10. For example, when the size of the copper-clad substrate 10 provided is 72 mm×48 mm, and the size of the circuit board unit 20 of the predetermined design is 17.5 mm×15.6 mm, when the copper-clad substrate cutting method of the present technical solution is used for typesetting, The elliptical circuit board unit 20 is obtained by cutting, and has a higher utilization ratio of the copper-clad substrate 10.

並且,本技術方案利用經緯方向識別記號對電路板單元20進行標記,避免電路板單元20經緯方向顛倒,並且可有效區分第一電路板單元22與第二電路板單元24,避免兩者混合而造成後續製程中出現漲縮不一致、線路錯位以及孔位偏差等不良。 Moreover, the present technical solution marks the circuit board unit 20 by using the warp and weft direction identification marks, thereby avoiding the reverse rotation direction of the circuit board unit 20, and effectively distinguishing the first circuit board unit 22 from the second circuit board unit 24 to avoid mixing of the two. This caused problems such as inconsistent expansion and contraction, line misalignment, and hole position deviation in subsequent processes.

綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本 案技藝之人士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。 In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Familiar with this Equivalent modifications or variations made by those skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10‧‧‧覆銅基板 10‧‧‧Copper-clad substrate

20‧‧‧電路板單元 20‧‧‧Circuit unit

22‧‧‧第一電路板單元 22‧‧‧First board unit

24‧‧‧第二電路板單元 24‧‧‧Second circuit board unit

2202‧‧‧第一識別記號 2202‧‧‧First identification mark

2222‧‧‧第二識別記號 2222‧‧‧Second identification mark

2402‧‧‧第三識別記號 2402‧‧‧ Third identification mark

2422‧‧‧第四識別記號 2422‧‧‧ Fourth identification mark

2424‧‧‧第五識別記號 2424‧‧‧ fifth identification mark

220‧‧‧第一端部 220‧‧‧ first end

222‧‧‧第二端部 222‧‧‧ second end

240‧‧‧第三端部 240‧‧‧ third end

242‧‧‧第四端部 242‧‧‧ fourth end

圖1係本技術方案實施例提供之覆銅基板之示意圖。 FIG. 1 is a schematic diagram of a copper-clad substrate provided by an embodiment of the present technical solution.

圖2係本技術方案實施例提供之對覆銅基板排版後之示意圖。 FIG. 2 is a schematic diagram of the copper clad substrate after the layout of the embodiment of the present technical solution.

圖3係本技術方案實施例提供之於第一電路板單元標示第一經緯向識別記號與於第二電路板單元標示第二經緯向識別記號之示意圖。 FIG. 3 is a schematic diagram showing the first latitude and longitude identification mark on the first circuit board unit and the second latitude and longitude identification mark on the second circuit board unit according to the embodiment of the present technical solution.

圖4係本技術方案實施例提供之裁切覆銅基板後堆疊第一電路板單元與第二電路板單元之示意圖。 4 is a schematic diagram of stacking a first circuit board unit and a second circuit board unit after cutting a copper clad substrate according to an embodiment of the present technical solution.

10‧‧‧覆銅基板 10‧‧‧Copper-clad substrate

20‧‧‧電路板單元 20‧‧‧Circuit unit

22‧‧‧第一電路板單元 22‧‧‧First board unit

24‧‧‧第二電路板單元 24‧‧‧Second circuit board unit

2202‧‧‧第一識別記號 2202‧‧‧First identification mark

2222‧‧‧第二識別記號 2222‧‧‧Second identification mark

2402‧‧‧第三識別記號 2402‧‧‧ Third identification mark

2422‧‧‧第四識別記號 2422‧‧‧ Fourth identification mark

2424‧‧‧第五識別記號 2424‧‧‧ fifth identification mark

220‧‧‧第一端部 220‧‧‧ first end

222‧‧‧第二端部 222‧‧‧ second end

240‧‧‧第三端部 240‧‧‧ third end

242‧‧‧第四端部 242‧‧‧ fourth end

Claims (13)

一種覆銅基板裁切方法,其包括以下步驟:提供覆銅基板,其具有經向與緯向;對覆銅基板進行排版,並使得排版後之覆銅基板包括長度方向平行於覆銅基板經向之複數第一電路板單元與長度方向平行於覆銅基板緯向之複數第二電路板單元;於第一電路板單元製作第一經緯向識別記號,於第二電路板單元製作第二經緯向識別記號;裁切覆銅基板以得到複數具有第一經緯向識別記號之第一電路板單元與複數具有第二經緯向識別記號之第二電路板單元;以及分別將複數第一電路板單元與複數第二電路板單元進行堆疊。 A copper-clad substrate cutting method, comprising the steps of: providing a copper-clad substrate having a warp direction and a weft direction; and patterning the copper-clad substrate, and causing the copper-clad substrate after the layout to include the length direction parallel to the copper-clad substrate a plurality of first circuit board units and a plurality of second circuit board units whose longitudinal direction is parallel to the latitudinal direction of the copper-clad substrate; a first warp and weft identification mark is formed in the first circuit board unit, and a second longitude and longitude is produced in the second circuit board unit Identifying a mark; cutting a copper clad substrate to obtain a plurality of first circuit board units having a first warp and weft identification mark; and a plurality of second circuit board units having a second warp and weft identification mark; and respectively dividing the plurality of first circuit board units Stacking with a plurality of second circuit board units. 如申請專利範圍第1項所述之覆銅基板裁切方法,其中,該覆銅基板、第一電路板單元、第二電路板單元均為矩形。 The copper clad substrate cutting method according to the first aspect of the invention, wherein the copper clad substrate, the first circuit board unit, and the second circuit board unit are rectangular. 如申請專利範圍第1項所述之覆銅基板裁切方法,其中,該覆銅基板為玻纖布基覆銅基板、紙基覆銅基板、複合基覆銅基板、芳醯胺纖維無紡布基覆銅基板或合成纖維基覆銅基板。 The method for cutting a copper-clad substrate according to the first aspect of the invention, wherein the copper-clad substrate is a glass fiber-based copper-clad substrate, a paper-based copper-clad substrate, a composite copper-clad substrate, and a linalominic fiber non-woven fabric. A copper-clad substrate or a synthetic fiber-based copper-clad substrate. 如申請專利範圍第1項所述之覆銅基板裁切方法,其中,該第一經緯向識別記號與第二經緯向識別記號由機械加工、雷射加工或化學蝕刻方法製作。 The copper-clad substrate cutting method according to the first aspect of the invention, wherein the first warp and weft direction identification mark and the second warp and weft direction identification mark are produced by a machining, a laser processing or a chemical etching method. 如申請專利範圍第1項所述之覆銅基板裁切方法,其中,該第一經緯向識別記號與第二經緯向識別記號均為一通孔 ,該通孔之橫截面形狀為不等腰三角形。 The method for cutting a copper-clad substrate according to the first aspect of the invention, wherein the first warp and weft direction identification mark and the second warp and weft direction identification mark are one through hole. The cross-sectional shape of the through hole is an isosceles triangle. 如申請專利範圍第5項所述之覆銅基板裁切方法,其中,該不等腰三角形位於該第一電路板單元或第二電路板單元之頂角區域。 The method of cutting a copper-clad substrate according to claim 5, wherein the anisometric triangle is located at a top corner region of the first circuit board unit or the second circuit board unit. 如申請專利範圍第1項所述之覆銅基板裁切方法,其中,該第一經緯向識別記號與第二經緯向識別記號為複數通孔。 The copper-clad substrate cutting method according to the first aspect of the invention, wherein the first warp and weft direction identification mark and the second warp and weft direction identification mark are plural through holes. 如申請專利範圍第7項所述之覆銅基板裁切方法,其中,該第一經緯向識別記號包括第一識別記號與第二識別記號,該第一識別記號位於第一電路板單元一端之頂角區域,該第二識別記號位於第一電路板單元另一端之中間區域。 The method for cutting a copper-clad substrate according to claim 7, wherein the first warp and weft identification mark comprises a first identification mark and a second identification mark, wherein the first identification mark is located at one end of the first circuit board unit. In the apex area, the second identification mark is located in an intermediate portion of the other end of the first circuit board unit. 如申請專利範圍第7項所述之覆銅基板裁切方法,其中,該第二經緯向識別記號包括第三識別記號、第四識別記號與第五識別記號,該第三識別記號位於第二電路板單元一端之頂角區域,該第四識別記號與第三識別記號相對,其位於第二電路板單元另一端之頂角區域,該第五識別記號與第四識別記號於同一端,其位於該端之中間區域。 The method for cutting a copper-clad substrate according to claim 7, wherein the second warp and weft identification mark comprises a third identification mark, a fourth identification mark and a fifth identification mark, wherein the third identification mark is located in the second a vertices region at one end of the circuit board unit, the fourth identification mark being opposite to the third identification mark, located at a top corner region of the other end of the second circuit board unit, the fifth identification mark and the fourth identification mark being at the same end, Located in the middle of the end. 如申請專利範圍第9項所述之覆銅基板裁切方法,其中,該第三識別記號與該第四識別記號位於同一緯度,該第四識別記號與第五識別記號位於同一經度。 The method for cutting a copper-clad substrate according to claim 9, wherein the third identification mark and the fourth identification mark are located at the same latitude, and the fourth identification mark and the fifth identification mark are at the same longitude. 如申請專利範圍第1項所述之覆銅基板裁切方法,其中,該第一經緯向識別記號為一通孔,該通孔之橫截面形狀為不等腰三角形。 The method for cutting a copper-clad substrate according to claim 1, wherein the first warp and weft identification mark is a through hole, and the cross-sectional shape of the through hole is an isosceles triangle. 如申請專利範圍第11項所述之覆銅基板裁切方法,其中,該不等腰三角形之長邊對應該第一電路板單元之長度方向,該不等腰三角形之短邊對應該第一電路板單元之寬度方 向。 The method for cutting a copper-clad substrate according to claim 11, wherein the long side of the unequal waist triangle corresponds to the length direction of the first circuit board unit, and the short side of the unequal waist triangle corresponds to the first The width of the board unit to. 如申請專利範圍第11項所述之覆銅基板裁切方法,其中,該第二經緯向識別記號為一橫截面形狀為非不等腰三角形之通孔。 The method for cutting a copper-clad substrate according to claim 11, wherein the second warp and weft identification mark is a through hole having a cross-sectional shape that is not an isosceles triangle.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107454745A (en) * 2016-06-01 2017-12-08 全亨科技有限公司 Circuit board dividing cuts out mill method
CN107454746A (en) * 2016-06-01 2017-12-08 全亨科技有限公司 Circuit board dividing bores target and edging method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106932062A (en) * 2017-04-26 2017-07-07 马斯利自动化技术(苏州)有限公司 A kind of accurate clout supervising device and its monitoring method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI239612B (en) * 2004-05-24 2005-09-11 Phoenix Prec Technology Corp IC package substrate strips and assembly formed by the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI239612B (en) * 2004-05-24 2005-09-11 Phoenix Prec Technology Corp IC package substrate strips and assembly formed by the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107454745A (en) * 2016-06-01 2017-12-08 全亨科技有限公司 Circuit board dividing cuts out mill method
CN107454746A (en) * 2016-06-01 2017-12-08 全亨科技有限公司 Circuit board dividing bores target and edging method

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