TWI763849B - 半導體裝置及形成其的方法 - Google Patents

半導體裝置及形成其的方法

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Publication number
TWI763849B
TWI763849B TW107117119A TW107117119A TWI763849B TW I763849 B TWI763849 B TW I763849B TW 107117119 A TW107117119 A TW 107117119A TW 107117119 A TW107117119 A TW 107117119A TW I763849 B TWI763849 B TW I763849B
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Taiwan
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layer
conductive
silicon
organic
conductive layer
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TW107117119A
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English (en)
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TW201941372A (zh
Inventor
楊政龍
蘇智宏
陳承先
黃宏麟
蔡昆銘
林瑋哲
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW201941372A publication Critical patent/TW201941372A/zh
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Publication of TWI763849B publication Critical patent/TWI763849B/zh

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Abstract

本發明實施例公開半導體裝置及其形成方法。所述半導 體裝置中的一種包括第一導電層、有機層、矽層、磁性層、及第二導電層。所述有機層設置在所述第一導電層之上並暴露出所述第一導電層的一部分。所述矽層設置在所述有機層上並接觸所述有機層。所述磁性層設置在所述第一導電層之上。所述第二導電層設置在所述有機層及所述磁性層之上以電連接所述第一導電層。

Description

半導體裝置及形成其的方法
本發明實施例是有關於一種半導體裝置。
半導體裝置用於例如個人電腦、行動電話、數位照相機、及其他電子設備等各種電子應用中。半導體裝置通常是通過以下步驟來製作：在半導體基底之上依序沉積絕緣層或介電層、導電層及半導體層，並使用微影將各種材料層圖案化以在所述半導體基底上形成電路元件及元件。
通常，電感器是可將能量存儲在由從中穿過的電流形成的磁場中的被動電元件。電感器可用於各種各樣的應用中。然而，存在許多與包括電感器的半導體裝置相關的挑戰。
本發明實施例的一種半導體裝置包括第一導電層、有機層、矽層、磁性層、及第二導電層。所述有機層設置在所述第一導電層之上並暴露出所述第一導電層的一部分。所述矽層設置在 所述有機層上並接觸所述有機層。所述磁性層設置在所述第一導電層之上。所述第二導電層設置在所述有機層及所述磁性層之上以電連接所述第一導電層。
100:基底
102:電路
104:層間介電層
106:觸點
108:內連結構
110:金屬間介電層
112:金屬化特徵
114:鈍化層
116:第一導電層
116a:側壁
116b:頂表面
118、124、132:矽層
118a:底部分
120、142:介電層
120a:底部分
122、130:有機層
126、134:無機層
128:磁性層
136:第二導電層
138:通孔
140:鈍化後內連結構
144:凸塊下金屬化層
146:凸塊
OP1、OP2、OP3、OP4:開口
S10、S20、S30、S40、S50、S60、S70、S80:步驟
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1是示出根據本發明一些實施例形成半導體裝置的方法的流程圖。
圖2A至圖2E是根據一些實施例形成半導體裝置的方法的示意性剖視圖。
圖3是根據一些實施例的半導體裝置的示意圖剖視圖。
圖4是根據一些實施例的半導體裝置的示意圖剖視圖。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包 括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、從而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“位於...之下(beneath)”、“位於...下面(below)”、“下部的(lower)”、“位於...上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或其他取向)，且本文中所用的空間相對性描述語可同樣相應地進行解釋。
本發明也可包括其他特徵及製程。舉例來說，可包括測試結構，以說明對三維(3D)封裝或三維積體電路(3DIC)裝置進行驗證測試。測試結構可例如包括在重佈線層中或基底上形成並容許對三維封裝或三維積體電路進行測試的測試墊、使用探針及/或探針卡等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與包括對已知良好管芯進行中間驗證的測試方法一起使用，以提高良率並降低成本。
圖1是示出根據本發明一些實施例形成半導體裝置的方 法的流程圖。圖2A至圖2E是根據一些實施例形成半導體裝置的方法的示意性剖視圖。
參照圖1及圖2A，在步驟S10中，在第一導電層116之上形成矽層118。在一些實施例中，提供基底100。基底100是半導體基底，例如矽基底、絕緣體上矽(silicon-on-insulator，SOI)基底、矽鍺基底、或由其他適合的半導體材料形成的基底。視設計要求而定，基底100可為P型基底或N型基底，且其中可具有摻雜區。
在基底100之上形成電路102。在一些實施例中，電路102包括由介電層及電極層形成的閘極堆疊。介電層可包括介面層(interfacial layer，IL)、以及介電常數大於約4、大於約8或甚至大於約10的高介電常數(high-k)層。介電層是通過例如化學氣相沉積(chemical vapor deposition，CVD)、原子層沉積(atomic layer deposition，ALD)、物理氣相沉積(physical vapor deposition，PVD)、熱氧化、其組合等適合的技術而沉積。電極層可包括單個層或多個層(例如金屬層、襯裡層、潤濕層、黏附層、其組合等)，且可通過原子層沉積、物理氣相沉積、化學氣相沉積等而形成。
在基底100之上形成層間介電(inter-layer dielectric，ILD)層104。在一些實施例中，層間介電層104覆蓋電路102。在一些實施例中，層間介電層104包含介電常數小於約4、小於約3.5或甚至小於約3的低介電常數介電材料。低介電常數材料包括磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽酸鹽玻璃 (borophosphosilicate glass，BPSG)、氟化矽酸鹽玻璃(fluorinated silicate glass，FSG)、碳氧化矽(silicon oxycarbide，SiOxCy)、旋塗玻璃(Spin-On-Glass，SOG)、旋塗聚合物(Spin-On-Polymer，SOP)、其組合等。層間介電層104可通過例如旋塗、化學氣相沉積、或電漿增強化學氣相沉積(plasma-enhanced CVD，PECVD)等適合的方法而形成。層間介電層104可具有單層式或多層式結構。
穿過層間介電層104形成觸點106，以提供連接電路102的電觸點。在一些實施例中，通過微影與刻蝕製程在層間介電層104中形成開口。可以襯有擴散障壁層及/或黏附層(圖中未示出)以及以導電材料填充所述開口。在一些實施例中，擴散障壁層包含TaN、Ta、TiN、Ti、CoW、其組合等，且導電材料包括銅、鎢、鋁、銀、其組合等。
在基底100之上形成內連結構108。在一些實施例中，內連結構108形成在層間介電層104上。在一些實施例中，內連結構108包括一個或多個金屬間介電(inter-metal dielectric，IMD)層110及嵌入金屬間介電層110中的相關聯金屬化特徵112(例如，金屬層及通孔)。通常，所述一個或多個金屬間介電層110及相關聯金屬化特徵112用於將電路102彼此內連並用於提供外部電連接。金屬間介電層110包含介電常數小於約4、小於約3.5或甚至小於約3的低介電常數介電材料。低介電常數材料包括磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟化矽酸鹽玻璃、碳氧化矽、旋塗 玻璃、旋塗聚合物、其組合等。在一些實施例中，金屬間介電層110是通過例如旋塗、化學氣相沉積、或電漿增強化學氣相沉積等適合的方法而形成。
在一些實施例中，可在介電層中的相鄰者(例如，層間介電層104與金屬間介電層110)之間定位一個或多個絕緣刻蝕停止層(圖中未示出)。絕緣刻蝕停止層是由刻蝕選擇性與相鄰的層不同的介電材料形成。在一些實施例中，絕緣刻蝕停止層可由SiN、SiCN、SiCO、其組合等形成，且可通過例如化學氣相沉積或電漿增強化學氣相沉積等適合的方法而形成。
在基底100之上形成鈍化層114。在一些實施例中，鈍化層114形成在金屬間介電層110上。在一些實施例中，鈍化層114可由例如SiN、電漿增強氧化物(plasma-enhanced oxide，PEOX)、電漿增強SiN(plasma-enhanced SiN，PE-SiN)、電漿增強未摻雜矽酸鹽玻璃(plasma-enhanced undoped silicate glass，PE-USG)、高密度電漿(high density plasma，HDP)化學氣相沉積(CVD)氧化物、其組合等介電材料形成。形成鈍化層114是為了保護下伏層免受各種環境污染物的影響。
在鈍化層114之上形成第一導電層116。在一些實施例中，第一導電層116包含鋁、銅、或銅合金。在一些實施例中，第一導電層116可通過電鍍製程而形成。在替代實施例中，第一導電層116可包括塗布有無電鍍鎳鈀浸金(electro-less nickel electro-less palladium immersion gold，ENEPIG)的銅層，所述無 電鍍鎳鈀浸金包括鎳層、鎳層上的鈀層、及鈀層上的金層。金層可使用浸鍍而形成。在又一些替代實施例中，可使用其他導電材料來形成第一導電層116。所屬領域中的技術人員應瞭解，第一導電層116的數目及尺寸僅為實例，且第一導電層116的數目及尺寸不受本發明的實施例限制。
在一些實施例中，在第一導電層116的經暴露表面上形成矽層118。在一些實施例中，矽層118形成在第一導電層116的側壁116a及頂表面116b上並實體接觸側壁116a及頂表面116b。在一些實施例中，矽層118具有不低於40%的矽濃度。在一些實施例中，矽層118的矽濃度介於從40%至100%的範圍內。在一些實施例中，矽層118是非晶矽層。在一些實施例中，例如，矽層118是無氮層。在一些實施例中，例如，矽層118是無氧層。矽層118可通過例如化學氣相沉積或電漿增強化學氣相沉積等適合的方法而形成。沉積製程的前驅氣體包括含矽氣體，其可為矽烷氣體，例如矽烷、甲基矽烷(methyl-silane，1MS)、二甲基矽烷(di-methyl-silane，2MS)、三甲基矽烷(tri-methyl-silane，3MS)、及其組合。另外，可添加不與前驅氣體發生反應的載體氣體，其中載體氣體可包括例如氦氣、氬氣等惰性氣體。前驅氣體可包括或可不包括與含矽氣體發生反應的其他氣體。在一些實施例中，例如，用於形成矽層118的前驅氣體包括矽烷，且載體氣體包括氬氣。例如，矽層118可為實質上共形層，其中在第一導電層116的側壁116a上矽層118的厚度與頂表面116b上矽層118的厚度彼 此接近。在一些實施例中，矽層118的厚度可大於500埃。在一些實施例中，矽層118的厚度可小於約1μm。矽層118可具有單層式或多層式結構。
在一些實施例中，在矽層118之上形成介電層120。在一些實施例中，介電層120實體接觸矽層118。在一些實施例中，介電層120包含例如SiN、SiC、SiCN、SiCO、SiON、SiOx、氮化物-氧化物-氮化物(NON)、氧化物-氮化物-氧化物(ONO)、或其組合等無機材料，且可通過例如化學氣相沉積或電漿增強化學氣相沉積等適合的方法而形成。介電層120可具有單層式或多層式結構。例如，介電層120的厚度可介於從約2000埃至2.5μm的範圍內。
在一些實施例中，矽層118的材料層(圖中未示出)及介電層120的材料層(圖中未示出)是依序毯覆式(blanket)形成在第一導電層116及鈍化層114上，且矽層118的材料層與介電層120的材料層是通過使用同一罩幕被圖案化以形成介電層120及矽層118。因此，如圖2A中所示，例如，矽層118的底部分118a位於介電層120的底部分120a下面。
參照圖1及圖2A，在步驟S20中，在矽層118之上形成有機層122，其中矽層118設置在有機層122與第一導電層116之間。在一些實施例中，有機層122是形成在基底100之上以覆蓋第一導電層116，且填充在第一導電層116之間的開口中。在一些實施例中，有機層122是設置在第一導電層116的側壁116a及頂 表面116b之上的介電層120上，並實體接觸介電層120。在一些實施例中，有機層122可由含有碳及氧的聚合物(例如，環氧樹脂、聚醯亞胺、苯環丁烷(benzocyclobutene，BCB)、聚苯並惡唑(polybenzoxazole，PBO)等)形成。例如，有機層122的厚度大於30μm。有機層122可具有單層式或多層式結構。有機層122可通過例如旋轉塗布、積層(lamination)、沉積等適合的方法而形成。在一些實施例中，由於有機層122與第一導電層116之間形成有矽層118，因此有機層122與第一導電層116的黏附性得以改善。因此，有機層122從第一導電層116的脫層得以預防，且半導體裝置的可靠性得以改善。
參照圖2B，在矽層118、介電層120、及有機層122中形成開口OP1，以暴露出第一導電層116的一部分。在一些實施例中，開口OP1是通過微影與刻蝕製程而形成。刻蝕製程可為濕刻蝕製程或乾刻蝕製程。
參照圖1及圖2B，在步驟S30中，在有機層122之上依序形成矽層124及無機層126，其中矽層124設置在有機層122與無機層126之間。在一些實施例中，例如，矽層124是毯覆式形成在有機層122上，且無機層126是毯覆式形成在所述矽層上。在一些實施例中，在形成矽層124之前，可對有機層122的經暴露表面執行電漿處理。例如，電漿處理是氬電漿處理。在一些實施例中，例如，通過進行電漿處理，有機層122的富碳表面可改變成富氧表面。在一些實施例中，矽層124形成在有機層122的 經改質表面上。在一些實施例中，例如，可在矽層124的表面處的矽原子與有機層122的經改質表面處的氧原子之間形成Si-O鍵。另外，可在矽層124與有機層122之間形成Si-Si鍵及/或Si-H鍵。在一些實施例中，可通過使用矽烷作為前驅氣體並使用氬氣作為載體氣體來沉積矽層124。在使用氬氣作為載體氣體的情況中，可省略電漿處理，因為氬氣起到電漿處理的作用。矽層124的材料及形成方法可類似於矽層118的材料及形成方法，且本文中已反復說明了細節。在一些實施例中，矽層118的材料與矽層124的材料可為相同或不同的。矽層118的矽濃度與矽層124的矽濃度可為相同或不同的。
在矽層124上形成無機層126。在一些實施例中，無機層126包含SiN、SiC、SiCN、SiCO、SiON、SiOx、氮化物-氧化物-氮化物(NON)、氧化物-氮化物-氧化物(ONO)、或其組合等，且可通過例如化學氣相沉積或電漿增強化學氣相沉積等適合的方法而形成。無機層126可具有單層式或多層式結構。例如，無機層126的厚度介於從約2000埃至2.5μm的範圍內。在一些實施例中，例如，可在矽層124與含有氮化物及/或氧化物的無機層126之間形成例如Si-N鍵及/或Si-O鍵等共價鍵。
在一些實施例中，當在有機層122上形成矽層124時，會在矽層124與有機層122之間形成例如Si-O鍵、Si-Si鍵及/或Si-H鍵等共價鍵。例如，當在矽層124上沉積含有氮化物及/或氧化物的無機層126時，可在矽層124與無機層126之間形成例如 Si-N鍵及/或Si-O鍵等共價鍵。在一些實施例中，通過在有機層122與無機層126之間並與有機層122及無機層126實體接觸地插入矽層124，會在矽層124與有機層122之間以及矽層124與無機層126之間形成共價鍵而非氫鍵。因此，無機層126通過被夾置的矽層124黏附到有機層122，且無機層126與有機層122之間的黏附性得以改善。在一些實施例中，當在微觀尺度上觀看時，矽層124與有機層122之間或矽層124與無機層126之間的介面是平滑的，且介面處表明發生脫層的毛刺(burr)顯著減少。另外，矽層124設置在第一導電層116與無機層126之間，且因此無機層126不接觸第一導電層116。因此，無機層126從第一導電層116的脫層得以預防。
參照圖2C，在矽層124及無機層126中形成開口OP2，以暴露出第一導電層116。在一些實施例中，開口OP2是通過使用同一罩幕將矽層124及無機層126圖案化而形成。也就是說，開口OP2是通過微影與刻蝕製程而形成。在一些實施例中，開口OP2設置在開口OP1中。
參照圖1及圖2C，在步驟S40中，在第一導電層116之上形成磁性層128。在一些實施例中，磁性層128是形成在第一導電層116之上的無機層126上。在一些實施例中，磁性層128包含含有鈷(cobalt，Co)、鋯(zirconium，Zr)、鉭(tantalum，Ta)、鈮(niobium，Nb)、錸(rhenium，Re)、釹(neodymium，Nd)、鐠(praseodymium，Pr)、鏑(dysprosium，Dy)、或其組合的磁性 金屬材料。在一些實施例中，磁性層128包含非晶鈷(Co)合金，所述非晶鈷(Co)合金包含鈷(Co)及鋯(Zr)。鋯(Zr)有助於使鈷(Co)成為非晶態的。在一些實施例中，磁性層128包含具有一種或多種額外元素(例如鉭(Ta)及鈮(Nb))的鈷-鋯(CoZr)合金。在一些其他實施例中，磁性層128包含具有例如稀土元素等一種或多種額外元素的鈷-鋯(CoZr)合金，所述稀土元素有助於提高鈷-鋯(CoZr)合金的鐵磁共振性。稀土元素包括錸(Re)、釹(Nd)、鐠(Pr)、或鏑(Dy)。在一些實施例中，磁性層128包含CoZrTa、CoZr、CoZrRe、NiFe、或其組合。磁性層128可通過例如物理氣相沉積、化學氣相沉積等適合的方法而形成。
參照圖1及圖2D，在步驟S50中，在磁性層128之上形成有機層130。在一些實施例中，有機層130形成在無機層126上以覆蓋磁性層128。有機層130的材料及形成方法可類似於有機層122的材料及形成方法，且本文中已反復說明了細節。在一些實施例中，有機層122的材料與有機層130的材料可為相同或不同的。在有機層130中形成開口OP3以暴露出第一導電層116，且開口OP3設置在開口OP2中。開口OP3是通過微影與刻蝕製程而形成。
參照圖1及圖2D，在步驟S60中，在有機層130之上依序形成矽層132及無機層134，其中矽層132設置在有機層130與無機層134之間。在一些實施例中，矽層132形成在有機層130上，且無機層134形成在矽層132上。矽層132及無機層134包 括開口OP4，以暴露出第一導電層116的一部分。開口OP4是通過微影與刻蝕製程而形成，且開口OP4設置在開口OP3中。矽層132及無機層134的材料及形成方法可類似於矽層124及無機層126的材料及形成方法，且本文中已反復說明了細節。在一些實施例中，矽層132的材料與矽層118、124的材料可為相同或不同的。在一些實施例中，無機層134的材料與無機層126的材料可為相同或不同的。在一些實施例中，當在有機層130上形成矽層132時，可在有機層130與矽層132之間形成例如Si-O鍵、Si-Si鍵及/或Si-H鍵等共價鍵。另外，例如，當在矽層132上沉積含有氮化物及/或氧化物的無機層134時，可在矽層132與無機層134之間形成例如Si-N鍵及/或Si-O鍵等共價鍵。在一些實施例中，通過在有機層130與無機層134之間並與有機層130及無機層134實體接觸地插入矽層132，會在矽層132與有機層130之間以及矽層132與無機層134之間形成共價鍵而非氫鍵。因此，無機層134通過被夾置的矽層132黏附到有機層130，且無機層134與有機層130之間的黏附性得以改善。另外，矽層132設置在第一導電層116與無機層134之間，且因此無機層134不接觸第一導電層116。因此，無機層134從第一導電層116的脫層得以預防。
參照圖1及圖2E，在步驟S70中，在有機層130之上形成第二導電層136，以電連接第一導電層116。在一些實施例中，第二導電層136形成在無機層134上。在一些實施例中，將導電材料填充到開口OP4中，以在開口OP4中形成通孔138並在通孔 138上形成第二導電層136。在一些實施例中，第二導電層136通過通孔138電連接到第一導電層116。通孔138及第二導電層136包含鋁、銅、或銅合金。在一些實施例中，第二導電層136可通過電鍍製程而形成。在替代實施例中，通孔138及第二導電層136可包括塗布有無電鍍鎳鈀浸金(ENEPIG)的銅層，所述無電鍍鎳鈀浸金包括鎳層、鎳層上的鈀層、及鈀層上的金層。金層可使用浸鍍而形成。在又一些替代實施例中，可使用其他導電材料來形成通孔138及第二導電層136。所屬領域中的技術人員應瞭解，通孔138的數目及尺寸僅為實例，且通孔138的數目及尺寸不受本發明的實施例限制。類似地，雖然第二導電層136電連接到兩個第一導電層116，然而本發明並非僅限於此。在一些替代實施例中，第二導電層136可電連接到一個或多於兩個第一導電層116。
在一些實施例中，第一導電層116、第二導電層136及其之間的通孔138在磁性層128之上形成鈍化後內連(post-passivation interconnect，PPI)結構140。磁性層128通過有機層130、矽層132、及無機層134與鈍化後內連結構140絕緣。在一些實施例中，例如，鈍化後內連結構140是螺旋形的，且磁性層128設置在螺旋的中心區中。在一些實施例中，例如，第二導電層136可被形成為螺旋結構的端部處的連接墊。在一些實施例中，例如，鈍化後內連結構140與磁性層128形成磁性電感器結構。
在一些實施例中，在無機層134上形成介電層142，以包 封第二導電層136。在一些實施例中，介電層142可由例如環氧樹脂、聚醯亞胺、苯環丁烷(BCB)、聚苯並惡唑(PBO)等聚合物形成。介電層142可通過例如旋轉塗布、積層、沉積等適合的方法而形成。
參照圖1及圖2E，在步驟S80中，形成凸塊下金屬化(under bump metallization，UBM)層144及凸塊146，以電連接第二導電層136。在一些實施例中，凸塊下金屬化層144形成在介電層142中及介電層142上以電連接到第二導電層136。在一些實施例中，凸塊下金屬化層144包含銅、鎳、鈦、其組合等，且是通過電鍍製程而形成。接著，凸塊146形成在凸塊下金屬化層144之上並電連接到凸塊下金屬化層144。在一些實施例中，凸塊146包含具有低電阻率的導電材料(例如Sn、Pb、Ag、Cu、Ni、Bi、或其合金)，且可通過例如蒸鍍、鍍覆、滴球、或網版印刷等適合的製程而形成。因此，包括磁性電感器結構及凸塊146的半導體結構完成。在一些實施例中，磁性電感器結構與封裝結構形成在同一區中，但本發明並非僅限於此。在一些替代實施例中，基底100可具有第一區域及與第一區域相鄰的第二區域，第一區域是其中形成有磁性電感器結構的區域，且第二區域是被配置成將半導體裝置結合到專用積體電路(application specific integrated circuit，ASIC)的封裝區域。
在一些實施例中，如圖2A中所示，矽層118與介電層120是通過同一圖案化製程而形成，但本發明並非僅限於此。在一 些替代實施例中，如圖3中所示，矽層118與介電層120可通過不同的圖案化製程而形成。也就是說，在第一導電層116及鈍化層114上毯覆式形成矽層118的材料層(圖中未示出)並通過使用第一罩幕將其圖案化以形成矽層118。接著，在矽層118及鈍化層114上毯覆式形成介電層120的材料層(圖中未示出)並通過使用與第一罩幕不同的第二罩幕將其圖案化以形成介電層120。因此，如圖3中所示，整個矽層118位於介電層120內，且介電層120覆蓋矽層118的整個經暴露表面。因此，例如，矽層118未被暴露出。另外，在一些替代實施例中，如圖4中所示，可省略介電層120，也就是說，有機層122是形成在矽層118上並實體接觸矽層118，且有機層122與第一導電層116的黏附性也得以改善。
在一些實施例中，半導體裝置包括第一導電層116、磁性層128、第二導電層136、有機層122、130、無機層126、134、及位於有機層122、130與無機層126、134之間的矽層124、132。在一些實施例中，有機層122可設置在第一導電層116與磁性層128之間。在一些實施例中，有機層130可設置在第二導電層136與磁性層128之間。由於無機層126、134是通過矽層124、132黏附到有機層122、130，因此無機層126、134與有機層122、130的黏附性得以改善。因此，無機層126、134從有機層122、130的脫層得以預防，且半導體裝置的可靠性得以改善。另外，在一些實施例中，第一導電層116與有機層122之間形成有矽層118，且因此有機層122與第一導電層116的黏附性得以改善。因此， 有機層122從第一導電層116的脫層得以預防，且半導體裝置的可靠性得以改善。在一些實施例中，例如，矽層124、132分別形成在有機層122、130與無機層126、134之間。在一些替代實施例中，可省略所述矽層中的一者，也就是說，可根據要求來確定在有機層與無機層之間插入矽層。
傳統上，在包括磁性電感器結構的半導體裝置中，高形貌結構及因此高膜應力會在有機層與無機層之間或有機層與導電層之間引發嚴重脫層及不良黏附性。在一些實施例中，通過在有機層與無機層之間插入矽層，會在矽層與有機層之間以及矽層與無機層之間形成共價鍵而非氫鍵。因此，有機層與無機層的黏附性得以改善。另外，有機層與導電層之間的矽層會改善有機層與導電層之間的黏附性。因此，有機層從無機層或導電層的脫層得以減少，且半導體裝置的可靠性得以提高。
根據本發明的一些實施例，一種半導體裝置包括第一導電層、有機層、矽層、磁性層、及第二導電層。所述有機層設置在所述第一導電層之上並暴露出所述第一導電層的一部分。所述矽層設置在所述有機層上並接觸所述有機層。所述磁性層設置在所述第一導電層之上。所述第二導電層設置在所述有機層及所述磁性層之上以電連接所述第一導電層。
根據本發明的一些實施例，所述矽層是非晶矽層。
根據本發明的一些實施例，所述半導體裝置進一步包括無機層，其中所述矽層設置在所述有機層與所述無機層之間，且 所述無機層不接觸所述第一導電層。
根據本發明的一些實施例，所述矽層接觸所述無機層。
根據本發明的一些實施例，所述有機層設置在所述第一導電層與所述磁性層之間。
根據本發明的一些實施例，所述有機層設置在所述第二導電層與所述磁性層之間。
根據本發明的一些實施例，所述半導體裝置進一步包括設置在所述第二導電層之上並電連接所述第二導電層的凸塊。
根據本發明的替代實施例，一種半導體裝置包括第一導電層、有機層、矽層、及磁性層。所述有機層設置在所述第一導電層旁邊。所述矽層設置在所述有機層與所述第一導電層之間。所述磁性層設置在所述第一導電層之上。
根據本發明的一些實施例，所述矽層是非晶矽層。
根據本發明的一些實施例，所述矽層接觸所述第一導電層及所述有機層。
根據本發明的一些實施例，所述半導體裝置進一步包括設置在所述有機層與所述矽層之間的介電層，且所述介電層不接觸所述第一導電層。
根據本發明的一些實施例，所述介電層是無機層。
根據本發明的一些實施例，所述矽層設置在所述第一導電層的側壁及頂表面上並接觸所述側壁及所述頂表面。
根據本發明的一些實施例，所述半導體裝置進一步包括 電連接所述第一導電層的凸塊。
根據本發明的又一些替代實施例，一種形成半導體裝置的方法包括至少以下步驟。在第一導電層之上形成有機層，其中所述第一導電層的一部分被暴露出。在所述有機層上形成矽層，其中所述矽層接觸所述有機層。在所述第一導電層之上形成磁性層。在所述有機層及所述磁性層之上形成第二導電層，以電連接所述第一導電層。
根據本發明的一些實施例，所述矽層是通過電漿增強化學氣相沉積(PECVD)而形成。
根據本發明的一些實施例，所述方法進一步包括在形成所述矽層之前對所述有機層執行電漿處理。
根據本發明的一些實施例，所述方法進一步包括在所述矽層上形成無機層，其中所述矽層設置在所述有機層與所述無機層之間。
根據本發明的一些實施例，述有機層形成在所述第一導電層與所述磁性層之間。
根據本發明的一些實施例，所述有機層形成在所述第二導電層與所述磁性層之間。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應知，他們可容易地使用本公開作為設計或修改其他過程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文 中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、替代及變更。
100:基底
102:電路
104:層間介電層
106:觸點
108:內連結構
110:金屬間介電層
112:金屬化特徵
114:鈍化層
116:第一導電層
118、124、132:矽層
118a:底部分
120、142:介電層
120a:底部分
122、130:有機層
126、134:無機層
128:磁性層
136:第二導電層
138:通孔
140:鈍化後內連結構
144:凸塊下金屬化層
146:凸塊

Claims (10)

  1. 一種半導體裝置，包括：第一導電層，包括第一表面；有機層，設置在所述第一導電層的所述第一表面之上；矽層，設置在所述有機層上並接觸所述有機層，且延伸到所述第一導電層的所述第一表面上並接觸所述第一導電層的所述第一表面；磁性層，設置在所述第一導電層之上；以及第二導電層，設置在所述有機層及所述磁性層之上以電連接所述第一導電層。
  2. 如請求項1所述的半導體裝置，進一步包括非導電性無機層，其中所述矽層設置在所述有機層與所述非導電性無機層之間，且所述非導電性無機層不接觸所述第一導電層。
  3. 如請求項1所述的半導體裝置，其中所述有機層包括第二表面及位於所述第一導電層的所述第一表面與所述第二表面之間的側壁表面，且所述矽層位於所述第二表面、所述側壁表面以及所述第一表面上。
  4. 一種半導體裝置，包括：第一導電層；有機層與非導電性無機層，設置在所述第一導電層之上；矽層，設置在所述有機層及所述非導電性無機層之間且與所述有機層及所述非導電性無機層接觸，其中所述有機層位於所述矽層與所述第一導電層之間；以及磁性層，設置在所述第一導電層之上。
  5. 一種形成半導體裝置的方法，包括：在第一導電層之上形成有機層，其中所述第一導電層的第一表面被暴露出；在所述有機層上形成矽層，其中所述矽層接觸所述有機層且所述矽層延伸到所述第一導電層的所述第一表面上並接觸所述第一導電層的所述第一表面；在所述第一導電層之上形成磁性層；以及在所述有機層及所述磁性層之上形成第二導電層，以電連接所述第一導電層。
  6. 一種半導體裝置，包括：第一導電層，包括第一表面；有機層，設置在所述第一導電層的所述第一表面之上；以及矽層，設置在所述有機層上，且延伸到所述第一導電層的所述第一表面上並接觸所述第一導電層的所述第一表面。
  7. 如請求項6所述的半導體裝置，進一步包括具有第二表面的第二導電層，其中所述矽層在所述第一導電層的所述第一表面、所述第一導電層與所述第二導電層之間的所述有機層的表面以及所述第二導電層的所述第二表面上連續地延伸。
  8. 一種半導體裝置，包括：第一導電層；有機層與非導電性無機層，設置在所述第一導電層之上；以及矽層，設置在所述有機層及所述非導電性無機層之間，其中所述有機層位於所述矽層與所述第一導電層之間。
  9. 如請求項8所述的半導體裝置，其中所述矽層直接接觸所述有機層及所述非導電性無機層。
  10. 一種半導體裝置，包括：第一導電層；第一有機層、第一非導電性無機層以及位於所述第一有機層與第一非導電性無機層之間的第一矽層，設置在所述第一導電層之上；以及第二有機層、第二非導電性無機層以及位於所述第二有機層與第二非導電性無機層之間的第二矽層，設置在所述第一導電層之上，其中所述第一矽層及所述第二矽層直接接觸所述第一導電層。
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