TWI763114B - 製作半導體結構的方法 - Google Patents

製作半導體結構的方法 Download PDF

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TWI763114B
TWI763114B TW109139047A TW109139047A TWI763114B TW I763114 B TWI763114 B TW I763114B TW 109139047 A TW109139047 A TW 109139047A TW 109139047 A TW109139047 A TW 109139047A TW I763114 B TWI763114 B TW I763114B
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dielectric layer
plasma
shallow trench
trench isolation
pit
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TW202203316A (zh
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賴振益
吳俊亨
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南亞科技股份有限公司
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Abstract

一種製作半導體結構的方法包括以下操作。接收埋設有淺溝槽隔離區的基板。形成第一介電層於基板上。執行蝕刻製程以在第一介電層中形成孔洞，並在基板中形成凹坑，其中淺溝槽隔離區的上表面從孔洞暴露出來，且凹坑與淺溝槽隔離區相鄰。形成第二介電層於第一介電層和淺溝槽隔離區上，以及凹坑中。以電漿處理第二介電層，以將實質上位於第一介電層及淺溝槽隔離區上的第二介電層的第一部分，轉變為電漿處理層。移除電漿處理層，以留下位於第二介電層的第二部分於凹坑中。

Description

製作半導體結構的方法
本揭示內容是關於一種製作半導體結構的方法。
半導體積體電路（integrated circuit, IC）行業經歷了快速的發展，並一直致力於提高裝置密度、提高性能和降低成本。 但是，當前已面臨涉及製造和設計的問題。舉例來說，在蝕刻製程期間，可能會發生過度蝕刻(over-etching)，從而可能引起一些問題，例如不期望的漏電流、不期望的電子元件之間的導通或降低裝置的可靠性。
有鑑於此，需要開發一種新方法以防止在蝕刻製程中出現上述問題。
本揭示內容提供一種製作半導體結構的方法。方法包括以下操作。接收埋設有淺溝槽隔離區的基板。形成第一介電層於基板上。執行蝕刻製程以在第一介電層中形成孔洞，並在基板中形成凹坑，其中淺溝槽隔離區的上表面從孔洞暴露出來，且凹坑與淺溝槽隔離區相鄰。形成第二介電層於第一介電層和淺溝槽隔離區上，以及凹坑中。以電漿處理第二介電層，以將實質上位於第一介電層及淺溝槽隔離區上的第二介電層的第一部分，轉變為電漿處理層。移除電漿處理層，以留下位於第二介電層的第二部分於凹坑中。
在一些實施方式中，以電漿處理第二介電層包括氧化第二介電層的第一部份，或還原第二介電層的第一部份。
在一些實施方式中，第二介電層的材料與基板的材料相同。
在一些實施方式中，第二介電層包括選自由矽、氮化矽和二氧化矽所組成的群組的材料。
在一些實施方式中，當第二介電層包括矽，電漿為氧氣電漿。
在一些實施方式中，當第二介電層包括氮化矽，電漿為氧氣電漿。
在一些實施方式中，當第二介電層包括二氧化矽，電漿為氫氣電漿。
在一些實施方式中，第二介電層具有實質上均勻的厚度。
在一些實施方式中，第二介電層係由化學氣相沉積、物理氣相沉積、或原子層沉積形成。
在一些實施方式中，電漿處理層係由蝕刻製程移除。
應該理解的是，前述的一般性描述和下列具體說明僅僅是示例性和解釋性的，並旨在提供所要求的本發明的進一步說明。
為了使本揭示內容之敘述更加詳盡與完備，可參照所附之圖式及以下所述各種實施例，圖式中相同之號碼代表相同或相似之元件。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
本揭示內容提供一種製造半導體結構的方法。 第1圖是根據本揭示內容的一些示例性實施方式的用於製造半導體結構的方法100的流程圖。此方法的操作110為接收埋設有淺溝槽隔離區的基板。此方法繼續進行操作120，形成第一介電層於基板上。操作130，進行蝕刻製程，以在第一介電層中形成孔洞，並在基板中形成凹坑，其中淺溝槽隔離區的上表面從孔洞暴露出來，且凹坑與淺溝槽隔離區相鄰。此方法繼續進行操作140，形成第二介電層於第一介電層和淺溝槽隔離區上，以及凹坑中。方法繼續進行操作150，以電漿處理第二介電層，以將實質上位於第一介電層及淺溝槽隔離區上的第二介電層的第一部分，轉變為電漿處理層。操作160，移除電漿處理層，以留下位於第二介電層的第二部分於凹坑中。為了更好地理解本揭示內容的概念，而簡化了第1圖。因此，應當注意，可以在第1圖的方法之前、期間和之後提供額外的製程，這裡僅簡要地描述一些其他製程。
第2至8圖是根據本揭示內容的一些示例性實施方式的在製造半導體結構中的中間階段的剖面圖。
參考第2圖。接收埋設有淺溝槽隔離區(shallow trench isolation, STI)220的基板210(第1圖的操作110)。在一些實施方式中，基板210是巨塊半導體(bulk semiconductor)、絕緣體上半導體（semiconductor-on-insulator, SOI）基板等等。 例如，基板210可以是晶圓，例如矽晶圓。通常，SOI基板包括絕緣層和在其上的半導體材料層。例如，絕緣層可以是埋藏氧化物(buried oxide, BOX)層、氧化矽層等等。絕緣層設置在基板、矽或玻璃基板上。也可以使用其他基板，例如多層或梯度(gradient)基板。在一些實施方式中，基板210的半導體材料可以包括矽；鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或其組合。
仍參照第2圖。在一些實施方式中，淺溝槽隔離區220由氧化矽、氮化矽、氧氮化矽、摻雜氟的矽酸鹽玻璃(fluoride-doped silicate glass, FSG)或其他低K介電材料製成。在一些實施方式中，淺溝槽隔離區220可由高密度電漿化學氣相沉積製程形成，以矽烷(SiH 4)和氧氣(O 2)作为反應前驅物。 在其他實施方式中，可以使用低於大氣壓的CVD(sub-atmospheric CVD, SACVD)製程或高縱橫比製程(high aspect-ratio process, HARP)形成淺溝槽隔離區220，其中製程氣體可以包括原矽酸四乙酯(tetraethylorthosilicate, TEOS)和臭氧(O 3)。 在其他實施方式中，淺溝槽隔離區220可以使用旋塗介電質(spin-on-dielectric, SOD)製程形成，例如含氫矽氧烷(hydrogen silsesquioxane, HSQ)或甲基矽氧烷(methyl silsesquioxane, MSQ)。亦可以使用其他製程和材料。
請參照第3圖。在基板210上形成第一介電層310(第1圖的操作120)。在一些實施方式中，可以在第一介電層310(第3圖中未示出)中形成一些電子元件，例如場效電晶體(field-effect transistor, FET)。在此將不描述電子元件的製造過程。 在一些實施方式中，第一介電層310包括一層或多層包含矽與O、N、C、B和/或H的矽基絕緣材料，或包含鋁與O、N、C、B和/或H的鋁基絕緣材料的一層或多層。第一介電層310的範例包括SiN、SiCN、SiC、SiCON、AlO x、AlN x和AlN xO y。
參考第4圖。執行蝕刻製程以在第一介電層310中形成孔洞H1並在基板210中形成凹坑H2，其中淺溝槽隔離區220的上表面S從孔洞H1暴露出來，且凹坑H2與淺溝槽隔離區220相鄰(第1圖的操作130)。更具體地說，在蝕刻製程期間，蝕刻劑不僅蝕刻第一介電層310，而且部分蝕刻基板210的表面以形成凹坑H2。換句話說，凹坑H2是由過度蝕刻造成的。凹坑H2是缺陷，並且可能引起例如不期望的漏電流、不期望的電子元件之間的導通或降低裝置的可靠性的問題。以下第5-8圖說明如何填滿凹坑H2。
現在請注意第5圖。在第一介電層310和淺溝槽隔離區220上，以及凹坑H2中形成第二介電層510(第1圖的操作140)。因此，凹坑H2填充有第二介電層510。如第5圖所示，第二介電層510具有部分512和部分514。部分512實質上設置在第一介電層310和淺溝槽隔離區220上。部分514設置在凹坑H2中。在一些實施方式中，第二介電層510具有實質上均勻的厚度。換句話說，第二介電層510實質上共形地覆蓋第一介電層310、淺溝槽隔離區220和基板210。在一些實施方式中，第二介電層510藉由化學氣相沉積(chemical vapor deposition, CVD)、物理氣相沉積(physical vapor deposition, PVD)或原子層沉積(atomic layer deposition ALD)形成。在一些實施方式中，第二介電層510的材料與基板210的材料相同。在一些實施方式中，第二介電層510是氧化物層或氮化物層。在一些實施方式中，第二介電層510包括選自由矽、氮化矽和二氧化矽所組成的群組的材料。
參考第6至7圖。以電漿P處理如第6圖所示的第二介電層510，以將實質上位於第一介電層310及淺溝槽隔離區220上的第二介電層510的一部分，轉變為如第7圖所示的電漿處理層512A(第1圖的操作150)。換句話說，以電漿P處理第二介電層510的表面部分。在一些實施方式中，以電漿P處理第二介電層510包括氧化第二介電層510的一部份，或還原第二介電層510的一部份。舉例來說，第二介電層510可被氧氣電漿氧化，或被氫氣電漿還原。換句話說，在一些實施方式中，電漿P為氧氣電漿或氫氣電漿。
在一些實施方式中，當第二介電層510包括矽，電漿P是氧氣電漿。矽被氧氣電漿氧化為二氧化矽，因此，電漿處理層512A包括二氧化矽。在一些實施方式中，當第二介電層510包括氮化矽，電漿P是氧氣電漿。氮化矽被氧氣電漿氧化為氮氧化矽，因此，電漿處理層512A包括氮氧化矽。在一些實施方式中，當第二介電層510包括二氧化矽，電漿P是氫氣電漿。二氧化矽被還原為矽，因此電漿處理層512A包括矽。
現在請參第8圖。移除電漿處理層512A，以留下第二介電層510的部分514於凹坑H2中(第1圖的操作160)。因此，如第8圖所示，形成半導體結構。在一些實施方式中，第二介電層510的部分514的上表面實質上對齊淺溝槽隔離區220的上表面。換句話說，第二介電層510的部分514的上表面實質上與淺溝槽隔離區220的上表面共平面。如第8圖所示，基板210中的凹坑H2被第二介電層510填滿，故可避免先前所提到的問題，例如：不期望的漏電流、不期望的電子元件之間的導通或降低裝置的可靠性。
在一些實施方式中，藉由蝕刻製程移除電漿處理層512A。在一些實施方式中，電漿處理層512A包括矽，可以藉由使用NH 4OH、HNO 3+HF或HNO 3+HF+CH 3COOH作為蝕刻劑來蝕刻矽。在一些實施方式中，電漿處理層512A包括氮氧化矽，可以藉由使用H 3PO 4作為蝕刻劑來蝕刻氮氧化矽。在一些實施方式中，電漿處理層512A包括二氧化矽，可以藉由使用HF、HF+NH 4F或NH 4F+H 3PO 4作為蝕刻劑來蝕刻二氧化矽。
儘管已經參考某些實施方式相當詳細地描述了本發明，但是亦可能有其他實施方式。因此，所附申請專利範圍的精神和範圍不應限於此處包含的實施方式的描述。
對於所屬技術領域人員來說，顯而易見的是，在不脫離本發明的範圍或精神的情況下，可以對本發明的結構進行各種修改和變化。鑑於前述內容，本發明意圖涵蓋落入所附權利要求範圍內的本發明的修改和變化。
100 : 方法 110、120、130、140、150、160 : 操作 210 : 基板 220 : 淺溝槽隔離區 310 : 第一介電層 H1 : 孔洞 H2 : 凹坑 P : 電漿 S : 上表面 510 : 第二介電層 512、514 : 部分 512A : 電漿處理層
本揭示內容上述和其他態樣、特徵及其他優點參照說明書內容並配合附加圖式得到更清楚的瞭解，其中： 第1圖是根據本揭示內容的一些示例性實施方式的用於製造半導體結構的方法的流程圖。 第2至8圖是根據本揭示內容的一些示例性實施方式的在製造半導體結構中的中間階段的剖面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
210 : 基板 220 : 淺溝槽隔離區 310 : 第一介電層 H1 : 孔洞 H2 : 凹坑 514 : 部分

Claims (9)

  1. 一種製作半導體結構的方法，包括：接收埋設有一淺溝槽隔離區的一基板；形成一第一介電層於該基板上；執行一蝕刻製程以在該第一介電層中形成一孔洞，並在該基板中形成一凹坑，其中該淺溝槽隔離區的一上表面從該孔洞暴露出來，且該凹坑與該淺溝槽隔離區相鄰；形成一第二介電層於該第一介電層和該淺溝槽隔離區上，以及該凹坑中；以一電漿處理該第二介電層，包括：氧化或還原實質上位於該第一介電層及該淺溝槽隔離區上的該第二介電層的一第一部分，以轉變為一電漿處理層；以及移除該電漿處理層，以留下該第二介電層的一第二部分於該凹坑中。
  2. 如請求項1所述的方法，其中該第二介電層的材料與該基板的材料相同。
  3. 如請求項1所述的方法，其中該第二介電層包括選自由矽、氮化矽和二氧化矽所組成的群組的材料。
  4. 如請求項3所述的方法，其中當該第二介電層包括矽，該電漿為一氧氣電漿。
  5. 如請求項3所述的方法，其中當該第二介電層包括氮化矽，該電漿為一氧氣電漿。
  6. 如請求項3所述的方法，其中當該第二介電層包括二氧化矽，該電漿為一氫氣電漿。
  7. 如請求項1所述的方法，其中該第二介電層具有實質上均勻的一厚度。
  8. 如請求項1所述的方法，其中該第二介電層係由化學氣相沉積、物理氣相沉積、或原子層沉積形成。
  9. 如請求項1所述的方法，其中該電漿處理層係由一蝕刻製程移除。
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