TWI762448B - 時鐘管理電路、以及含有該時鐘管理電路的積體電路 - Google Patents
時鐘管理電路、以及含有該時鐘管理電路的積體電路 Download PDFInfo
- Publication number
- TWI762448B TWI762448B TW105124727A TW105124727A TWI762448B TW I762448 B TWI762448 B TW I762448B TW 105124727 A TW105124727 A TW 105124727A TW 105124727 A TW105124727 A TW 105124727A TW I762448 B TWI762448 B TW I762448B
- Authority
- TW
- Taiwan
- Prior art keywords
- clock
- circuit
- processor
- period
- timer
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microcomputers (AREA)
- Advance Control (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2015-0111210 | 2015-08-06 | ||
KR1020150111210A KR102476357B1 (ko) | 2015-08-06 | 2015-08-06 | 클럭 관리 유닛과 이를 적용하는 집적 회로 및 시스템 온 칩 및 그 동작 방법 |
US15/185,505 | 2016-06-17 | ||
US15/185,505 US10983551B2 (en) | 2015-08-06 | 2016-06-17 | Clock management unit, integrated circuit including the clock management unit, system on chip, and method of operating the system on chip |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201712464A TW201712464A (zh) | 2017-04-01 |
TWI762448B true TWI762448B (zh) | 2022-05-01 |
Family
ID=58053825
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105124727A TWI762448B (zh) | 2015-08-06 | 2016-08-04 | 時鐘管理電路、以及含有該時鐘管理電路的積體電路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10983551B2 (ko) |
KR (1) | KR102476357B1 (ko) |
CN (1) | CN106444965B (ko) |
TW (1) | TWI762448B (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105718320B (zh) * | 2016-01-18 | 2020-11-06 | 华为技术有限公司 | 一种时钟任务处理方法、装置及设备 |
US11099602B2 (en) * | 2019-04-30 | 2021-08-24 | International Business Machines Corporation | Fault-tolerant clock gating |
JP7422066B2 (ja) * | 2020-12-28 | 2024-01-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW544680B (en) * | 2000-08-04 | 2003-08-01 | Nec Electronics Corp | Timer circuit and semiconductor memory device integrated with the timer circuit |
TW200739581A (en) * | 2005-09-28 | 2007-10-16 | Hynix Semiconductor Inc | Delay locked operation in semiconductor memory device |
CN103116384A (zh) * | 2013-02-01 | 2013-05-22 | 山东华芯半导体有限公司 | 一种SoC系统时钟控制的方法和SoC |
US20140125381A1 (en) * | 2012-11-05 | 2014-05-08 | Advanced Micro Devices, Inc. | Voltage-aware signal path synchronization |
Family Cites Families (26)
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US6343363B1 (en) | 1994-09-22 | 2002-01-29 | National Semiconductor Corporation | Method of invoking a low power mode in a computer system using a halt instruction |
KR960003080B1 (ko) * | 1993-08-30 | 1996-03-04 | 켄 사쿠마 | 한국마늘의 껍질을 벗기는 기계 |
JPH11203266A (ja) * | 1998-01-07 | 1999-07-30 | Mitsubishi Electric Corp | マイクロコンピュータ |
US6671795B1 (en) | 2000-01-21 | 2003-12-30 | Intel Corporation | Method and apparatus for pausing execution in a processor or the like |
US6687838B2 (en) | 2000-12-07 | 2004-02-03 | Intel Corporation | Low-power processor hint, such as from a PAUSE instruction |
JP4831899B2 (ja) * | 2001-08-28 | 2011-12-07 | 富士通セミコンダクター株式会社 | 半導体集積回路及びクロック制御方法 |
JP4253796B2 (ja) | 2001-11-08 | 2009-04-15 | 富士通株式会社 | コンピュータ及び制御方法 |
US7363474B2 (en) | 2001-12-31 | 2008-04-22 | Intel Corporation | Method and apparatus for suspending execution of a thread until a specified memory access occurs |
US7500126B2 (en) | 2002-12-04 | 2009-03-03 | Nxp B.V. | Arrangement and method for controlling power modes of hardware resources |
JP4575795B2 (ja) * | 2005-01-31 | 2010-11-04 | パナソニック株式会社 | クロック供給回路、半導体システムおよびその設計方法 |
US7770050B2 (en) * | 2006-05-03 | 2010-08-03 | Sony Computer Entertainment Inc. | Method and apparatus for resolving clock management issues in emulation involving both interpreted and translated code |
US7647509B2 (en) | 2006-05-12 | 2010-01-12 | Intel Corporation | Method and apparatus for managing power in a processing system with multiple partitions |
KR20090014692A (ko) | 2007-08-07 | 2009-02-11 | 한국과학기술원 | 인터럽트 기반의 프로세서를 위한 인터럽트 대기 명령어를실행하는 인터럽트 처리 방법 |
US8762692B2 (en) | 2007-09-27 | 2014-06-24 | Intel Corporation | Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode |
CN101452337A (zh) | 2008-12-18 | 2009-06-10 | 北京中星微电子有限公司 | 一种外接设备的控制方法和装置 |
US8156275B2 (en) | 2009-05-13 | 2012-04-10 | Apple Inc. | Power managed lock optimization |
US8464035B2 (en) | 2009-12-18 | 2013-06-11 | Intel Corporation | Instruction for enabling a processor wait state |
JP2011150422A (ja) | 2010-01-19 | 2011-08-04 | Renesas Electronics Corp | データ処理装置 |
CN102955494A (zh) | 2011-08-31 | 2013-03-06 | 北京中电华大电子设计有限责任公司 | 一种wlan芯片的时钟树实现方法和电路 |
US9009451B2 (en) | 2011-10-31 | 2015-04-14 | Apple Inc. | Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle |
CN104769841B (zh) | 2012-09-19 | 2018-11-13 | 高通股份有限公司 | 用于降低动态功率的时钟门控电路 |
US8816743B1 (en) | 2013-01-24 | 2014-08-26 | Altera Corporation | Clock structure with calibration circuitry |
US9411360B2 (en) * | 2014-01-13 | 2016-08-09 | Apple Inc. | Method to manage current during clock frequency changes |
US9496851B2 (en) * | 2014-09-10 | 2016-11-15 | Qualcomm Incorporated | Systems and methods for setting logic to a desired leakage state |
US9672305B1 (en) * | 2015-01-28 | 2017-06-06 | Apple Inc. | Method for gating clock signals using late arriving enable signals |
CN107315448A (zh) | 2017-06-26 | 2017-11-03 | 北方电子研究院安徽有限公司 | 一种低功耗多核SoC的时钟管理架构设计方法 |
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2015
- 2015-08-06 KR KR1020150111210A patent/KR102476357B1/ko active IP Right Grant
-
2016
- 2016-06-17 US US15/185,505 patent/US10983551B2/en active Active
- 2016-08-04 TW TW105124727A patent/TWI762448B/zh active
- 2016-08-08 CN CN201610642814.4A patent/CN106444965B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW544680B (en) * | 2000-08-04 | 2003-08-01 | Nec Electronics Corp | Timer circuit and semiconductor memory device integrated with the timer circuit |
TW200739581A (en) * | 2005-09-28 | 2007-10-16 | Hynix Semiconductor Inc | Delay locked operation in semiconductor memory device |
US20140125381A1 (en) * | 2012-11-05 | 2014-05-08 | Advanced Micro Devices, Inc. | Voltage-aware signal path synchronization |
CN103116384A (zh) * | 2013-02-01 | 2013-05-22 | 山东华芯半导体有限公司 | 一种SoC系统时钟控制的方法和SoC |
Also Published As
Publication number | Publication date |
---|---|
US20170038791A1 (en) | 2017-02-09 |
KR102476357B1 (ko) | 2022-12-09 |
KR20170017382A (ko) | 2017-02-15 |
US10983551B2 (en) | 2021-04-20 |
TW201712464A (zh) | 2017-04-01 |
CN106444965A (zh) | 2017-02-22 |
CN106444965B (zh) | 2021-06-25 |
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