TWI762197B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI762197B
TWI762197B TW110105520A TW110105520A TWI762197B TW I762197 B TWI762197 B TW I762197B TW 110105520 A TW110105520 A TW 110105520A TW 110105520 A TW110105520 A TW 110105520A TW I762197 B TWI762197 B TW I762197B
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Taiwan
Prior art keywords
antenna
layer
electronic package
manufacturing
electronic
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TW110105520A
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English (en)
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TW202234604A (zh
Inventor
柯仲禹
賴佳助
陳亮斌
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矽品精密工業股份有限公司
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Priority to TW110105520A priority Critical patent/TWI762197B/zh
Priority to CN202110219310.2A priority patent/CN114976582A/zh
Priority to US17/231,436 priority patent/US11682826B2/en
Application granted granted Critical
Publication of TWI762197B publication Critical patent/TWI762197B/zh
Publication of TW202234604A publication Critical patent/TW202234604A/zh
Priority to US18/143,247 priority patent/US20230275337A1/en

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    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
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Abstract

一種電子封裝件，係包括：具有複數天線饋入線路之第一承載結構，以及設於該第一承載結構上之天線模組，且該天線模組係包含有基板本體，其具有複數不同深度之凹部，以於該複數凹部中形成有天線層，使該天線層電磁耦合該天線饋入線路，以提升該天線組件之整體輻射效率。

Description

電子封裝件及其製法
本發明係關於一種電子封裝件，特別是關於一種具有天線結構之電子封裝件及其製法。
現今無線通訊技術已廣泛應用於各式消費性電子產品(如手機、平板電腦等)，以利接收或發送各種無線訊號。為滿足消費性電子產品的便於攜帶性及上網便利性(如觀看多媒體內容)，無線通訊模組之製造與設計係朝輕、薄、短、小之需求作開發，其中，平面天線(Patch Antenna)因具有體積小、重量輕與製造容易等特性而廣泛利用在電子產品之無線通訊模組中。
此外，由於目前的多媒體內容因畫質的提升而造成其檔案資料量變得更大，故無線傳輸的頻寬也需變大，因而產生第五代的無線傳輸(5G)，另5G因傳輸頻率較高，其相關無線通訊模組的要求也較高。
有關5G之應用係未來全面商品化之趨勢，其應用頻率範圍約在1GHz~1000GHz之間的高頻頻段，其商業應用模式為5G搭配4G LTE，並於戶外架設一蜂巢式基站以配合設於室內的小基站，故5G行動通訊會於基站內使用大量天線以符合5G系統的大容量快速傳輸且低延遲。
圖1係習知無線通訊模組1之立體示意圖。如圖1所示，該無線通訊模組1係包括：一基板10、設於該基板10上之複數電子元件11、一天線結構12以及封裝材13。該基板10係為電路板並呈矩形體。該電子元件11係設於該基板10上且電性連接該基板10。該天線結構12係為平面型且具有一天線本體120與一導線121，該天線本體120藉由該導線121電性連接該電子元件11。該封裝材13覆蓋該電子元件11與該部分導線121。
以應用於智慧型手機為例，5G頻段可分為3.5Ghz~6Ghz、28Ghz、39Ghz、60Ghz、71Ghz~73Ghz等，且5G系統因訊號品質與傳輸速度要求，而需更多天線配置，以提升訊號的品質與傳輸速度。
惟，習知無線通訊模組1中，該天線結構12係為平面型，且該基板10之長寬尺寸均為固定，致使線路佈線空間(層數)有限，因而限制該天線結構12之功能，造成該無線通訊模組1無法提供運作5G系統所需之電性功能，難以達到5G系統之天線運作之需求。
再者，若於該基板10之表面上增加佈設區域以形成多種頻率之天線本體120，將使該基板10之寬度增加，導致難以縮小該無線通訊模組1的寬度，造成該無線通訊模組1無法達到微小化之需求。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：第一承載結構，係具有複數天線饋入線路；以及天線模組，係設於該第 一承載結構上，且該天線模組係包含具有相對之第一表面與第二表面之基板本體，以令該基板本體以其第一表面設於該第一承載結構上，其中，該基板本體之第一表面上係具有不同深度之複數凹部，以於該複數凹部中形成有第一天線層，且基板本體之第二表面上係具有對應該第一天線層配置之第二天線層，使該第一天線層電磁耦合該複數天線饋入線路之至少其中一者與該第二天線層。
前述之電子封裝件中，該第一天線層與該複數天線饋入線路之間形成空氣間隔。
前述之電子封裝件中，該天線模組係藉由支撐件設於該第一承載結構上。
前述之電子封裝件中，該第一承載結構係具有相對兩側，以令該天線模組設於該第一承載結構之其中一側上，且該電子封裝件復包括：第二承載結構，係藉由複數導電體堆疊於該第一承載結構之另一側上；以及至少一電子元件，係設於該第一承載結構與第二承載結構之間並電性連接該複數導電體。
前述之電子封裝件中，該第一承載結構係藉由該複數導電體電性連接該第二承載結構。
前述之電子封裝件中，該複數天線饋入線路電性連接該複數導電體，以電性導通至該至少一電子元件。
前述之電子封裝件中，復包括包覆層，其形成於該第一承載結構與第二承載結構之間以包覆該至少一電子元件。
前述之電子封裝件中，復包括形成於該第二承載結構上之複數導電元件，其與該複數導電體係分別位於該第二承載結構之不同側。
本發明亦提供一種電子封裝件之製法，係包括：提供一基板本體，其具有相對之第一表面與第二表面，且該第二表面上係具有第二天線層；形成不同深度之複數凹部於該基板本體之第一表面上；形成第一天線層於該複數凹部 中，使該第一天線層電磁耦合該第二天線層；以及將該基板本體以其第一表面設於一具有複數天線饋入線路之第一承載結構上，使該第一天線層電磁耦合該複數天線饋入線路之至少其中一者。
前述之製法中，該第一天線層與該複數天線饋入線路之間形成空氣間隔。
前述之製法中，該基板本體係藉由支撐件設於該第一承載結構上。
前述之製法中，該基板本體之第一表面上係以蝕刻方式形成該複數凹部。
前述之製法，該第一承載結構係具有相對兩側，以令該天線模組設於該第一承載結構之其中一側上，且該製法復包括將第二承載結構藉由複數導電體堆疊於該第一承載結構之另一側上，且將至少一電子元件設於該第一承載結構與第二承載結構之間並電性連接該複數導電體。
前述之製法中，該第一承載結構係藉由該複數導電體電性連接該第二承載結構。
前述之製法中，該複數天線饋入線路電性連接該複數導電體，以電性導通至該至少一電子元件。
前述之製法中，復包括於該第一承載結構與第二承載結構之間形成包覆該至少一電子元件之包覆層。
前述之製法中，復包括於該第二承載結構上設置複數導電元件，其與該複數導電體係分別位於該第二承載結構之不同側。
由上可知，本發明之電子封裝件及其天線組件與製法，係藉由該凹部之設計，以當第一天線層電磁耦合該天線饋入線路與第二天線層時，可提升該電子封裝件(或該天線組件)之天線結構之整體輻射效率，故相較於習知技術， 本發明可提升天線的效能增益及效率，並使天線之電場強度增強而有利於傳輸訊號，因而可達到5G系統之天線運作之需求。
再者，本發明藉由該複數不同深度之凹部之設計，可調整該第一天線層與第二天線層電磁耦合之距離而產生不同頻率，使該電子封裝件(或該天線組件)之天線可依需求傳遞不同之天線訊號，故相較於習知技術，本發明之單一該電子封裝件即可對應多種頻率之射頻產品之需求，以取代多個對應不同頻率之封裝模組，因而可縮減產品尺寸，以利於該電子封裝件(或該天線組件)符合微小化之需求。
又，本發明藉由將該天線模組疊置於該第一承載結構上，因而無需於該第一承載結構上增加佈設區域，故可於預定的第一承載結構尺寸下製作各種頻率之天線，以利於該電子封裝件(或該天線組件)符合微小化之需求。
1:無線通訊模組
10:基板
11,21:電子元件
12:天線結構
120:天線本體
121:導線
13:封裝材
2,3:電子封裝件
2’,3’:天線組件
2a,3a:封裝模組
2b:天線模組
20,30:第一承載結構
20a,30a:第一側
20b,30b:第二側
200:第一絕緣層
201,301:第一線路層
21a:作用面
21b:非作用面
21c:固晶層
210:電極墊
211,212:保護膜
213,313:導電凸塊
22,32:第二承載結構
220:第二絕緣層
221,321:第二線路層
23,33:導電體
24:導電元件
240:凸塊底下金屬層
25:包覆層
26:支撐件
27,29:天線本體
27a:低頻天線部
270:第一天線饋入線路
271,291:第一天線層
272,292:第二天線層
28:基板本體
28a:第一表面
28b:第二表面
280,281:凹部
29a:高頻天線部
290:第二天線饋入線路
300,320:絕緣體
302:絕緣保護層
302a,900:開孔
330:核心塊
331:導電材
35:底膠
9:承載板
A:空曠區
A1,A2:空氣間隔
D1,D2,L1,L2:距離
H1,H2:深度
S:切割路徑
圖1係為習知無線通訊模組之剖面示意圖。
圖2A至圖2F係為本發明之電子封裝件之製法之第一實施例之剖視示意圖。
圖3A至圖3E係為本發明之電子封裝件之製法之第二實施例之剖視示意圖。
圖3C-1係為圖3C之另一實施態樣示意圖。
圖4A至圖4C係為本發明之電子封裝件之天線模組之製法之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2F圖係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如圖2A所示，於一承載板9上設有第一承載結構20，該第一承載結構20具有相對之第一側20a與第二側20b，且該第一承載結構20以其第二側20b結合至該承載板9上。接著，於該第一側20a上形成複數電性連接該第一承載結構20之導電體23，且設置至少一電子元件21於該第一承載結構20之第一側20a上。
於本實施例中，該第一承載結構20係為無核心層(coreless)之線路構造，其包括至少一第一絕緣層200與設於該第一絕緣層200上之第一線路層201，如線路重佈層(redistribution layer，簡稱RDL)，其具有第一天線饋入線路(feed line)270與第二天線饋入線路290，使該第一承載結構20可做為天線基板。例如，形成該第一線路層201之材質係為銅，且形成該第一絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。
再者，該承載板9例如為半導體材質(如矽或玻璃)之圓形板體，其供該第一承載結構20之第一絕緣層200接置。
又，該導電體23係例如為柱狀體、線狀體或球狀體，其設於該第一線路層201上並電性連接該第一線路層201(或該第一天線饋入線路270與第二天線饋入線路290)，且形成該導電體23之材質係為如銅、金之金屬材或銲錫材。應可理解地，該導電體23之種類繁多，例如亦可為被動元件，並不限於上述。
另外，該電子元件21係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於本實施例中，該電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，該電子元件21係以其非作用面21b藉由一固晶層21c黏固於該第一承載結構20之第一側20a上，且該作用面21a具有複數電極墊210，並於該複數電極墊210上形成有複數導電凸塊213及至少一用以覆蓋該些電極墊210與導電凸塊213之保護膜(本實施例係以兩層保護膜211,212進行說明)，其中，該些保護膜211,212係例如為聚對二唑苯(PBO)、氮化物(如氮化矽)、氧化物(如氧化矽)，且該些導電凸塊213係為如導電線路、銲球之圓球狀、或如銅柱、銲錫凸塊等金屬材之柱狀、或銲線機製作之釘狀(stud)，但不限於此。應可理解地，該電子元件21亦可以其作用面21a藉由該些導電凸塊213以覆晶方式結合並電性連接該第一承載結構20。因此，有關該電子元件21連接該承載結構之方式繁多，如打線封裝方式，並不限於上述。
如圖2B所示，形成一包覆層25於該第一承載結構20之第一側20a上，以令該包覆層25包覆該電子元件21與該些導電體23，再藉由整平製程，令上層之保護膜212、該導電體23之端面與該導電凸塊213之端面外露於該包覆層25，使該包覆層25之上表面齊平該上層之保護膜212、該導電體23之端面與該導電凸塊213之端面。
於本實施例中，該包覆層25係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該第一承載結構20之第一側20a上。
再者，該整平製程係藉由研磨方式，移除該導電體23、保護膜212、導電凸塊213與包覆層25之部分材質，而使該包覆層25之上表面齊平該保護膜212、該導電體23之端面與該導電凸塊213之端面。
如圖2C所示，形成一第二承載結構22於該包覆層25上，使該第二承載結構22堆疊於該第一承載結構20上以形成一封裝模組2a，且令該第二承載結構22電性連接該些導電體23與該導電凸塊213。
於本實施例中，該第二承載結構22係為無核心層之線路構造，其包括複數第二絕緣層220、及設於該第二絕緣層220上之複數如RDL之第二線路層221，且最外層之第二絕緣層220可作為防銲層，以令最外層之第二線路層221外露於該防銲層。或者，該第二承載結構22亦可僅包括單一第二絕緣層220及單一第二線路層221。
再者，形成該第二線路層221之材質係為銅，且形成該第二絕緣層220之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)之介電材。
又，該第一線路層201藉由該些導電體23電性連接該第二線路層221，以令該第一天線饋入線路270與第二天線饋入線路290電性連接至該電子元件21。
另外，形成複數如銲球之導電元件24於最外層之第二線路層221上。例如，可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)240於最外層之第二線路層221上，以利於結合該導電元件24。
如圖2D所示，移除該承載板9，並翻轉整體結構，以令最外側第一絕緣層200作為絕緣保護層，且於該最外側第一絕緣層200上形成複數開孔900，以令部分該第一線路層201外露於該些開孔900。
於本實施例中，亦可再形成一如防銲層之絕緣保護層(圖未示)於該第一承載結構20之第二側20b上，且於該絕緣保護層中形成複數開孔，以令部分該第一線路層201外露於該些開孔。因此，有關該封裝模組2a之種類繁多，並不限於上述。
如圖2E所示，藉由複數支撐件26將一天線模組2b堆疊於該封裝模組2a之第一承載結構20之第二側20b上，使該天線模組2b與該第一承載結構20之間形成空曠區A。
於本實施例中，該天線模組2b係包含有一基板本體28，其為封裝基板型式，例如為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構，以於介電材上藉由濺鍍(sputtering)、蒸鍍(vaporing)、電鍍、無電電鍍、化鍍或貼膜(foiling)等方式形成複數厚度輕薄之天線本體27,29。例如，該基板本體28係定義有相對之第一表面28a與第二表面28b，以令該基板本體28以其第一表面28a藉由該些支撐件26設於該第一承載結構20之第二側20b上，且該天線本體27,29係具有相互分離且相對應配置於該第一表面28a與該第二表面28b之一第一天線層271,291與一第二天線層272,292。具體地，該第一天線層271,291係作為內天線，且該第二天線層272,292係作為外天線。
再者，該第一天線層271,291與該第二天線層272,292係以耦合方式傳輸訊號。例如，該第一天線層271,291與該第二天線層272,292係可由交變電壓、交變電流或輻射變化產生輻射能量，且該輻射能量係為電磁場，以令該第一天線層271,291與該第二天線層272,292能相互電磁耦合，使天線訊號能於該第一天線層271,291與該第二天線層272,292之間傳遞。具體地，該些第一天線層 271,291亦電磁耦合該第一天線饋入線路270與第二天線饋入線路290，使天線訊號能於該些天線本體27,29與該第一線路層201之間傳遞(如發送或接收)，故該天線模組2b與該第一承載結構20係形成天線組件2’，且該天線本體27,29及第一天線饋入線路270與第二天線饋入線路290可視為天線結構。
又，該基板本體28之第一表面28a上係具有複數深度H1,H2不同之凹部280,281，其分別對應該些天線本體27,29配置，以令該第一天線層271,291形成於該凹部280,281之底面上。藉由該第一天線層271,291與該第一天線饋入線路270及第二天線饋入線路290的距離D1,D2愈大，則頻寬愈寬的特性，因而有利於調整輻射頻率。因此，相較於形成於該第一表面28a上之天線層，形成於該凹部280,281中之天線層，將增加該第一天線層271,291與該第一天線饋入線路270及第二天線饋入線路290之間的距離D1,D2。另一方面，藉由該第一天線層271,291與該第二天線層272,292之間的距離L1,L2愈短，則頻率愈高的特性，而可依需求調控該凹部280,281之深度H1,H2進而調控該第一天線層271,291與該第二天線層272,292之間的距離L1,L2，以獲取所需之多個頻率。
另外，該支撐件26係為柱狀或牆狀，其接合該些開孔900中之第一線路層201但未訊號連接該第一線路層201，故該支撐件26僅作為支撐用而不具有訊號傳輸功能。例如，該支撐件26可為絕緣材或如銲錫之導電材，並無特別限制。
如圖2F所示，沿如圖2E所示之切割路徑S進行切單製程，以完成該電子封裝件2之製法。
於本實施例中，該電子封裝件2可藉由該些導電元件24接置一如電路板之電子裝置(圖略)，且該天線模組2b利用該第一天線饋入線路270及第二天線饋入線路290經由該導電體23及第二承載結構22，以接收/傳遞天線訊號至該電子元件21。
本實施例主要藉由在第一天線層271,291與該第一天線饋入線路270及第二天線饋入線路290之間採用低介電常數構造，其包含空氣間隔(air gap)A1,A2(其由空曠區A與凹部280,281構成)作為訊號傳遞介質，使該電子封裝件2(或該天線組件2’)之天線結構之整體輻射效率提升。
再者，藉由該凹部280,281之設計，以調整該空氣間隔A1,A2之高度，即調整該第一天線層271,291與該第二天線層272,292電磁耦合之距離L1,L2而可產生不同頻率之5G毫米波，使該電子封裝件2(或該天線組件2’)之天線結構可依需求傳遞不同之天線訊號，例如，該第一天線饋入線路270、第一天線層271與第二天線層272之間作為低頻天線部27a，且該第二天線饋入線路290、第一天線層291與第二天線層292之間作為高頻天線部29a。具體地，該電子元件21藉由該低頻天線部27a收發28吉赫(GHz)頻率之5G毫米波訊號；或者，該電子元件21藉由該高頻天線部29a收發60吉赫(GHz)頻率之5G毫米波訊號。
因此，相較於習知技術，本實施例藉由該天線模組2b包含多種頻率之天線部(該低頻天線部27a及高頻天線部29a)之設計，使單一該電子封裝件2即可對應多種頻率之射頻產品之需求，以取代多個對應不同頻率之封裝模組2a，因而可縮減產品尺寸，以利於該電子封裝件2(或該天線組件2’)符合微小化之需求。
又，本發明係將該天線模組2b疊置於該第一承載結構20上，因而無需於該第一承載結構20上增加佈設區域，使本實施例之製法能於預定的第一承載結構20尺寸下製作各種頻率之天線(即毫米波式天線)，進而使該電子封裝件2(或該天線組件2’)能符合微小化之需求。
圖3A至圖3E係為本發明之電子封裝件3之第二實施例之製法之剖視示意圖。本實施例與第一實施例大致相同，故以下僅說明相異處，而不再贅述相同處。
如圖3A所示，提供一設有複數導電體33之第一承載結構30、及一設有電子元件21之第二承載結構32。
所述之第一承載結構30係具有相對之第一側30a及第二側30b，且該第一側30a及第二側30b上形成有例如防銲層之絕緣保護層302。於本實施例中，該第一承載結構30係為封裝基板，其包含具有核心層之線路構造或無核心層之線路構造，該線路構造係包含如介電材之絕緣體300及形成於該絕緣體300上之第一線路層301，如扇出(fan out)型RDL，且該第一線路層301具有第一天線饋入線路270與第二天線饋入線路290，使該第一承載結構30可視為天線基板。具體地，該介電材係例如預浸材(PP)、聚醯亞胺(PI)、環氧樹脂或玻纖(glass fiber)，且形成該第一線路層301之材質係為金屬，如銅。應可理解地，該第一承載結構30亦可為其它承載晶片之載體，如有機板材、晶圓(wafer)、或其它具有金屬佈線(routing)之載板，並不限於上述，且該第一承載結構30因屬於板材而可免用如圖2A所示之承載件9。
再者，該絕緣保護層302係形成有複數開孔302a，以令該第一線路層301之部分表面外露於該些開孔302a。
所述之第二承載結構32係為封裝基板，其包含具有核心層之線路構造或無核心層之線路構造，該線路構造係包含如介電材之絕緣體320及形成於該絕緣體320上之第二線路層321，如扇出型RDL。具體地，該介電材係例如預浸材(PP)、聚醯亞胺(PI)、環氧樹脂或玻纖(glass fiber)，且形成該第二線路層321之材質係為金屬，如銅。應可理解地，該第二承載結構32亦可為其它承載晶片之載體，如有機板材、晶圓(wafer)、或其它具有金屬佈線(routing)之載板，並不限於上述。
所述之電子元件21以其電極墊210藉由複數如銲錫材料之導電凸塊313以覆晶方式電性連接該第二承載結構32。
所述之導電體33係形成於該第一承載結構30之第一側30a上。於本實施例中，該導電體33係為多種材質形式，其具有核心塊330與包覆該核心塊330之導電材331，其中，該核心塊330係為如塑料球之絕緣材或如銅球之金屬材，且該導電材331係為銲錫材，如鎳錫、錫鉛或錫銀，但不限於此。應可理解地，該導電體33亦可為被動元件或如圖2A所示之單一材質形式。
如圖3B所示，將該第一承載結構30藉由該些導電體33堆疊於該第二承載結構32上，並回銲該導電材331，使該第一承載結構30固接該第二承載結構32以形成一封裝模組3a，且該電子元件21位於該第一承載結構30與該第二承載結構32之間。
於本實施例中，該第一承載結構30藉由該些導電體33電性連接該第二承載結構32。
如圖3C所示，形成一包覆層25於該第一承載結構30與該第二承載結構32之間，以包覆該些導電體33、導電凸塊313與該電子元件21。
於本實施例中，如圖3C-1所示，亦可先形成底膠35於該第二承載結構32與該電子元件21之間以包覆該些導電凸塊313，再形成該包覆層25，以包覆該些導電體33、底膠35與該電子元件21。
如圖3D所示，接續圖3C所示之製程，於該第一承載結構30上藉由複數支撐件26堆疊天線模組2b，且令第一天線層271,291之位置對應該第一天線饋入線路270與第二天線饋入線路290之位置，使天線訊號能於天線本體27,29與該第一線路層301之間傳遞，其中，該天線模組2b與該第一承載結構30係視為天線組件3’，且該第一天線饋入線路270與第二天線饋入線路290、第一天線層271,291及第二天線層272,292視為天線結構。
於本實施例中，該些支撐件26係接合該些開孔302a中之第一線路層301但未訊號連接該第一線路層301，故該支撐件26僅作為支撐用而不具有訊號傳輸功能。
如圖3E所示，形成複數如銲球之導電元件24於該第二承載結構32上，且沿如圖3D所示之切割路徑S進行切單製程，以完成該電子封裝件3之製法。
本實施例係藉由在第一天線層271,291與該第一天線饋入線路270及第二天線饋入線路290之間採用空氣間隔A1,A2作為訊號傳遞介質，使該電子封裝件3之天線組件3’之整體輻射效率提升。
再者，藉由該凹部280,281之設計，以調整該空氣間隔A1,A2之高度，即調整該第一天線層271,291與該第二天線層272,292電磁耦合之距離L1,L2而可產生不同頻率之5G毫米波，使該電子封裝件3(或該天線組件3’)之天線結構可依需求傳遞不同之天線訊號。因此，相較於習知技術，本實施例藉由該天線模組2b包含多種頻率之天線部(該低頻天線部27a及高頻天線部29a)之設計，使單一該電子封裝件3即可對應多種頻率之射頻產品之需求，以取代多個對應不同頻率之封裝模組3a，因而可縮減產品尺寸，以利於該電子封裝件2(或該天線組件3’)符合微小化之需求。
又，本實施例係將該天線模組2b疊置於該第一承載結構30上，因而無需於該第一承載結構30上增加佈設區域，使本發明之製法能於預定的第一承載結構30尺寸下製作各種頻率之天線(即毫米波式天線)，進而使該電子封裝件3能符合微小化之需求。
圖4A至圖4C係為本發明之天線模組2b之製法之剖視示意圖。
如圖4A所示，提供一基板本體28，其具有相對之第一表面28a與第二表面28b，以於該基板本體28之第二表面28b上以電鍍金屬材方式形成第二天線層272,292，俾作為外天線。
如圖4B所示，於該基板本體28之第一表面28a上以例如蝕刻方式形成複數深度H1,H2不同之凹部280,281。
如圖4C所示，於該凹部280,281之底面上以電鍍金屬材方式形成第一天線層271,291，俾作為內天線，且於該基板本體28之第一表面28a上之外圍區域形成複數支撐件26。
應可理解地，有關形成天線層之方式繁多，並不限於上述，且形成凹部280,281之方式亦相當多種，並不限於上述。例如，可先形成該凹部280,281，再製作該第二天線層272,292。
本發明復提供一種電子封裝件2,3，係包括：一具有第一天線饋入線路270與第二天線饋入線路290之第一承載結構20,30以及一天線模組2b。
所述之天線模組2b係設於第一承載結構20,30上，且該天線模組2b係包含有一基板本體28，其具有相對之第一表面28a與第二表面28b，以令該基板本體28以其第一表面28a設於該第一承載結構20,30上，其中，該基板本體28之第一表面28a上係具有複數不同深度H1,H2之凹部280,281，以於該複數凹部280,281中形成有第一天線層271,291，且基板本體28之第二表面28b上係具有對應該第一天線層271,291配置之第二天線層272,292，使該第一天線層271,291電磁耦合第一天線饋入線路270及第二天線饋入線路290與第二天線層272,292。
於一實施例中，該第一天線層271,292與該第一天線饋入線路270及第二天線饋入線路290之間係形成空氣間隔A1,A2。
於一實施例中，該天線模組2b係藉由複數支撐件26設於該第一承載結構20,30上。
於一實施例中，該電子封裝件2,3復包括：第二承載結構22,32以及至少一電子元件21，且該第一承載結構20,30係具有相對之第一側20a,30a與第二側20b,30b，以令該天線模組2b設於該第一承載結構20,30之第二側20b,30b上。
所述之第二承載結構22,32係藉由複數導電體22,33堆疊於該第一承載結構20,30之第一側20a,30a上。
所述之電子元件21係設於該第一承載結構20,30與第二承載結構22,32之間並電性連接該導電體23,33。
於一實施例中，該第一承載結構20,30係藉由該導電體23,33電性連接該第二承載結構22,32。
於一實施例中，該第一天線饋入線路270與第二天線饋入線路290電性連接該導電體23,33，以電性導通至該電子元件21。
於一實施例中，所述之電子封裝件2,3復包括一包覆層25，其形成於該第一承載結構20,30與第二承載結構22,32之間，以包覆該電子元件21。
於一實施例中，所述之電子封裝件2,3復包括形成於該第二承載結構22,32上之複數導電元件24，其與該導電體23,33係分別位於該第二承載結構22,32之不同側。
綜上所述，本發明之電子封裝件及其製法暨天線組件與其製法，係藉由在第一天線層與天線饋入線路之間採用空氣間隔作為訊號傳遞介質，以提升該電子封裝件(或該天線組件)之天線結構之整體輻射效率。
再者，本發明藉由該複數不同深度之凹部之設計，以調整該第一天線層與第二天線層電磁耦合之距離而產生不同頻率，使該電子封裝件(或該天線組件)之天線可依需求傳遞不同之天線訊號，故本發明之單一該電子封裝件即可對應多種頻率之射頻產品之需求，以取代多個對應不同頻率之封裝模組，因而可縮減產品尺寸，以利於該電子封裝件(或該天線組件)符合微小化之需求。
又，藉由將該天線模組疊置於該第一承載結構上，因而無需於該第一承載結構上增加佈設區域，故能於預定的第一承載結構尺寸下製作各種頻率之天線，以利於該電子封裝件(或該天線組件)符合微小化之需求。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2’:天線組件
2a:封裝模組
2b:天線模組
20:第一承載結構
21:電子元件
22:第二承載結構
23:導電體
24:導電元件
25:包覆層
26:支撐件
27,29:天線本體
27a:低頻天線部
270:第一天線饋入線路
271,291:第一天線層
272,292:第二天線層
28:基板本體
28a:第一表面
28b:第二表面
280,281:凹部
29a:高頻天線部
290:第二天線饋入線路
A1,A2:空氣間隔

Claims (17)

  1. 一種電子封裝件，係包括：第一承載結構，係具有複數天線饋入線路；以及天線模組，係設於該第一承載結構上，且該天線模組係包含具有相對之第一表面與第二表面之基板本體，以令該基板本體以其第一表面設於該第一承載結構上，其中，該基板本體之第一表面上係具有不同深度之複數凹部，以於該複數凹部中形成有第一天線層，且該基板本體之第二表面上係具有對應該第一天線層配置之第二天線層，使該第一天線層電磁耦合該複數天線饋入線路之至少其中一者與該第二天線層。
  2. 如請求項1所述之電子封裝件，其中，該第一天線層與該複數天線饋入線路之間形成空氣間隔。
  3. 如請求項1所述之電子封裝件，其中，該天線模組係藉由支撐件設於該第一承載結構上。
  4. 如請求項1所述之電子封裝件，其中，該第一承載結構係具有相對兩側，以令該天線模組設於該第一承載結構之其中一側上，且該電子封裝件復包括：第二承載結構，係藉由複數導電體堆疊於該第一承載結構之另一側上；以及至少一電子元件，係設於該第一承載結構與第二承載結構之間並電性連接該複數導電體。
  5. 如請求項4所述之電子封裝件，其中，該第一承載結構係藉由該複數導電體電性連接該第二承載結構。
  6. 如請求項4所述之電子封裝件，其中，該複數天線饋入線路電性連接該複數導電體，以電性導通至該至少一電子元件。
  7. 如請求項4所述之電子封裝件，復包括包覆層，其形成於該第一承載結構與第二承載結構之間以包覆該至少一電子元件。
  8. 如請求項4所述之電子封裝件，復包括形成於該第二承載結構上之複數導電元件，其與該複數導電體係分別位於該第二承載結構之不同側。
  9. 一種電子封裝件之製法，係包括：提供一基板本體，其具有相對之第一表面與第二表面，且該第二表面上係具有第二天線層；形成不同深度之複數凹部於該基板本體之第一表面上；形成第一天線層於該複數凹部中，使該第一天線層電磁耦合該第二天線層；以及將該基板本體以其第一表面設於一具有複數天線饋入線路之第一承載結構上，使該第一天線層電磁耦合該複數天線饋入線路之至少其中一者。
  10. 如請求項9所述之電子封裝件之製法，其中，該第一天線層與該複數天線饋入線路之間形成空氣間隔。
  11. 如請求項9所述之電子封裝件之製法，其中，該基板本體係藉由支撐件設於該第一承載結構上。
  12. 如請求項9所述之電子封裝件之製法，其中，該基板本體之第一表面上係以蝕刻方式形成該複數凹部。
  13. 如請求項9所述之電子封裝件之製法，其中，該第一承載結構係具有相對兩側，以令該基板本體設於該第一承載結構之其中一側上，且該製法復包括：將第二承載結構藉由複數導電體堆疊於該第一承載結構之另一側上，且將至少一電子元件設於該第一承載結構與第二承載結構之間並電性連接該複數導電體。
  14. 如請求項13所述之電子封裝件之製法，其中，該第一承載結構係藉由該複數導電體電性連接該第二承載結構。
  15. 如請求項13所述之電子封裝件之製法，其中，該複數天線饋入線路電性連接該複數導電體，以電性導通至該至少一電子元件。
  16. 如請求項13所述之電子封裝件之製法，復包括於該第一承載結構與第二承載結構之間形成包覆該至少一電子元件之包覆層。
  17. 如請求項13所述之電子封裝件之製法，復包括於該第二承載結構上設置複數導電元件，其與該複數導電體係分別位於該第二承載結構之不同側。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201901915A (zh) * 2017-05-18 2019-01-01 矽品精密工業股份有限公司 電子封裝件及其製法
EP3573099A1 (en) * 2018-05-14 2019-11-27 MediaTek Inc. Antenna integrated in semiconductor package
CN111564373A (zh) * 2020-05-20 2020-08-21 甬矽电子(宁波)股份有限公司 具有天线的基板的制作方法、封装天线结构和电子设备
US20200303806A1 (en) * 2017-06-07 2020-09-24 Mediatek Inc. Semiconductor package having discrete antenna device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7675465B2 (en) * 2007-05-22 2010-03-09 Sibeam, Inc. Surface mountable integrated circuit packaging scheme
US8521106B2 (en) * 2009-06-09 2013-08-27 Broadcom Corporation Method and system for a sub-harmonic transmitter utilizing a leaky wave antenna
US8508422B2 (en) * 2009-06-09 2013-08-13 Broadcom Corporation Method and system for converting RF power to DC power utilizing a leaky wave antenna
US10957982B2 (en) * 2018-04-23 2021-03-23 Samsung Electro-Mechanics Co., Ltd. Antenna module formed of an antenna package and a connection member
US11424197B2 (en) * 2018-07-27 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package, package structure with redistributing circuits and antenna elements and method of manufacturing the same
US10971798B2 (en) * 2018-10-18 2021-04-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
TWI696255B (zh) * 2019-04-09 2020-06-11 矽品精密工業股份有限公司 電子封裝件及其製法
TWI700801B (zh) * 2019-09-16 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
CN115036669A (zh) * 2022-06-22 2022-09-09 江苏长电科技股份有限公司 天线封装结构及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201901915A (zh) * 2017-05-18 2019-01-01 矽品精密工業股份有限公司 電子封裝件及其製法
US20200303806A1 (en) * 2017-06-07 2020-09-24 Mediatek Inc. Semiconductor package having discrete antenna device
EP3573099A1 (en) * 2018-05-14 2019-11-27 MediaTek Inc. Antenna integrated in semiconductor package
CN111564373A (zh) * 2020-05-20 2020-08-21 甬矽电子(宁波)股份有限公司 具有天线的基板的制作方法、封装天线结构和电子设备

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