TWI759078B - 元件封裝、積體電路封裝及其製作方法 - Google Patents

元件封裝、積體電路封裝及其製作方法 Download PDF

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TWI759078B
TWI759078B TW110101711A TW110101711A TWI759078B TW I759078 B TWI759078 B TW I759078B TW 110101711 A TW110101711 A TW 110101711A TW 110101711 A TW110101711 A TW 110101711A TW I759078 B TWI759078 B TW I759078B
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die
layer
substrate
heat dissipation
bonding
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TW110101711A
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TW202141708A (zh
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余振華
林詠淇
邱文智
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台灣積體電路製造股份有限公司
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Abstract

一種元件封裝，包括第一晶粒，所述第一晶粒在界面處直 接接合至第二晶粒，其中所述界面包括導體對導體接合。所述元件封裝更包括包圍所述第一晶粒及所述第二晶粒的包封體及延伸穿過所述包封體的多個穿孔。所述多個穿孔鄰近所述第一晶粒及所述第二晶粒配置。所述元件封裝更包括延伸穿過所述包封體的多個熱通孔及電連接至所述第一晶粒、所述第二晶粒以及所述多個穿孔的重佈線結構。所述多個熱通孔配置於所述第二晶粒的表面上且鄰近所述第一晶粒。

Description

元件封裝、積體電路封裝及其製作方法
本發明的實施例是有關於一種積體電路封裝及其製作方法。
歸因於多種電子組件(例如，電晶體、二極體、電阻器、電容器等)的整合密度的持續改善，半導體行業已經歷快速發展。在大多數情況下，整合密度的改善源自最小特徵尺寸的反覆減小，其允許將更多組件整合至給定區域中。隨著縮小電子元件的需求增長，需要更小的半導體晶粒及其更具創造性封裝技術。此類封裝系統的一實例為層疊式封裝(Package-on-Package；PoP)技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝頂部，以提供高整合度及高組件密度。PoP技術通常使得能夠生產功能性增強且在印刷電路板(printed circuit beard；PCB)上佔據面積小的半導體元件。
在一些實施例中，元件封裝包括：第一晶粒，在界面處直接接合至第二晶粒，其中所述界面包括導體對導體接合；包封體， 包圍第一晶粒及第二晶粒；多個穿孔，延伸穿過包封體，其中所述多個穿孔鄰近第一晶粒及第二晶粒配置；多個熱通孔，延伸穿過包封體，其中所述多個熱通孔配置於第二晶粒的表面上且鄰近第一晶粒；以及重佈線結構，電連接至第一晶粒、第二晶粒及多個穿孔。
在一些實施例中，積體電路封裝包括：第一晶粒，接合至第二晶粒，其中第一晶粒的背側直接接合至第二晶粒的前側；包封體，包封第一晶粒及第二晶粒；重佈線結構，電連接至第一晶粒及第二晶粒；多個熱通孔，自第一晶粒的表面延伸至包封體的與重佈線結構相對的表面；以及多個穿孔，自重佈線結構延伸至包封體的與重佈線結構相對的表面。
在一些實施例中，製作積體電路封裝的方法包括將第一晶粒混合接合至第二晶粒；在第一晶粒及第二晶粒的側壁上方且沿所述側壁沈積晶種層；將鍍敷(plating)於第一晶粒上方的晶種層的表面上；將第一晶粒、第二晶粒以及多個熱通孔包封於包封體中；使包封體平坦化以暴露第二晶粒及多個熱通孔；以及在第二晶粒的與第一晶粒相對的側面上形成重佈線結構。
102:承載基底
104、106:釋放層
112:散熱構件
114:絕緣材料
116、118:導電接合層
116A、118A:黏著層
116B、118B:擴散障壁層
116C、118C:導電層
120、202:基底
122:導電連接件
150、154、156:箭頭
152:介電接合層
152A:第一介電接合層
152B:第二介電接合層
200、300:晶粒
204:穿孔
206:內連線結構
206A:金屬化圖案
206B:介電層
208:絕緣障壁層
210、310、318:接觸墊
212:鈍化薄膜
214、314:鈍化層
220、320:前側
222、322:背側
400、410、420、500、510、520、600、610、620、700、710、720:半導體封裝
當結合隨附圖式閱讀時，自以下詳細描述最佳地理解本發明的態樣。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。事實上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。
圖1A至圖1M示出根據一些實施例的製造半導體封裝的中 間步驟的剖面圖。
圖2示出根據一些實施例的半導體封裝的剖面圖。
圖3示出根據一些實施例的半導體封裝的剖面圖。
圖4A至圖4C示出根據一些實施例的製造半導體封裝的中間步驟的剖面圖。
圖5示出根據一些實施例的半導體封裝的剖面圖。
圖6示出根據一些實施例的半導體封裝的剖面圖。
圖7A至圖7D示出根據一些實施例的製造半導體封裝的中間步驟的剖面圖。
圖8示出根據一些實施例的半導體封裝的剖面圖。
圖9示出根據一些實施例的半導體封裝的剖面圖。
圖10A至圖10C示出根據一些實施例的製造半導體封裝的中間步驟的剖面圖。
圖11示出根據一些實施例的半導體封裝的剖面圖。
圖12示出根據一些實施例的半導體封裝的剖面圖。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及佈置的特定實例以簡化本發明。當然，這些組件及佈置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵形成於第二特徵上方或上可包括第一特徵及第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可形成在第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複參考標號 及/或字母。此重複是出於簡單及清晰的目的，且本身並不指示所論述的各種實施例及/或配置之間的關係。
另外，為易於描述，本文中可使用諸如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及類似者的空間相對術語來描述如圖式中所說明的一個元件或特徵相對於另一元件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據一些實施例，堆疊晶粒(例如，接合至第二晶粒的第一晶粒)包封在絕緣材料中，且散熱結構(例如，基底)接合至第二晶粒的背側及絕緣材料上。在一些實施例中，散熱結構為使用金屬對金屬接合(metal-to-metal bonding)來接合的半導體基底，其改善已完成封裝中的散熱且改善散熱結構與第二晶粒之間的黏著。在其他實施例中，散熱結構使用另一種接合配置(例如，介電質對介電質接合、半導體對導體接合或類似接合)來接合。
圖1A至圖1M為根據一些實施例的用於形成半導體封裝400(參見圖1M)的製程的中間步驟的剖面圖。
參考圖1A，示出半導體晶粒200。晶粒200可為裸晶片半導體晶粒(例如，未封裝半導體晶粒)。舉例而言，晶粒200可為邏輯晶粒(例如，應用程式處理器(application processor；AP)、中央處理單元、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、混合記憶體立方體(hybrid memory cube；HMC)、靜態隨機存取記憶體(static random access memory；SRAM)晶粒、寬輸入/輸出(wide input/output；wide IO)記憶體晶粒、磁阻式隨機存取記憶體(magnetoresistive random access memory；mRAM)晶粒、電阻式隨機存取記憶體(resistive random access memory；rRAM)晶粒等)、功率管理晶粒(例如，功率管理積體電路(power management integrated circuit；PMIC)晶粒)、射頻(radio frequency；RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system；MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(digital signal processing；DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end；AFE)晶粒)、生物醫學晶粒，或類似晶粒。
晶粒200可根據適用的製造製程處理以在晶粒200中形成積體電路。舉例而言，晶粒200可包括半導體基底202，諸如經摻雜或未摻雜的矽，或絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底202可包括其他半導體材料，諸如：鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。
諸如電晶體、二極體、電容器、電阻器等元件可形成於半導體基底202中及/或上，且可由包括例如在半導體基底202上的一或多個介電層206B中的金屬化圖案206A的內連線結構206內連。內連線結構206電連接基底202上的元件以形成一或多個積體電路。
晶粒200各自更包括穿孔204，所述穿孔204可電連接至 內連線結構206中的金屬化圖案。穿孔204可包括導電材料(例如，銅或類似物)且可自內連線結構206延伸至基底202中。絕緣障壁層208可形成在基底202中的至少部分穿孔204周圍。絕緣障壁層208可包括例如氧化矽、氮化矽、氮氧化矽或類似物，且可用於使穿孔204與基底202實體及電氣隔離。在後續處理步驟中，可薄化基底202以暴露穿孔204(參見圖1C)。在薄化後，穿孔204提供自基底202的背側至基底202的前側的電連接。
晶粒200各自更包括接觸墊210，其允許內連線結構206與基底202上的元件形成外部連接。接觸墊210可包括銅、鋁(例如，28K鋁)或另一種導電材料。接觸墊210配置於可被稱為晶粒200的主動側或前側220的側面上。晶粒200的主動側/前側220可指代其上形成有主動元件的半導體基底202的側面。晶粒200的背側222可指代半導體基底的與主動側/前側相對的側面。
鈍化薄膜212配置於內連線結構206上，且接觸墊210暴露在鈍化薄膜212的頂表面處。鈍化薄膜212可包括氧化矽、氮氧化矽、氮化矽或類似物。在一些實施例中，接觸墊210可在鈍化薄膜212的頂表面上方延伸。
晶粒200可形成為較大晶圓的部分(例如，連接至其他晶粒200)。在一些實施例中，晶粒200可在封裝之前彼此單體化。單體化製程可包括機械鋸割、雷射切割、電漿切割、其組合或類似製程。在其他實施例中，晶粒200在整合至半導體封裝中之後單體化。舉例而言，可在仍連接為晶圓的部分的同時封裝晶粒200。
在一些實施例中，晶片探針(chip probe；CP)測試可施加至晶粒200中的每一者(例如，經由接觸墊210)。CP測試檢查 晶粒200的電功能性，且通過所述CP測試的晶粒被稱為良品晶粒(known good dies；KGD)。丟棄或整修未通過CP測試的晶粒200。以此方式，提供KGD以用於封裝，從而減少浪費及封裝故障晶粒的費用。
在CP測試後，在每一KGD的接觸墊210及內連線結構206上方形成鈍化層214。鈍化層214可包括氧化矽、氮氧化矽、氮化矽或類似物。如本文中所描述，鈍化層214可在後續封裝製程期間保護接觸墊210。
在圖1B中，將晶粒200以正面朝下方式貼合至承載基底102。承載基底102可為玻璃承載基底、陶瓷承載基底或類似物。承載基底102可為晶圓，以使得多個封裝可同時形成於承載基底102上。儘管僅在圖1B中示出單個晶粒200，但可將多個晶粒200貼合至承載基底102以供同步處理。舉例而言，晶粒200可在使用晶圓覆晶(chip on wafer；CoW)製程單體化後貼合至承載基底102，或晶粒200可在使用層疊晶圓(wafer on wafer；WoW)製程單體化之前貼合至承載基底102。晶粒200以正面朝下的方式配置，使得晶粒200的前側220面向承載基底102且晶粒200的背側222背對承載基底102。
在一些實施例中，晶粒200藉由釋放層106貼合至承載基底102，且晶粒200的鈍化層214可接觸釋放層106。釋放層106可由聚合物類材料形成，所述釋放層106可與承載基底102一起自晶粒200及將在後續步驟中形成的其他上覆結構移除。在一些實施例中，釋放層106為在加熱時損失其黏著特性的環氧樹脂類熱釋放材料，諸如光-熱轉換(light-to-heat-conversion；LTHC) 釋放塗層。在其他實施例中，釋放層106可為在暴露於UV光下時損失其黏著特性的紫外線(ultra-violet；UV)膠。釋放層106可呈液體形式施配且經固化，可為疊層於承載基底102上的疊層膜，或可為類似物。在其他實施例中，晶粒200可例如藉由將鈍化層214熔融接合至載體102來直接熔融接合至載體102。熔融接合可形成鈍化層214與載體102之間的介電質對半導體(dielectric-to-semiconductor)接合。在此類實施例中，可省略釋放層106。
在圖1C中，可將薄化製程施加於晶粒200以暴露穿孔204。薄化會移除基底202在穿孔204上方的部分。在一些實施例中，薄化可進一步移除在穿孔204上的障壁層(例如，障壁層208，參見圖1A)的橫向部分以暴露穿孔204。薄化製程可包括執行化學機械研磨(chemical mechanical polish；CMP)、研磨、回蝕(例如，濕式蝕刻)、其組合或類似製程。在一些實施例中，薄化製程可使基底202凹陷，以使穿孔204延伸超出基底202的背面。此可例如經由選擇性蝕刻基底202的選擇性蝕刻製程達成而無需明顯蝕刻穿孔204。
在圖1D中，介電層106沈積於基底202上方及穿孔204的部分周圍。舉例而言，介電層106可沈積在於基底202上方延伸的穿孔204的部分周圍。介電層106可包括氧化矽、氮化矽、氮氧化矽或類似物，且介電層106可使用合適的沈積製程來沈積，諸如化學氣相沈積(chemical vapor deposition；CVD)、物理氣相沈積(physical vapor deposition；PVD)、原子層沈積(atomic layer deposition；ALD)或類似沈積製程。可沈積介電層106以首先覆蓋穿孔204。隨後，可執行平坦化步驟以使穿孔204與介電層106 的表面實質上齊平。
在圖1E中，晶粒300例如以混合接合配置接合至晶粒200。晶粒300的結構可類似於針對晶粒200所描述的結構，且本文不重複所述細節。可藉由參考晶粒200中的相同特徵發現晶粒300中的特徵的材料及形成製程，其中晶粒200中的相同特徵以數字「2」開始，所述特徵對應於晶粒300中的具有以數字「3」開始的參考標號的特徵。在特定實施例中，晶粒300為記憶體晶粒，但亦可使用其他類型的晶粒。
晶粒300以正面朝下的方式配置，使得晶粒300的前側320面向晶粒200且晶粒300的背側322背對晶粒200。晶粒300接合至在晶粒200的背側上的介電層106及在晶粒200中的穿孔204。舉例而言，晶粒300的鈍化層可直接接合至介電層106，且晶粒300的接觸墊310可直接接合至穿孔204。在一實施例中，鈍化層314之間的接合為氧化物間接合或類似接合。混合接合製程經由直接金屬對金屬接合進一步將晶粒300的接觸墊318直接接合至晶粒200的穿孔204。因此，晶粒200與晶粒300之間的電連接由接觸墊310至穿孔204的實體連接提供。
舉例而言，混合接合製程開始於例如藉由對介電層106或鈍化層314中的一或多者施加表面處理而將晶粒200與晶粒300對準。所述表面處理可包括電漿處理。可在真空環境中執行電漿處理。在電漿處理後，表面處理可更包括可施加至介電層106或鈍化層314中的一或多者的清潔製程(例如，用去離子水或類似物沖洗)。隨後，可繼續進行混合接合製程以將接觸墊310與穿孔204對準。當晶粒200與晶粒300對準時，接觸墊310可與對應穿孔 204重疊。接著，混合接合包括預接合步驟，在此期間使每一晶粒200與各別晶粒300接觸。可在室溫下(例如，約21℃至約25℃之間)執行預接合。混合接合製程繼續例如在約150℃與約400℃之間的溫度下執行退火約0.5小時與約3小時之間的持續時間，以使得接觸墊310中的金屬(例如，銅)及穿孔204中的金屬(例如，銅)彼此互相擴散，且因此形成直接金屬對金屬接合。儘管僅單個晶粒300經示出為接合至晶粒200，但其他實施例可包括接合至晶粒200的多個晶粒300。在此類實施例中，多個晶粒300可呈堆疊配置(例如，具有多個堆疊晶粒300)及/或並排配置。
晶粒300的表面積可小於晶粒200。晶粒200橫向延伸超過晶粒300，且在使晶粒200及晶粒300接合後暴露介電層106的部分。藉由使介電層106的部分暴露，視情況選用的散熱構件112可貼合至介電層106以包圍晶粒300。散熱構件112可為一或多個矽晶粒(參見例如，圖1F的俯視圖)、矽環(參見例如，圖1G的俯視圖)或包圍晶粒300的一或多個側面的類似者。散熱構件112可不含任何主動元件及/或不含任何被動元件。因此，在一些實施例中，散熱構件112可被稱為虛設構件(dummy feature)。
散熱構件112可使用例如形成於散熱構件112的底表面處的原生氧化物、熱氧化物或類似物藉由介電質對介電質接合來接合至介電層106。介電質對介電質接合製程可包括對介電層106或在散熱構件112上的氧化物中的一或多者施加表面處理。表面處理可包括電漿處理。可在真空環境中執行電漿處理。在電漿處理後，表面處理可更包括可施加至介電層106或在散熱構件112上的氧化物中的一或多者的清潔製程(例如，用去離子水或類似物沖 洗)。隨後，可使散熱構件112與介電層106對準，且所述兩者彼此壓抵以引發散熱構件112至晶粒200的預接合。可在室溫下(例如，約21℃至約25℃之間)執行預接合。在預接合後，可藉由例如在約150℃至400℃之間的溫度下加熱散熱構件112約0.5小時至約3小時之間的持續時間來施加退火製程。可同時執行將散熱構件112接合至晶粒200及將晶粒300接合至晶粒200的退火製程，使得不需要執行分開退火。
在其他實施例中，可省略散熱構件112(參見例如圖2及圖3)。在此類實施例中，晶粒300的表面積可小於晶粒200的表面積(參見例如圖2)。替代地，晶粒300的表面積可與晶粒200的表面積相同，且晶粒300可與晶粒200毗連(參見例如圖3)。舉例而言，在一些實施例中，晶粒300可接合至晶粒200，同時晶粒300及晶粒200仍使用晶圓間(wafer to wafer；WoW)接合製程整合於其各別晶圓中。在其他實施例中，單體化晶粒300可接合至晶粒200，同時晶粒200仍使用晶片至晶圓(chip to wafer；CoW)接合製程整合於晶圓中。
在圖1H中，絕緣材料114形成於晶粒200上方、晶粒300周圍以及散熱構件112(若存在)周圍。在一些實施例中，絕緣材料114為模製化合物(例如，環氧樹脂、樹脂、可模製聚合物或類似物)，所述模製化合物使用例如可具有在應用時用於保持絕緣材料114的邊界或其他構件的模具(未繪示)成形或模製。此模具可用於壓力模製晶粒300周圍的絕緣材料114以迫使絕緣材料114進入開口及凹部中，從而排除在絕緣材料114中的氣穴或類似物。
在一些實施例中，絕緣材料114為形成於晶粒200上方的包括氧化物、氮化物、氮氧化物或類似物的介電質。在此類實施例中，絕緣材料114可包括氮化矽、氧化矽、氮氧化矽或另一介電材料，且藉由化學氣相沈積(chemical vapor deposition；CVD)、電漿增強CVD(plasma enhanced CVD；PECVD)或另一製程形成。
亦由圖1H示出，絕緣材料114可藉由例如研磨、化學機械研磨(chemical-mechanical polish；CMP)製程或類似製程平坦化。在平坦化後，絕緣材料114、晶粒300、散熱構件112(若存在)的頂表面實質上齊平。散熱構件112提供自晶粒200的表面穿過絕緣材料114的散熱。
在圖1I中，導電接合層116形成於晶粒300、散熱結構112(若存在)以及絕緣材料114上方。在一些實施例中，接合層116包括一或多個導電層(例如，金屬層)，諸如視情況選用的黏著層116A、視情況選用的擴散障壁層116B以及導電層116C。接合層116中的每一層可藉由PVD、CVD、ALD、鍍敷或類似方式沈積。黏著層116A可包括鈦、鋁、鉭、其組合或類似物。黏著層116A輔助層116B及層116C黏著至晶粒300、散熱結構112(若存在)以及絕緣材料114，且在一些實施例中，可省略黏著層116A。擴散障壁層116B可包括鈦、氮化鈦、鉭、氮化鉭、鈷、其組合或類似物。擴散障壁層116B可用於防止或至少減少導電層116C的材料至封裝的下伏構件的擴散，且在一些實施例中，可省略擴散障壁層116B。導電層116C可包括銅、鋁、銦、其組合或類似物。導電層116C可在後續製程步驟中用作基底的接合界面。使用導電層作為接合界面可具有優勢，諸如改善封裝結構中的散熱及黏著。
在圖1J中，提供基底120。可選擇基底120以在其貼合至晶粒200及晶粒300後提供散熱(參見圖1K)。舉例而言，基底120可為矽基底、玻璃基底(例如，具有在約1.5瓦/米．度至約5瓦/米．度範圍內的熱導率的玻璃基底)或類似物。在一些實施例中，基底120可不含任何主動元件且不含任何被動元件。
亦在圖1J中示出，導電接合層118形成於基底120上方。在一些實施例中，接合層118包括一或多個導電層(例如，金屬層)，諸如視情況選用的黏著層118A、視情況選用的擴散障壁層118B以及導電層118C。在接合層118中的每一層可藉由PVD、CVD、ALD、鍍敷或類似方式沈積。黏著層118A可包括鈦、鋁、鉭、其組合或類似物。黏著層118A輔助層118B及層118C黏著至基底120，且在一些實施例中，可省略黏著層118A。擴散障壁層118B可包括鈦、氮化鈦、鉭、氮化鉭、鈷、其組合或類似物。擴散障壁層118B可用於防止或至少減少導電層118C的材料至下伏基底120的擴散，且在一些實施例中，可省略擴散障壁層118B。導電層118C可包括銅、鋁、銦、其組合或類似物。導電層118C可在後續製程步驟中用作基底的接合界面。使用導電層作為接合界面可具有優勢，諸如改善所得封裝結構中的散熱及黏著。
導電層118C的材料可與導電層116C(參見圖11)的材料相同或不同。舉例而言，在一些實施例中，導電層116C及導電層118C可各自為銅層、金層或類似層。在一些實施例中，導電層116C為銅層，且導電層118C為金層；替代地，導電層116C為金層，且導電層118C為銅層。在一些實施例中，導電層116C為銦層，且導電層118C為金層；替代地，導電層116C為金層，且導 電層118C為銦層。
在圖1K中，藉由將接合層116直接接合至接合層118，基底120接合至晶粒200及晶粒300。使接合層116及接合層118直接接合可形成導電層116C與導電層118C之間的金屬對金屬接合(例如，銅-銅接合、銅-金接合、金-金接合、銦-金接合或類似接合)。接合基底120可包括使接合層116與接合層118對準，且所述兩個接合層彼此壓抵以促使基底120與晶粒200及晶粒300的預接合。可在室溫下(例如，約21℃至約25℃之間)執行預接合。在預接合後，可藉由例如在約150℃至400℃之間的溫度下加熱約0.5小時至約3小時之間的持續時間來施加退火製程，以使得接合層116及接合層118中的金屬(例如，銅、金、銦及/或類似物)彼此互相擴散，且因此形成直接金屬對金屬接合。
基底120可為晶粒200及晶粒300提供改善的散熱。舉例而言，晶粒300、散熱構件112(若存在)以及接合層116及接合層118可提供自晶粒200至基底120的散熱路徑。另外，基底120可充當晶粒200及晶粒300提供實體支撐的載體。因此，可改善元件可靠性及耐久性。
在圖1L中，執行承載基底剝離以使承載基底102自晶粒200脫離(剝離)。根據一些實施例，剝離包括將諸如雷射光或UV光的光投射於釋放層104上，以使得釋放層104在光的熱量下分解且承載基底102可得以移除。在移除承載基底102後，穿過鈍化層214形成開口以暴露接觸墊210的部分。可例如使用雷射鑽孔、蝕刻或類似方式來形成開口。
接著，在圖1M中，導電連接件122形成於接觸墊210 上。導電連接件122可為BGA連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微凸塊、化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成的凸塊或類似物。導電連接件122可包括導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合。在一些實施例中，藉由首先經由諸如蒸鍍、電鍍、列印、焊料轉移、植球或類似方式的此類常用方法形成焊料層來形成導電連接件122。一旦焊料層已形成於結構上，即可執行回焊以便將材料塑形成所要凸塊形狀。在另一實施例中，導電連接件122為藉由濺鍍、列印、電鍍、化學鍍、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可不含焊料且具有實質上豎直之側壁。在一些實施例中，金屬頂蓋層(未繪示)形成於金屬柱連接件122的頂部。金屬頂蓋層可包括鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或其組合，且可由鍍敷製程形成。
因此，形成半導體封裝400。封裝基底400包括第一晶粒200及混合接合至第一晶粒的第二晶粒300。舉例而言，第一晶粒200可經由介電質對介電質接合與金屬對金屬接合的組合而接合至第二晶粒300。在一些實施例中，第一晶粒200在無任何介入焊料區域的情況下接合至第二晶粒300。絕緣材料114配置於第二晶粒300周圍，且一或多個散熱構件112自第一晶粒200的表面延伸穿過絕緣材料114。基底120使用例如直接金屬對金屬接合而接合至第二晶粒300的與第一晶粒200相對的側面。舉例而言，在第二晶粒300及絕緣材料114上方的導電接合層116可直接接合至形成於矽基底上的導電接合層118。基底120在半導體封裝400 中提供散熱及支撐。
在晶粒200仍作為晶圓之部分封裝之實施例中，可施加單體化以使半導體封裝400與其他同時形成的半導體封裝分開。由於單體化，基底120、導電接合層116、導電接合層118、絕緣材料114以及晶粒200可全部毗連。
圖2示出根據一些替代實施例的半導體封裝410的剖面圖。半導體封裝410可類似於半導體封裝400，其中相同參考標號指示使用相同製程形成的相同元件。在半導體封裝410中，省略散熱構件112。晶粒200可比晶粒300寬且橫向延伸超過晶粒300。
圖3示出根據一些替代實施例的半導體封裝420的剖面圖。半導體封裝420可類似於半導體封裝400，其中相同參考標號指示使用相同製程形成的相同元件。在半導體封裝420中，省略散熱構件112。晶粒200可具有與晶粒300相同的寬度且與晶粒300毗連。
圖4A至圖4C示出根據一些實施例的形成半導體封裝500的中間階段的剖面圖。在圖4A中，示出與上文關於圖11及圖1J所描述的結構類似的結構，其中相同參考標號指示使用相同製程形成的相同元件。然而，在圖4A中，自晶粒200及晶粒300上方省略接合層116。另外，自基底120省略接合層118。在圖4A中，基底120對準晶粒300、絕緣材料114以及散熱構件112，以使得基底120的暴露表面面向晶粒300、絕緣材料114以及散熱構件112的暴露表面。此由箭頭150指示。
舉例而言，在圖4B中，基底120使用直接接合而直接接合至晶粒300、絕緣材料114以及散熱構件112而無需沈積任何介 入接合層。在一些實施例中，直接接合形成於基底120與晶粒300之間，且直接接合亦可形成於散熱構件112與基底120之間。
作為直接接合基底120的一實例，可對基底120執行表面處理。表面處理包括在基底120的表面上形成原生氧化物或熱氧化物。表面處理可更包括電漿處理製程，且用於產生電漿的處理氣體可為含氫氣體，所述含氫氣體包括：含有氫氣(H2)及氬氣(Ar)的第一氣體；含有H2及氮氣(N2)的第二氣體；或含有H2及氦氣(He)的第三氣體。經由處理，在基底120的表面上的OH基團的數目例如藉由與基底120的表面上存在的原生氧化物或熱氧化物相互作用而增加。接著，基底120壓抵晶粒300、絕緣材料114以及散熱構件112以形成弱接合。隨後，執行退火以加強弱接合及形成熔融接合。在退火期間，OH鍵中的H排出，從而在基底120與晶粒300之間形成Si-O-Si鍵，從而加強接合。
基底120可為晶粒200及晶粒300提供改善的散熱。舉例而言，晶粒300及散熱構件112(若存在)可提供自晶粒200至基底120的散熱路徑。另外，基底120可充當晶粒200及晶粒300提供實體支撐的載體。因此，可改善元件可靠性及耐久性。圖4C示出在執行處理(例如，如上文在圖1L至圖1M中所描述)以移除載體102及形成連接件122之後所得的封裝。
圖5示出根據一些替代實施例的半導體封裝510的剖面圖。半導體封裝510可類似於半導體封裝500，其中相同參考標號指示使用相同製程形成的相同元件。舉例而言，在半導體封裝510中，基底120直接接合至晶粒300而無需任何介入接合層。在半導體封裝510中，省略散熱構件112，且晶粒200可比晶粒300寬 且橫向延伸超過晶粒300。
圖6示出根據一些替代實施例的半導體封裝520的剖面圖。半導體封裝520可類似於半導體封裝500，其中相同參考標號指示使用相同製程形成的相同元件。舉例而言，在半導體封裝520中，基底120直接接合至晶粒300而無需任何介入接合層。在半導體封裝520中，省略散熱構件112，且晶粒200可具有與晶粒300相同的寬度且與晶粒300毗連。
圖7A至圖7D示出根據一些實施例的形成半導體封裝600的中間階段的剖面圖。在圖7A中，示出與上文關於圖1I及圖1J所描述的結構類似的結構，其中相同參考標號指示使用相同製程形成的相同元件。然而，在圖7A中，自晶粒200及晶粒300上方省略接合層116。另外，自基底120省略接合層118。在圖7A中，介電接合層152沈積於承載基底120上。介電接合層152可包括氧化矽、氮氧化矽或類似物且藉由CVD、PVD、ALD或類似方式沈積。替代地，介電接合層152可沈積於晶粒300、散熱構件112以及絕緣材料114而非基底120上(參見圖7B)。
在圖7A及圖7B中，基底120對準晶粒300、絕緣材料114以及散熱構件112，以使得基底120的暴露表面面向晶粒300、絕緣材料114以及散熱構件112的暴露表面。此由箭頭154指示。
舉例而言，在圖7C中，基底120使用介電接合層152接合至晶粒300、絕緣材料114以及散熱構件112以形成介電質對半導體接合。在一些實施例中，介電質對半導體接合形成於介電接合層152與晶粒300之間以及散熱構件112與基底120之間。在一些實施例中，介電質對半導體接合形成於介電接合層152與基底 120之間。
基底120可為晶粒200及晶粒300提供改善的散熱。舉例而言，晶粒300及散熱構件112(若存在)可提供自晶粒200至基底120的散熱路徑。另外，基底120可充當晶粒200及晶粒300提供實體支撐的載體。因此，可改善元件可靠性及耐久性。圖7D示出在執行處理(例如，如上文在圖1L至圖1M中所描述)以移除載體102及形成連接件122之後所得的封裝。因此，形成半導體封裝600。
圖8示出根據一些替代實施例的半導體封裝610的剖面圖。半導體封裝610可類似於半導體封裝600，其中相同參考標號指示使用相同製程形成的相同元件。舉例而言，在半導體封裝610中，基底120藉由介電接合層152接合至晶粒300。在半導體封裝610中，省略散熱構件112，且晶粒200可比晶粒300寬且橫向延伸超過晶粒300。
圖9示出根據一些替代實施例的半導體封裝620的剖面圖。半導體封裝620可類似於半導體封裝600，其中相同參考標號指示使用相同製程形成的相同元件。舉例而言，在半導體封裝620中，基底120藉由介電接合層152接合至晶粒300。在半導體封裝620中，省略散熱構件112，且晶粒200具有與晶粒300相同的寬度且與晶粒300毗連。
圖10A至圖10C示出根據一些實施例的形成半導體封裝700的中間階段的剖面圖。在圖10A中，示出與上文關於圖1I及圖1J所描述的結構類似的結構，其中相同參考標號指示使用相同製程形成的相同元件。然而，在圖10A中，自晶粒200及晶粒300 上方省略接合層116。另外，自基底120省略接合層118。第一介電接合層152A形成於基底120上，且第二介電接合層152B形成於晶粒300、絕緣材料114以及散熱構件112上。介電接合層152A及介電接合層152B實質上類似於介電接合層152且可使用如上文所描述的類似製程及類似材料形成。
基底120對準晶粒300、絕緣材料114以及散熱構件112以使得基底120的暴露表面面向晶粒300、絕緣材料114以及散熱構件112的暴露表面。此由箭頭156指示。
舉例而言，在圖10B中，基底120使用介電接合層152A及介電接合層152B接合至晶粒300、絕緣材料114以及散熱構件112以形成介電質對介電質接合。在一些實施例中，介電質對介電質接合形成於介電接合層152A與介電接合層152B之間。
作為形成介電質對介電質接合的一實例，可對介電接合層152A及/或介電接合層152B執行表面處理。表面處理可更包括電漿處理製程，且用於產生電漿的處理氣體可為含氫氣體，所述含氫氣體包括：含有氫氣(H2)及氬氣(Ar)的第一氣體；含有H2及氮氣(N2)的第二氣體；或含有H2及氦氣(He)的第三氣體。經由處理，在介電接合層152A及/或介電接合層152B表面的OH基團的數目會增加。接著，介電接合層152A壓抵介電接合層152B以形成弱接合。隨後，執行退火以加強弱接合及形成熔融接合。在退火期間，OH鍵中的H排出，從而在介電接合層152A與介電接合層152B之間形成Si-O-Si鍵，從而加強接合。
基底120可為晶粒200及晶粒300提供改善的散熱。舉例而言，晶粒300及散熱構件112(若存在)可提供自晶粒200至 基底120的散熱路徑。另外，基底120可充當晶粒200及晶粒300提供實體支撐的載體。因此，可改善元件可靠性及耐久性。圖10C示出在執行處理(例如，如上文在圖1L至圖1M中所描述)以移除載體102及形成連接件122之後所得的封裝。因此，形成半導體封裝700。
圖11示出根據一些替代實施例的半導體封裝710的剖面圖。半導體封裝710可類似於半導體封裝700，其中相同參考標號指示使用相同製程形成的相同元件。舉例而言，在半導體封裝710中，基底120藉由介電接合層152A及介電接合層152B接合至晶粒300。在半導體封裝710中，省略散熱構件112，且晶粒200可比晶粒300寬且橫向延伸超過晶粒300。
圖12示出根據一些替代實施例的半導體封裝720的剖面圖。半導體封裝720可類似於半導體封裝700，其中相同參考標號指示使用相同製程形成的相同元件。舉例而言，在半導體封裝720中，基底120藉由介電接合層152A及介電接合層152B接合至晶粒300。在半導體封裝720中，省略散熱構件112，且晶粒200具有與晶粒300相同的寬度且與晶粒300毗連。
根據一些實施例，堆疊晶粒(例如，接合至第二晶粒的第一晶粒)包封在絕緣材料中，且基底接合至第二晶粒的背側及絕緣材料。基底可提供結構支撐及散熱。在一些實施例中，基底使用金屬對金屬接合進行接合，從而改善已完成封裝中的散熱且改善基底與第二晶粒之間的黏著。在其他實施例中，基底使用另一接合配置(例如，具有或不具有介入介電接合層)進行接合。
在一些實施例中，元件封裝包括：第一晶粒，在界面處直 接接合至第二晶粒，其中所述界面包括導體對導體接合；包封體，包圍第一晶粒及第二晶粒；多個穿孔，延伸穿過包封體，其中所述多個穿孔鄰近第一晶粒及第二晶粒配置；多個熱通孔，延伸穿過包封體，其中所述多個熱通孔配置於第二晶粒的表面上且鄰近第一晶粒；以及重佈線結構，電連接至第一晶粒、第二晶粒及多個穿孔。視情況，在一些實施例中，第一晶粒更包括：半導體基底，其中第二晶粒的介電層在界面處直接接合至半導體基底；及基底穿孔，延伸穿過半導體基底，其中第二晶粒的接觸墊在界面處直接接合至基底穿孔。視情況，在一些實施例中，基底穿孔將第二晶粒電連接至重佈線結構。視情況，在一些實施例中，第一晶粒的介電層在界面處直接連接至第二晶粒的介電層，且其中第一晶粒的接觸墊在界面處直接連接至第二晶粒的接觸墊。視情況，在一些實施例中，第一晶粒包括延伸穿過半導體基底的穿孔，其中所述穿孔延伸而高於半導體基底。視情況，在一些實施例中，元件封裝更包括在第二晶粒上方且沿第一晶粒的側壁配置的鈍化介電層。視情況，在一些實施例中，鈍化介電層配置於多個熱通孔的底表面與第二晶粒的頂表面之間。視情況，在一些實施例中，元件封裝更包括在穿孔及鈍化介電層上的接觸墊，其中所述接觸墊將穿孔電連接至重佈線結構。視情況，在一些實施例中，多個熱通孔與在第一晶粒及第二晶粒中的任何主動元件電隔離。視情況，在一些實施例中，多個熱通孔電連接至在第一晶粒中的主動元件。
在一些實施例中，封裝包括：第一晶粒，接合至第二晶粒，其中第一晶粒的背側直接接合至第二晶粒的前側；包封體，包封第一晶粒及第二晶粒；重佈線結構，電連接至第一晶粒及第二晶粒； 多個熱通孔，自第一晶粒的表面延伸至包封體的與重佈線結構相對的表面；以及多個穿孔，自重佈線結構延伸至包封體的與重佈線結構相對的表面。視情況，在一些實施例中，第一晶粒包括：半導體基底，直接接合至第二晶粒的介電層；及穿孔，延伸穿過半導體基底，其中第二晶粒的接觸墊直接接合至穿孔。視情況，在一些實施例中，多個熱通孔中的每一者包括在第一晶粒的背側上的晶種層。視情況，在一些實施例中，多個熱通孔在平面圖中延伸超過第二晶粒的側壁。視情況，在一些實施例中，多個穿孔在平面圖中環繞第一晶粒及第二晶粒。
在一些實施例中，方法包括將第一晶粒混合接合至第二晶粒；在第一晶粒及第二晶粒的側壁上方且沿所述側壁沈積晶種層；將鍍敷於第一晶粒上方的晶種層的表面上；將第一晶粒、第二晶粒以及多個熱通孔包封於包封體中；使包封體平坦化以暴露第二晶粒及多個熱通孔；以及在第二晶粒的與第一晶粒相對的側面上形成重佈線結構。視情況，在一些實施例中，所述方法更包括在將第一晶粒混合接合至第二晶粒之前，將第一晶粒貼合至載體，其中所述晶種層沈積於載體上方；以及將多個穿孔鍍敷於載體上方的晶種層的表面上。視情況，在一些實施例中，第一晶粒混合接合至第二晶粒包括：將第二晶粒的介電層直接接合至第一晶粒的半導體基底；以及將第二晶粒的介電層中的接觸墊直接接合至延伸穿過第一晶粒的半導體基底的穿孔。視情況，在一些實施例中，所述方法更包括在形成重佈線結構之前，自第一載體移除第一晶粒及第二晶粒；以及將第二載體貼合至第二晶粒的與第一晶粒相對的側面。視情況，在一些實施例中，所述方法更包括在鍍敷多個熱 通孔之後，自第一晶粒的側壁、第二晶粒的側壁以及第二晶粒的頂表面移除晶種層。
前文概述若干實施例的特徵，以使得本領域技術人員可較好地理解本發明的態樣。本領域技術人員應理解，其可容易地使用本發明作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優勢的其他製程及結構的基礎。本領域技術人員亦應認識到，此類等效構造並不脫離本發明的精神及範疇，且其可在不脫離本發明的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
106:釋放層
112:散熱構件
114:絕緣材料
116、118:導電接合層
116A、118A:黏著層
116B、118B:擴散障壁層
116C、118C:導電層
116A、118A:黏著層
116B、118B:擴散障壁層
116C、118C:導電層
120、202:基底
122:導電連接件
200、300:晶粒
204:穿孔
206:內連線結構
210、310:接觸墊
214、314:鈍化層
400:半導體封裝

Claims (10)

  1. 一種元件封裝，包括：第一晶粒；第二晶粒，位於所述第一晶粒上且在界面處與所述第一晶粒直接接合，其中所述界面包括金屬對金屬接合；絕緣材料，環繞所述第二晶粒；第一導電接合層，位於所述第二晶粒與所述絕緣材料上；基底，經由第二導電接合層接合至所述第一導電接合層，其中所述第一導電接合層與所述第二導電接合層實體接觸。
  2. 如請求項1之元件封裝，其中所述金屬對金屬接合位於所述第一晶粒的穿孔與所述第二晶粒的接觸墊之間。
  3. 如請求項1之元件封裝，更包括介電層位於所述第一晶粒與所述第二晶粒的界面處，其中所述介電層環繞所述穿孔的上部份。
  4. 如請求項1之元件封裝，更包括延伸穿過所述絕緣材料的散熱構件，其中所述第一導電接合層與所述散熱構件直接接觸。
  5. 一種積體電路封裝，包括：第一晶粒，包括半導體基底及延伸穿過所述半導體基底的穿孔；第二晶粒，接合至所述第一晶粒，其中所述第二晶粒的接觸墊直接接觸所述第一晶粒的所述穿孔；絕緣材料，環繞所述第二晶粒；以及基底，在無接合層的情況下直接接合至所述第二晶粒，其中 所述第一導電接合層與所述第二導電接合層接觸，其中所述基底更直接接觸所述絕緣材料。
  6. 如請求項5之積體電路封裝，更包括位於所述絕緣材料中的散熱構件，所述散熱構件從所述第一晶粒連續地延伸至所述基底。
  7. 如請求項5之積體電路封裝，其中所述第二晶粒的鈍化層與所述第一晶粒的介電層直接接觸，所述介電層環繞所述穿孔的上部份，且所述接觸墊配置於所述鈍化層中。
  8. 一種積體電路的製作方法，包括：以第一金屬對金屬接合將第一晶粒直接接合至第二晶粒；沉積環繞所述第二晶粒的絕緣材料；在所述第二晶粒與所述絕緣材料上沉積第一導電接合層；在基底上沉積第二導電接合層；以及將所述第二晶粒接合至所述基底，其中將所述第二晶粒接合至所述基底包括使所述第一導電接合層與所述第二導電接合層直接接觸並且形成第二金屬對金屬接合。
  9. 如請求項8之積體電路的製作方法，更包括：在沉積所述絕緣材料之前，將散熱構件直接接合至所述第一晶粒，其中沉積所述絕緣材料包括沉積環繞所述散熱構件的所述絕緣材料。
  10. 如請求項8之積體電路的製作方法，更包括：使所述第一晶粒的半導體基底凹陷以低於穿孔的頂表面，所述穿孔延伸穿過所述半導體基底；以及沉積環繞所述穿孔的介電層，其中將第一晶粒直接接合至第二晶粒包括將第二晶粒的鈍化層直接接合至所述介電層。
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